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2015-03-12Fixes a problem generating relocs for thumb function calls to local symbols ↵Nick Clifton2-7/+11
defined in other sections. PR gas/17444 * config/tc-arm.h (MD_APPLY_SYM_VALUE): Pass the current segment to arm_apply_sym_value. Update prototype. * config/tc-arm.c (arm_apply_sym_value): Add segment argument. Do not apply the value if the symbol is in a different segment to the current segment.
2015-03-11Fix powerpc gas abort on invalid instruction fixupsAlan Modra1-3/+23
* config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups. (md_apply_fix): Report an error on data-only fixups used with insns.
2015-03-10S/390: Add check for length field operandAndreas Krebbel1-0/+3
gas/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/config/tc-s390.c (md_gather_operands): Check for valid length field operands.
2015-03-10Fixes a bug in the ARM port of GAS when parsing inverted register lists.Michael Perkins1-1/+3
* config/tc-arm.c (parse_operands): Fix bug setting writeback values for '^' on OP_REGLSTs. (do_push_pop): Add new writeback constraint.
2015-03-10[ARM]Fix "align directive causes MAP_DATA symbol to be lost"Sterling Augustine1-17/+13
gas/ 2015-03-10 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code. (mapping_state_2): Emit first MAP_DATA symbol here. gas/testsuite/ 2015-03-05 Renlin Li <renlin.li@arm.com> * gas/arm/dis-data.d: Adjust the desired output. * gas/arm/dis-data2.d: Ditto.
2015-03-10[AArch64] Set the minimum alignment on code segmentsJiong Wang1-1/+8
gas/ 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (mapping_state): Set minimum alignment for code sections. gas/testsuite 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/codealign.d: Add test for code section alignment. * gas/aarch64/codealign.s: New file.
2015-03-10Fixes a bug building the ARM Linux kernel with a toolchain compiled with ↵Nick Clifton1-0/+2
CPU_DEFAULT set. PR gas/17852 * config/tc-arm.c (md_begin): Ensure that selected_cpu is initialised when CPU_DEFAULT is defined.
2015-03-05Fixes a thinko in the implementation of the V850 -m8byte-align and ↵Nick Clifton1-6/+8
-m4byte-align command line options. * config/tc-v850.c (md_parse_option): Fix code to set or clear EF_RH850_DATA_ALIGN8 bit in ELF header, based upon the use of the -m8byte-align and -m4byte-align command line options.
2015-03-04Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NCRichard Sandiford1-2/+0
bfd/ PR gas/17843 * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC to be used with MOVK rather than MOVZ. gas/ PR gas/17843 * config/tc-aarch64.c (process_movw_reloc_info): Allow R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC for MOVK. gas/testsuite/ PR gas/17843 * gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC sequence. ld/testsuite/ PR gas/17843 * ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test. * ld-aarch64/aarch64-elf.exp: Run it.
2015-02-26[AArch64] Add support for :tlsdesc: and TLSDESC_LD_PREL19Marcus Shawcroft1-1/+3
2015-02-26[AArch64] Add support for :tlsdesc: and TLSDESC_ADR_PREL21Marcus Shawcroft1-1/+3
2015-02-26Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support.Marcus Shawcroft1-1/+3
2015-02-26Adding support for TLSIE_LD_GOTTREL_PREL19.Marcus Shawcroft1-1/+3
2015-02-26Adding ld_literal_type.Marcus Shawcroft1-5/+36
Extend the address modifier parsing to distinguish between the modifers used in LDR literal and LDR register offset address modes. The current parser incorrectly accepts the :got: modifier on a register offset instruction resulting in silent corruption of the output binary.
2015-02-26Adding adr_type and prevent adr :got:Marcus Shawcroft1-3/+47
The current implementation of the :got: assembler modifier does not distinguish the ADR and ADRP instruction. The :got: modifier does not make sense on and ADR instruction and should be error'd rather than the current behavior of applying an inappropriate relocation to the output and scrambling the underlying instruction silently.
2015-02-26Remove dead code.Marcus Shawcroft1-3/+0
2015-02-25avr/gas: Write out data to track .org/.align usage.Andrew Burgess2-0/+354
Adds support to the assembler to write out data for tracking the use of .org and .align directives. This data is collected within the assembler and written out to a section ".avr.prop" (if there's anything to write out). This patch does not add any tests. The next patch in this series will add a better mechanism for visualising the contents of .avr.prop which will make writing tests much easier. This patch also does not make any use of this collected data, that will also come along in a later patch; the intended consumer is the linker, during linker relaxation this information will be used to ensure that the .org and .align directives are honoured. bfd/ChangeLog: * elf32-avr.h (AVR_PROPERTY_RECORD_SECTION_NAME): Define. (AVR_PROPERTY_RECORDS_VERSION): Define. (AVR_PROPERTY_SECTION_HEADER_SIZE): Define. (struct avr_property_record): New structure. gas/ChangeLog: * config/tc-avr.c: Add elf32-avr.h include. (struct avr_property_record_link): New structure. (avr_output_property_section_header): New function. (avr_record_size): New function. (avr_output_property_record): New function. (avr_create_property_section): New function. (avr_handle_align): New function. (exclude_section_from_property_tables): New function. (create_record_for_frag): New function. (append_records_for_section): New function. (avr_create_and_fill_property_section): New function. (avr_post_relax_hook): New function. * config/tc-avr.h (md_post_relax_hook): Define. (avr_post_relax_hook): Declare. (HANDLE_ALIGN): Define. (avr_handle_align): Declare. (strut avr_frag_data): New structure. (TC_FRAG_TYPE): Define.
2015-02-24Adds support for generating notes in V850 binaries.Nick Clifton2-0/+91
bfd * elf32-v850.c (v850_set_note): New function. Creates a Renesas style note entry. (v850_elf_make_note_section): New function. Creates a note section. (v850_elf_create_sections): New function. Create a note section if one is not already present. (v850_elf_set_note): New function. Adds a note to a bfd. (v850_elf_copy_private_bfd_data): New function. Copies V850 notes. (v850_elf_merge_notes): New function. Merges V850 notes. (print_v850_note): New function. Displays a V850 note. (v850_elf_print_notes): New function. Displays all notes attached to a bfd. (v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes. (v850_elf_print_private_bfd_data): Call v850_elf_print_notes. (v850_elf_fake_sections): Set the type of the V850 note section. * bfd-in.h (v850_elf_create_sections): Add prototype. (v850_elf_set_note): Add prototype. * bfd-in2.h: Regenerate. binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine flags. (get_v850_section_type_name): New function. Handles V850 special sections. (get_section_type_name): Add support for V850. (get_v850_elf_note_type): New function. Returns the name of a V850 note. (print_v850_note): New function. Prints a V850 note. (process_v850_notes): New function. Prints V850 notes. (process_note_sections): Add support for V850. binutils/testsute * binutils-all/objcopy.exp: Skip the strip-10 test for the V850. gas * config/tc-v850.c (soft_float): New variable. (v850_data_8): New variable. (md_show_usage): Add -msoft-float/-mhard-float. (md_parse_option): Likewise. (md_begin): Set the default value of soft_float. (v850_md_end): New function. Creates a note section. * config/tc-v850.h (md_end): Define. * doc/c-v850.texi: Document -msoft-float/-mhard-float. gas/testsuite * gas/elf/elf.exp: Add special version of the section2 test for the V850. * gas/elf/section2.e-v850: New file. include/elf * v850.h (EF_RH850_SIMD): Delete deprecated flag. (EF_RH850_CACHE): Likewise. (EF_RH850_MMU): Likewise. (EF_RH850_DATA_ALIGN8): Likewise. (SHT_RENESAS_IOP): Fix typo in name. (SHT_RENESAS_INFO): Define. (V850_NOTE_SECNAME): Define. (SIZEOF_V850_NOTE): Define. (V850_NOTE_NAME): Define. (enum v850_notes): New enum. (NUM_V850_NOTES): Define. ld/ChangeLog 2015-02-24 Nick Clifton <nickc@redhat.com> * Makefile.am (ev850.c): Add dependency upon $(srcdir)/emultempl/v850elf.em. (ev850_rh850.c): Likewise. * Makefile.in: Regenerate. * emultempl/v850elf.em: New file. * emulparams/v850.sh (EXTRA_EM_FILE): Define. * emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define. * scripttempl/v850.sc: Add .note.renesas section. * scripttempl/v850_rh850.sc: Likewise. ld/testsuite * ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
2015-02-23Add support for the h8300-linux target.Yoshinori Sato2-4/+111
ld * Makefile.am: (ALL_EMULATION_SOURCES): Add new emulations. * Makefile.in: Regenerate. * configure.tgt: Add h8300-*-linux * emulparams/h8300elf_linux.sh: Add new emulation. * emulparams/h8300helf_linux.sh: Likewise. * emulparams/h8300self_linux.sh: Likewise. * emulparams/h8300sxelf_linux.sh: Likewise. bfd * config.bfd: Add h8300-*-linux. * configure.ac: Add h8300_elf32_linux_vec. * configure: Regenerate. * elf32-h8300.c: Likewise. * targets.c(_bfd_target_vector): Likewise. gas * config/tc-h8300.c (line_separater_chars): Add a version for h8300-linux that includes a separator. (default_mach): New variable. (md_main): Use it. (md_longopts): Add '--march' option. (md_parse_option): Parse the new option. * config/tc-h8300.h (TARGET_FORMAT): Add elf32-h8300-linux. * configure.tgt: Add h8300-*-linux * doc/c-h8300.texi: Document --march.
2015-02-23Fixes the generation of dwarf line debug information for the msp430, even in ↵Nick Clifton1-2/+3
the presence of function sections and linker garbage collection. PR 17940 * dwarf2dbg.c (out_header): When generating dwarf sections use real symbols not temps for the start and end symbols. * config/tc-msp430.h (TC_FORCE_RELOCATION_SUB_SAME): Also prevent adjustments to relocations in debug sections. (TC_LINKRELAX_FIXUP): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Adjust debug symbols at end of sections. Adjust function sizes.
2015-02-11[AArch64] Fix code formatting in the cpu-tableJiong Wang1-6/+6
2015-02-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
2015-02-11[ARM] Add support for Cortex-A72Jiong Wang1-0/+2
2015-02-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c: Add support for Cortex-A72.
2015-02-09[ARM][gas] Use as_tsktsk instead of as_warn for deprecation messages.Kyrylo Tkachov1-15/+15
* config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead of as_warn for deprecation messages. (encode_arm_addr_mode_2): Likewise. (check_obsolete): Likewise. (do_rd_rm_rn): Likewise. (do_co_reg): Likewise. (do_setend): Likewise. (do_t_mov_cmp): Likewise. (do_neon_ldr_str): Likewise. (opcode_lookup): Likewise. (if_fsm_post_encode): Likewise. (md_assemble): Likewise. * gas/arm/armv1.l: Remove 'Warning: ' from expected messages for deprecations. * gas/arm/armv8-a-bad.l: Likewise. * gas/arm/armv8-a-it-bad.l: Likewise. * gas/arm/depr-swp.l: Likewise. * gas/arm/ldsgeb.l: Likewise. * gas/arm/ldsgeh.l: Likewise. * gas/arm/thumb2_bad_reg.l: Likewise. * gas/arm/thumb32.l: Likewise. * gas/arm/udf.l: Likewise. * gas/arm/vstr-arm-bad.l: Likewise.
2015-02-05Fix msp430 build with gcc-5Alan Modra1-2/+2
gcc-5 correctly complains "loop exit may only be reached after undefined behavior". I was going to correct this by checking the index before dereferencing the array rather than the other way around, but then I noticed it is possible for extract_cmd to write the terminating zero one past the end of "cmd". Fixing that means no index check is needed in md_assemble. * config/tc-msp430.c (md_assemble): Correct size passed to extract_cmd. Remove index check.
2015-02-04[AArch64] Add support for Cortex-A72Jiong Wang1-0/+2
2015-02-04 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72. * doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
2015-02-04Fix encoding of "addw ax, [hl]" and "subw ax, [hl]".Nick Clifton1-1/+1
* config/rl78-parse.y (addsubw): Fix encoding of [HL] variant of these instructions.
2015-02-03Fix use of uninitialised memory by the RL78 port of GAS.Nick Clifton1-0/+3
* config/tc-rl78.h (TC_PARSE_CONS_EXPRESSION): Define.
2015-01-29NDS32: Set branch instruction to relaxable.Kuan-Lin Chen2-166/+277
Relaxable fragments can be relaxed when there are alignment requirements. Besides, insert a dummy fragment in the final to make sure that all alignment is traversed. Finally, convert these fragments in md_convert_frag with relax_table.
2015-01-28FT32 initial supportAlan Modra2-0/+661
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2015-01-27NDS32/gas: Limit the format of pseudo instruction la.Kuan-Lin Chen1-1/+10
2015-01-27NDS32/gas: Fix md_parse_name hook.Kuan-Lin Chen1-0/+7
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel1-124/+78
- 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-13[ARM] vcmp/vcmpe should accept #0x0 as an operandJiong Wang1-0/+10
gas/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for #0, restoring previous behaviour. gas/testsuite/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/ual-vcmp.s: Add vcmp, vcmpe with #0x0 operand. * gas/ual/vcmp.d: Update expected output. * gas/ual/vcmp-zero-bad.l: Likewise
2015-01-12arm: properly range check immediate operands of VSHL and VQSHLJan Beulich1-3/+9
These two, other than VQSHLU, didn't have their immediates properly range checked so far. (Re-sending unchanged from the original v2 due to never having got an answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.) gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range. (do_neon_qshl_imm): Likewise. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/arm/neon-addressing-bad.s: Add test for invalid VSHL, VQSHL, and VQSHLU immediates. * gas/arm/neon-addressing-bad.l: Update accordingly.
2015-01-10gas/avr: Prevent incorrect overflow errors for diff fixups.Andrew Burgess1-0/+1
When fixups are converted to a difference type within md_apply_fix, we previously left the contents of VALP (the value that was initially computed within write.c:fixup_segment) unchanged. This is harmless, except that this value is used within write.c:fixup_segment once we return from md_apply_fix to perform an overflow check. In some cases, the value computed in write.c:fixup_segment is so wrong that an overflow error can be triggered. These errors are incorrect. This patch avoids the overflow errors by adjusting the value in write.c:fixup_segment using the VALP pointer in md_apply_fix. A test for this issue is included. gas/ChangeLog: * config/tc-avr.c (md_apply_fix): Update the contents of VALP for diff fixups. gas/testsuite/ChangeLog: * gas/avr/large-debug-line-table.d: New file. * gas/avr/large-debug-line-table.s: New file.
2015-01-09This patch adds the necessary support to the assembler to allow wiringPhilipp Tomsich1-0/+5
the X-Gene scheduling description up in the respective GCC backend. * config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and X-Gene 2. * doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
2015-01-07arm: fix extension feature disablingJan Beulich1-15/+27
Using e.g. .arch_extension simd .arch_extension nocrypto so far results in SIMD support getting disabled, which I can't see being the purpose of the "no"-prefixed variants of architecture extension specifications. Of course it is questionable whether the current, counter intuitive behavior needs to be retained, and the new behavior perhaps be made work through e.g. a newly recognized "no-" prefix. gas/ 2015-01-07 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (struct arm_option_extension_value_table): Split field "value" into fields "merge_value" and "clear_value". (arm_extensions): Adjust initializer accordingly.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra236-236/+236
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green1-8/+8
2014-12-25Don't pass unadorned zeros to varargs functionsYaakov Selkowitz1-2/+2
PR gas/17753 * config/tc-mep.c (md_begin): Specify types of vararg literals.
2014-12-24AVR: Assembler now prepares for linker relaxation by default.Andrew Burgess1-8/+16
Have the assembler prepare for linker relaxation by default. This means that users will be able to make use of linker relaxation without having to adjust the assembler flags, this can make life easier when compiling libraries. Having this on by default in the assembler should make no difference to the assembler code produced, however, some of the debug information will be slightly less compressed. A few tests needed to be updated as a result of this change as they relied on linker relaxation support being off by default. I've tightened up the definition of which sections can be relaxed on AVR as part of this commit, the assembler used to think that all non-debugging sections could be relaxed, when in reality only code sections can be relaxed for AVR. The previous definition was not dangerous, just over cautious. The new tighter definition allows an extra test (gas/testsuite/gas/all/forward.d) to continue to pass. gas/ChangeLog: * config/tc-avr.c (struct avr_opt_s): Change link_relax to no_link_relax, extend comment. (enum options): Add new OPTION_NO_LINK_RELAX. (md_longopts): Add entry for -mno-link-relax. (md_parse_option): Handle OPTION_NO_LINK_RELAX, and update OPTION_LINK_RELAX. (md_begin): Initialise linkrelax from no_link_relax. (md_show_usage): Include -mno-link-relax option. (relaxable_section): Only allocatable code sections can be relaxed. * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define. gas/testsuite/ChangeLog: * gas/all/gas.exp: Test will not pass on AVR due to linker relaxation support. * gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option. * gas/avr/link-relax-elf-flag-clear.d: Likewise. ld/testsuite/ChangeLog: * ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax option. * ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
2014-12-23AVR: Only set link-relax elf flag when appropriate.Andrew Burgess2-1/+11
The AVR target uses a bit in the elf header flags to indicate if the object was assembled ready for linker relaxation. Previously this flag was always set, even when the object was not assembled ready for linker relaxation. This patch moves setting of the flag into the assembler, and sets it only when the assembler is preparing the file for linker relaxation. bfd/ChangeLog: * elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set EF_AVR_LINKRELAX_PREPARED unconditionally. gas/ChangeLog: * config/tc-avr.c: Add include for elf/avr.h. (avr_elf_final_processing): New function. * config/tc-avr.h (elf_tc_final_processing): Define. (avr_elf_final_processing): Declare gas/testsuite/ChangeLog: * gas/avr/link-relax-elf-flag-clear.d: New file. * gas/avr/link-relax-elf-flag-set.d: New file. * gas/avr/link-relax-elf-flag.s: New file.
2014-12-23This patch add support for cpu marvell-whitney.Nick Clifton1-0/+3
* gas/config/tc-arm.c (arm_cpus): Add core marvell-whitney.
2014-12-19Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.Matthew Fortune1-4/+8
gas/ * config/tc-mips.c (md_apply_fix): Apply alignment check to the symbol and offset rather than *valP for BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message for BFD_RELOC_MIPS_19_PCREL_S2. gas/testsuite/ * gas/mips/r6-64.s: Remove .align directives from LDPC instructions and add further tests for LDPC. * gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected output and update for new tests. * gas/mips/r6-64-n64.d: Likewise. * gas/mips/ldpc-unalign.l: New file. * gas/mips/ldpc-unalign.s: Likewise. * gas/mips/mips.exp: Run ldpc-unalign test.
2014-12-14Compress debug sections for Linux/x86 by defaultH.J. Lu1-0/+5
* config/tc-i386.c (flag_compress_debug): Default to compress debug sections for Linux.
2014-12-13PowerPC register numbers in DWARFAlan Modra2-2/+37
This makes gas .cfi output to .debug_frame match register numbering emitted by gcc. md_reg_eh_frame_to_debug_frame follows the ABI, targets not using it, notably Linux, don't. * config/tc-ppc.h (md_reg_eh_frame_to_debug_frame): Match current gcc behaviour. * config/te-aix.h: New file. * configure.tgt: Use em=aix for powerpc-aix.
2014-12-09Ensure zero termination of tic4x insn bufferChen Gang1-3/+5
* config/tc-tic4x.c (md_assemble): Ensure insn->name is zero terminated. Simplify concatenation of parallel insn.
2014-12-06Add Visium support to gasEric Botcazou2-0/+2387
gas/ * configure.tgt: Add Visium support. * Makefile.am (TARGET_CPU_CFILES): Move config/tc-vax.c around and add config/tc-visium.c. (TARGET_CPU_HFILES): Move config/tc-vax.h around and add config/tc-visium.h. * Makefile.in: Regenerate. * config/tc-visium.c: New file. * config/tc-visium.h: Likewise. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/elf/elf.exp: Skip ifunc-1 for Visium. * gas/visium/: New directory.
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore1-137/+0
2014-11-28 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. (NIOS2_INSN_OPTARG): Renumber. opcodes/ * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes from descriptors. gas/ * config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete. (output_addi, output_andi, output_ori, output_xori): Delete. (md_assemble): Remove calls to deleted functions. gas/testsuite/ * gas/nios2/nios2.exp: Make "movi" a list test. * gas/nios2/movi.s: Adjust comments, add another case. * gas/nios2/movi.l: New. * gas/nios2/movi.d: Delete.
2014-11-26Fix trampolines search code for conditional branchesMax Filippov1-4/+4
For conditional branches that need more than one trampoline to reach its target assembler couldn't always find suitable trampoline because post-loop condition check was placed inside the loop, resulting in premature loop termination. Move check outside the loop. This fixes the following build errors seen when assembling huge files produced by gcc: Error: jump target out of range; no usable trampoline found Error: operand 1 of 'j' has out of range value '307307' 2014-11-25 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (search_trampolines): Move post-loop condition check outside the search loop. gas/testsuite/ * gas/xtensa/trampoline.d: Add expected output for branches. * gas/xtensa/trampoline.s: Add test case for branches.
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