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AgeCommit message (Expand)AuthorFilesLines
2023-04-19x86: parse_register() must not alter the parsed stringJan Beulich1-13/+9
2023-04-19x86: parse_real_register() does not alter the parsed stringJan Beulich1-4/+4
2023-04-18Symbols with GOT relocatios do not fix adjustbalemengqinggang1-0/+15
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-0/+1
2023-04-03ubsan: aarch64 parse_vector_reg_listAlan Modra1-4/+4
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-17/+47
2023-03-31x86: handle immediate operands for .insnJan Beulich2-3/+108
2023-03-31x86: allow for multiple immediates in output_disp()Jan Beulich1-5/+5
2023-03-31x86: handle EVEX Disp8 for .insnJan Beulich1-1/+97
2023-03-31x86: process instruction operands for .insnJan Beulich2-21/+302
2023-03-31x86: parse special opcode modifiers for .insnJan Beulich1-1/+38
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich1-6/+238
2023-03-31x86: introduce .insn directiveJan Beulich1-10/+155
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+5
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-3/+14
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-1/+2
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-9/+64
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-14/+71
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+8
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-3/+32
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-0/+23
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-1/+32
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-1/+1
2023-03-30aarch64: Add +sme2Richard Sandiford1-0/+2
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford1-5/+7
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-20/+38
2023-03-30aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford1-71/+71
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-2/+1
2023-03-30aarch64: Tweak priorities of parsing-related errorsRichard Sandiford1-5/+45
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-0/+4
2023-03-30aarch64: Tweak register list errorsRichard Sandiford1-4/+2
2023-03-30aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford1-20/+34
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-0/+8
2023-03-30aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford1-3/+3
2023-03-30aarch64: Update operand_mismatch_kind_namesRichard Sandiford1-0/+2
2023-03-30aarch64: Rework reporting of failed register checksRichard Sandiford1-118/+282
2023-03-30aarch64: Try to avoid inappropriate default errorsRichard Sandiford1-4/+17
2023-03-30aarch64: Improve errors for malformed register listsRichard Sandiford1-13/+22
2023-03-30aarch64: Tweak parsing of integer & FP registersRichard Sandiford1-29/+42
2023-03-30aarch64: Tweak errors for base & offset registersRichard Sandiford1-3/+11
2023-03-30aarch64: Tweak error for missing immediate offsetRichard Sandiford1-3/+3
2023-03-30aarch64: Move w12-w15 range check to libopcodesRichard Sandiford1-9/+6
2023-03-30aarch64: Commonise index parsingRichard Sandiford1-21/+21
2023-03-30aarch64: Consolidate ZA slice parsingRichard Sandiford1-72/+22
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-77/+4
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