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AgeCommit message (Expand)AuthorFilesLines
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner1-38/+26
2018-05-04-Wstringop-truncation warningsAlan Modra2-9/+11
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-40/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+40
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-17/+54
2018-04-26x86: also optimize zeroing-masking variants of insnsJan Beulich1-1/+1
2018-04-26x86: properly force / avoid forcing EVEX encodingJan Beulich1-7/+5
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-11/+13
2018-04-26x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich1-0/+3
2018-04-26x86: x87-related adjustmentsJan Beulich1-6/+5
2018-04-26x86: fix indentation in build_modrm_byte()Jan Beulich1-39/+39
2018-04-26x86: move and fold common code in build_modrm_byte()Jan Beulich1-29/+13
2018-04-26x86: drop VexImmExtJan Beulich1-7/+3
2018-04-26x86: tighten assertion in build_modrm_byte()Jan Beulich1-4/+3
2018-04-26x86: drop dead code from build_modrm_byte()Jan Beulich1-19/+4
2018-04-25[ARM] Add TLS relocations for FDPIC.Christophe Lyon1-1/+25
2018-04-25[ARM] Add FDPIC relocations definitionsChristophe Lyon1-1/+26
2018-04-25[ARM] Add FDPIC OSABI flag support.Christophe Lyon1-3/+31
2018-04-25Remove arm-aout and arm-coff supportAlan Modra3-73/+2
2018-04-23Silence gcc-8 warningsAlan Modra2-4/+8
2018-04-20RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson1-0/+14
2018-04-18various i386-aout and i386-coff target removalAlan Modra5-187/+0
2018-04-17[MicroBlaze] PIC data text relativeMichael Eager1-9/+36
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-0/+2
2018-04-16Fix illegal memory accesses in the assembler when attempting to parse corrup ...Nick Clifton1-1/+2
2018-04-16Remove arm-epoc-pe supportAlan Modra2-30/+1
2018-04-16Remove sparc-aout and sparc-coff supportAlan Modra4-264/+6
2018-04-16Remove m68k-aout and m68k-coff supportAlan Modra4-285/+4
2018-04-16Remove sh5 and sh64 supportAlan Modra3-4309/+5
2018-04-16Remove sh-symbianelf supportAlan Modra2-10/+0
2018-04-16Remove i370 supportAlan Modra3-2738/+0
2018-04-16Remove h8500 supportAlan Modra1-5/+0
2018-04-16Remove h8300-coff supportAlan Modra3-54/+5
2018-04-16Remove netware supportAlan Modra2-29/+0
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-0/+2
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra10-4936/+5
2018-03-30Make power8 the default cpu when assembling for 64-bit little endian targets.Peter Bergner1-1/+5
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-6/+46
2018-03-28x86: drop VecESizeJan Beulich1-14/+12
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-25/+45
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-2/+6
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+20
2018-03-22x86: use local variable in check_VecOperands()Jan Beulich1-7/+8
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich1-0/+8
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-2/+5
2018-03-22x86: fold a few XOP templatesJan Beulich1-4/+8
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson1-6/+11
2018-03-14RISC-V: Add .insn support.Jim Wilson1-27/+413
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu1-1/+2
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu1-0/+6
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