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2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu1-379/+262
Add option parser for disassembler, and refine the codes of parse register operand and disassemble register operand. While strengthen the operands legality check of some instructions. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (parse_type_ctrlreg): Use function csky_get_control_regno to operand. (csky_get_reg_val): Likewise. (is_reg_sp_with_bracket): Use function csky_get_reg_val to parse operand. (is_reg_sp): Refine. (is_oimm_within_range): Fix, report error when operand is not constant. (parse_type_cpreg): Refine. (parse_type_cpcreg): Refine. (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS. (md_assemble): Fix no error reporting somtimes when operands number are not fit. (csky_addc64): Refine. (csky_subc64): Refine. (csky_or64): Refine. (v1_work_fpu_fo): Refine. (v1_work_fpu_read): Refine. (v1_work_fpu_writed): Refine. (v1_work_fpu_readd): Refine. (v2_work_addc): New function, strengthen the operands legality check of addc. * gas/testsuite/gas/csky/all.d : Use register number format when disassemble register name by default. * gas/testsuite/gas/csky/cskyv2_all.d : Likewise. * gas/testsuite/gas/csky/trust.d: Likewise. * gas/testsuite/gas/csky/cskyv2_ck860.d : Fix. * gas/testsuite/gas/csky/trust.s : Fix. opcodes/ * csky-dis.c (using_abi): New. (parse_csky_dis_options): New function. (get_gr_name): New function. (get_cr_name): New function. (csky_output_operand): Use get_gr_name and get_cr_name to disassemble and add handle of OPRND_TYPE_IMM5b_LS. (print_insn_csky): Parse disassembler options. * opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum. (GENARAL_REG_BANK): Define. (REG_SUPPORT_ALL): Define. (REG_SUPPORT_ALL): New. (ASH): Define. (REG_SUPPORT_A): Define. (REG_SUPPORT_B): Define. (REG_SUPPORT_C): Define. (REG_SUPPORT_D): Define. (REG_SUPPORT_E): Define. (csky_abiv1_general_regs): New. (csky_abiv1_control_regs): New. (csky_abiv2_general_regs): New. (csky_abiv2_control_regs): New. (get_register_name): New function. (get_register_number): New function. (csky_get_general_reg_name): New function. (csky_get_general_regno): New function. (csky_get_control_reg_name): New function. (csky_get_control_regno): New function. (csky_v2_opcodes): Prefer two oprerans format for bclri and bseti, strengthen the operands legality check of addc, zext and sext.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-1/+9
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-21PR26569, R_RISCV_RVC_JUMP results in buffer overflowAlan Modra1-3/+7
This patch corrects "size" and "bitsize" in R_RISCV_RVC_* reloc howtos so that elfnn-riscv.c:perform_relocation doesn't access past the end of a section. I've also corrected "size" in the R_RISCV_CALL* reloc howtos since these relocs apply to two consecutive instructions. That caused fallout in the assembler with complaints about "fixup not contained within frag" due to tc-riscv.c:append_insn finishing off a frag after the auipc insn making up a "call" macro. Which is a little rude since the CALL reloc also relocates the following jalr. Fixed by changing the frag handling a little. I've also changed R_RISCV_ALIGN and R_RISCV_TPREL_ADD marker reloc howtos to look like R_RISCV_NONE, and corrected dst_mask for numerous relocs, not that it matters very much. bfd/ PR 26569 * elfxx-riscv.c (howto_table): Correct size and bitsize of R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, and R_RISCV_RVC_LUI. Correct size for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPREL32, R_RISCV_CALL, and R_RISCV_CALL_PLT. Make R_RISCV_TPREL_ADD and R_RISCV_ALIGN like R_RISCV_NONE. Correct dst_mask many relocs. gas/ * config/tc-riscv.c (append_insn): Don't tie off frags at CALL relocs. (riscv_call): Tie them off after the jalr. (md_apply_fix): Zero fx_size of RELAX fixup.
2020-09-16Tidy elf_symbol_fromAlan Modra5-11/+8
bfd/ * elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter. * elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data), (swap_out_syms): Adjust elf_symbol_from invocation. binutils/ * nm.c (print_symbol): Adjust elf_symbol_from invocation. * objcopy.c (is_hidden_symbol): Likewise. gas/ * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust elf_symbol_from invocation. * config/tc-aarch64.c (s_variant_pcs): Likewise. * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise. * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation), (ppc_fix_adjustable): Likewise. * config/tc-xgate.c (xgate_frob_symbol): Likewise. ld/ * plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from invocation. opcodes/ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
2020-09-15PR26610, ARM's "VFPv3 vldr to vmov" gas testcase failAlan Modra1-19/+20
I removed a few too many parentheses in git commit 7af677524e2. This patch fixes that problem, rewriting the expression so it won't happen again. The patch also avoids more UB with shifts of signed values. PR 26610 * config/tc-arm.c (move_or_literal_pool): Correct extraction of bignum. Use unsigned "v" (is_double_a_single): Make "v" and "mantissa" unsigned. Formatting. (double_to_single): Likewise.
2020-09-15Fix the assembler's new .nop directive so that the input line pointer is ↵Nick Clifton1-6/+3
preserved. * read.c (s_nop): Preserve the input_line_pointer around the call to md_assemble. * config/tc-s12z.c (md_assemble): Revert previous delta.
2020-09-15Change the /nop directive for the BPF port of the assembler to use the ↵David Faust1-1/+3
encoding expected by the kernel. * config/tc-bpf.h (md_single_noop_insn): Use 'ja 0' for no-op.
2020-09-14Fix support for theassembler's new ".nop" directive on the IA64 target.Nick Clifton1-0/+2
* config/tc-ia64.h (md_single_noop_insn): Define.
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op ↵Nick Clifton4-3/+11
instructions in an architeture neutral manner. * read.c (s_nop): New function. Handles the .nop directive. (potable): Add entry for "nop". (s_nops): Code tidy. * read.h (s_nop): Add prototype. * config/tc-bpf.h (md_single_noop_insn): Define. * config/tc-mmix.h (md_single_noop_insn): Define. * config/tc-or1k.h (md_single_noop_insn): Define. * config/tc-s12z.c (md_assemble): Preserve the input line pointer, rather than corrupting it. * write.c (relax_segment): Update error message regarding non-absolute values passed to .fill and .nops. * NEWS: Mention the new directive. * doc/as.texi: Document the new directive. * doc/internals.texi: Document the new internal macros used to implement the new directive. * testsuite/gas/all/nop.s: New test. * testsuite/gas/all/nop.d: New test control file. * testsuite/gas/all/gas.exp: Run the new test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test control file. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/space1.l: Adjust expected output.
2020-09-14CSKY: Set feature flags for default cpu.Cooper Qu1-3/+2
Fix floating point instructions not recognized when building GCC. gas/ PR 26608 * config/tc-csky.c (md_begin): Set feature flags for default cpu.
2020-09-10CSKY: Enable extend lrw by default for CK802, CK803 and CK860.Cooper Qu1-1/+4
gas/ * config/tc-csky.c (md_begin): Enable extend lrw by default for CK802, CK803 and CK860.
2020-09-10CSKY: Add new arches while refine the cpu option process.Cooper Qu1-172/+435
Add arches CK804, CK805 and CK800. CK800 is an special arch which support all instructions for CSKYV2. Refine the cpu tables to simplify adding a new cpu. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (struct csky_cpu_info): Add new members isa_flag, features and ver. (struct csky_cpu_feature): New. (struct csky_cpu_version): New. (CSKY_FEATURE_MAX): Define. (CSKY_CPU_REVERISON_MAX): Define. (FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP, FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD): Define, each standard one collection of instructions. (CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e, CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v, CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt, CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv, CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d, CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft, CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv, CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv, CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define, the features combination used by cpu. (CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0, CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0, CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3): Define, version information used by cpu. (csky_cpus): Refine, and add CK804, CK805 and CK800. (parse_cpu): Refine. (parse_arch): Refine. (md_show_usage): Refine. (md_begin): Refine. include/ * opcode/csky.h (CSKY_ARCH_804): Define. (CSKY_ARCH_805): Define. (CSKY_ARCH_800): Define.
2020-09-09power10 on ppc32Alan Modra1-1/+2
We don't support power10 on ppc32, mainly because some instructions have 34-bit fields for which we don't have relocations on ppc32. If you try to assemble typical code, you'll see errors saying "reloc ... not supported by object file format". Also, on 32-bit hosts with binutils configured without a 64-bit bfd, you'll see errors saying "bignum invalid" when using large offsets. But let's not kill output of prefix insns entirely on 32-bit hosts. * config/tc-ppc.c (md_assemble): Emit prefix insn by parts when valueT is smaller than 64 bits.
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu1-2/+2
gas/ * config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60. (CSKY_ISA_860): Likewise. include/ * opcode/csky.h (CSKY_ISA_DSPE60): Define. opcodes/ * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's ISA flag.
2020-09-09CSKY: Support option -mfloat-abi.Cooper Qu1-0/+57
The option corresponds to GCC to control the float calling conversion, and the value will be stored in .csky.attributes section. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (float_abi): New. (md_longopts): Add mfloat-abi. (struct sky_option_value_table): New. (csky_float_abis): New, the possible values for -mfloat-abi. (parse_float_abi): New funtion. (md_show_usage): Show help information for -mfloat-abi. (set_csky_attribute): Store float-abi value.
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu1-31/+189
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (float_work_fpuv3_fmovi): New function, helper function to encode fpuv3 fmovi instructions. (float_work_fpuv3_fstore): New function. (struct literal): Add new member 'offset'. (csky_cpus): New cpu CK860f. (enter_literal): Return literal pool pointer instead of offset. (parse_rt): Adjust the change of enter_literal. (parse_rtf): Likewise. (v1_work_lrw): Likewise. (v1_work_jbsr): Likewise. (v2_work_lrw): Likewise. (v2_work_jbsr): Likewise. (v2_work_jsri): Likewise. (vdsp_work_vlrw): Likewise. (is_freglist_legal): Add handler for FPUV3. (parse_type_freg): Likewise. (is_imm_within_range): Set e.X_add_number if it is a signed and negtive number. (get_operand_value): Add handler for OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (float_to_half): Convert float number to harf float. opcodes/ * csky-dis.c (csky_output_operand): Add handlers for OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH to support FPUV3 instructions. * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8, OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24, OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22, OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25, OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25, OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21, OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24, OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25, OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20, OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25, OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24, OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20, OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define. (csky_v2_opcodes): Add FPUV3 instructions. include/ * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
2020-09-08MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz1-1/+53
Link-time relaxations of branches are common for MSP430, given that GCC can generate pessimal branch instructions, and the -mcode-region=either/-mdata-region=either options to shuffle sections can further change the type of branch instruction required. These relaxations can result in invalid code when .uleb128 directives, used in the .gcc_except_table section, are used to calculate the distance between two labels. A value for the .uleb128 directive is calculated at assembly-time, and can't be updated at link-time, even if relaxation causes the distance between the labels to change. This patch adds relocations for subtract expressions in .uleb128 directives, to allow the linker to re-calculate the value of these expressions after relaxation has been performed. bfd/ChangeLog: * bfd-in2.h (bfd_reloc_code_real): Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128. * elf32-msp430.c (msp430_elf_ignore_reloc): New. (elf_msp430_howto_table): Add R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. (msp430_reloc_map): Add R_MSP430_GNU_{SET,SUB}_ULEB128. (msp430x_reloc_map): Add R_MSP430X_GNU_{SET,SUB}_ULEB128. (write_uleb128): New. (msp430_final_link_relocate): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. * libbfd.c (_bfd_write_unsigned_leb128): New. * libbfd.h (_bfd_write_unsigned_leb128): New prototype. Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128. * reloc.c: Document BFD_RELOC_MSP430_{SET,SUB}_ULEB128. binutils/ChangeLog: * readelf.c (target_specific_reloc_handling): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. gas/ChangeLog: * config/tc-msp430.c (msp430_insert_uleb128_fixes): New. (msp430_md_end): Call msp430_insert_uleb128_fixes. include/ChangeLog: * elf/msp430.h (elf_msp430_reloc_type): Add R_MSP430_GNU_{SET,SUB}_ULEB128. (elf_msp430x_reloc_type): Add R_MSP430X_GNU_{SET,SUB}_ULEB128. ld/ChangeLog: * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests. * testsuite/ld-msp430-elf/uleb128.s: New test. * testsuite/ld-msp430-elf/uleb128_430.d: New test. * testsuite/ld-msp430-elf/uleb128_430x.d: New test.
2020-09-08aarch64: Add -mcpu option for Cortex-R82Alex Coplan1-0/+1
This adds support for the Arm Cortex-R82 CPU in AArch64 GAS. For more information about this processor, see [0]. [0] : https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82 gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82. * doc/c-aarch64.texi: Document -mcpu=cortex-r82.
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-4/+5
This patch adds support for the system registers introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to validation function. (parse_sys_ins_reg): Likewise. (print_operands): Pass CPU features to aarch64_print_operand(). * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output. * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output. * testsuite/gas/aarch64/v8-r-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take system register name in order to simplify validation for v8-R. (aarch64_print_operand): Also take CPU feature set, as disassembly for system registers now depends on arch variant. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (print_operands): Pass CPU features to aarch64_print_operand(). * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine preferred disassembly of system registers. (SR_RNG): Refactor to use new SR_FEAT2 macro. (SR_FEAT2): New. (SR_V8_1_A): New. (SR_V8_4_A): New. (SR_V8_A): New. (SR_V8_R): New. (SR_EXPAND_ELx): New. (SR_EXPAND_EL12): New. (aarch64_sys_regs): Specify which registers are only on A-profile, add R-profile system registers. (ENC_BARLAR): New. (PRBARn_ELx): New. (PRLARn_ELx): New. (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for Armv8-R AArch64.
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+1
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
2020-09-02ubsan: tc-z80.c:3656 shift exponent 32 is too largeAlan Modra1-1/+1
* config/tc-z80.c (is_overflow): Avoid too large shift.
2020-09-02ubsan: tc-sparc.c:1146 left shift cannot be representedAlan Modra1-1/+1
* config/tc-sparc.c (in_signed_range): Use an unsigned type for sign mask.
2020-09-02ubsan: tc-nios2.c:1403 shift exponent 32 is too largeAlan Modra1-1/+1
* config/tc-nios2.c (md_apply_fix): Avoid too large shift.
2020-09-02ubsan: tc-mips.c:9606 shift exponent 32 is too largeAlan Modra1-2/+5
* config/tc-mips.c (load_register): Avoid too large shift.
2020-09-02ubsan: tc-d30v.c left shift cannot be representedAlan Modra1-2/+2
* config/tc-d30v.c (parallel_ok): Use 1UL for left shift expression.
2020-09-02ubsan: rx-parse.y:1743 shift exponent 32 is too largeAlan Modra1-24/+24
* config/rx-parse.y (rx_intop): Avoid too large shifts. (rx_intop, rx_uintop, rx_disp3op, rx_disp5op, displacement), (rtsd_immediate): Use correctly typed unsigned variables.
2020-09-02ubsan: obj-macho.c:503 left shift cannot be representedAlan Modra1-1/+1
* config/obj-macho.c (obj_mach_o_zerofill): Correct type of constant shifted left.
2020-09-02ubsan: bfin-lex.l:503 left shift cannot be representedAlan Modra1-1/+1
* config/bfin-lex.l: Use an unsigned type for "value".
2020-09-0232-bit host pdp11 breakageAlan Modra1-0/+2
If bfd_vma is 32 bits, gcc complains about shift counts exceeding width of the type. * config/tc-pdp11.c (md_number_to_chars): Condition nbytes=8 code on BFD64.
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu1-17/+21
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is enabled by ck803r3, and it's still a part of enhance DSP instruction set. gas/ * config/tc-csky.c (csky_cpus): Add ck803r3. (CSKY_ISA_803R3): Define. (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1. include/ * opcode/csky.h (CSKYV2_ISA_3E3R3): Define. opcodes/ * csky-opc.h (csky_v2_opcodes): Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set.
2020-09-02CSKY: Refine literals pool dump process and float register parser.Cooper Qu1-3/+51
gas/ * config/tc-csky.c (struct literal): New member bignum. (dump_literals): Handle big constant. (enter_literal): Likewise. (parse_type_freg): Handle vector register.
2020-09-01PR26420, PR26421, PR26425, PR26427 UBSAN: tc-arm.c left shiftsAlan Modra1-78/+78
PR 26420 PR 26421 PR 26425 PR 26427 * config/tc-arm.c (struct arm_it): Make size, size_req, cond and uncond_value unsigned. (parse_vfp_reg_list): Make setmask unsigned, vpr_str_len size_t. (parse_big_immediate): Cast generic_bignum elements to unsigned. (encode_thumb32_immediate): Shift left 0xffU. (double_to_single): Make sign unsigned. Tidy. (move_or_literal_pool): Cast LITTLE_NUM elements to uint64_t or valueT. (vfp_or_neon_is_neon): Adjust inst.uncond_value expression. (md_assemble): Likewise. (handle_pred_state): Make cond unsigned. (thumb32_negate_data_op): Make variables unsigned. (md_apply_fix): Make value and newval unsigned, adjust uses.
2020-08-31PR26510 UBSAN: tc-z8k.c left shift of negative valueAlan Modra1-8/+8
This also fixes the packing of the nibble buffer, which contains rubbish in the top 4 bits of each element. PR 26510 * config/tc-z8k.c (buffer): Use unsigned char. (apply_fix): Use unsigned char* pointers. (build_bytes): Likewise and mask nibbles when packing.
2020-08-31PR26503 UBSAN: tc-v850.c:1447 left shift cannot be representedAlan Modra1-1/+1
PR 26503 * config/tc-v850.c (parse_register_list): Shift 1u left.
2020-08-31PR26502 UBSAN: tc-tic6x.c left shift of negative valueAlan Modra1-21/+21
PR 26502 * config/tc-tic6x.c (md_apply_fix): Use unsigned variables.
2020-08-31PR26497 UBSAN: tc-sh.c:2467 left shift cannot be representedAlan Modra1-6/+6
PR 26497 * config/tc-sh.c (assemble_ppi): Use unsigned variables.
2020-08-31PR26495 UBSAN: tc-score.c, tc-score7.c left shift of negative valueAlan Modra2-15/+15
PR 26495 * config/tc-score.c (s3_apply_fix): Use unsigned variables. * config/tc-score7.c (s7_apply_fix): Likewise.
2020-08-31PR26480 UBSAN: tc-nios2.c:1634 left shift cannot be representedAlan Modra1-1/+1
PR 26480 * config/tc-nios2.c (nios2_parse_reglist): Shift 1UL left.
2020-08-31PR26479 UBSAN: tc-nios2.c:244 left shift cannot be representedAlan Modra1-2/+2
PR 26479 * config/tc-nios2.c (md_chars_to_number): Cast buf[i] before shifting.
2020-08-31PR26472, PR26473, PR26474 UBSAN: tc-mips.c shift left UBAlan Modra1-9/+9
PR 26472 PR 26473 PR 26474 * config/tc-mips.c (operand_reg_mask): Shift 1u left. (load_register): Shift 0xffffU left.
2020-08-31PR26471 UBSAN: tc-metag.c:7038 left shift cannot be representedAlan Modra1-1/+1
PR 26471 * config/tc-metag.c (md_chars_to_number): Make retval unsigned.
2020-08-31PR26468 UBSAN: tc-mep.c:1684 left shift of negative valueAlan Modra1-2/+2
PR 26468 * config/tc-mep.c (md_convert_frag): Use uint32_t for addend and other variables.
2020-08-31PR26493 UBSAN: tc-riscv.c left shift negative and not representableAlan Modra1-17/+17
PR 26493 * config/tc-riscv.c (riscv_ip): Cast X_add_number passed to VALID_* macros to unsigned.
2020-08-31crx: ubsan: cannot be representedAlan Modra1-126/+98
* config/tc-crx.c: Formatting. (CRX_PRINT): Wrap params in parentheses. Remove parens from uses throughout file. (reset_vars, get_register, get_copregister, get_optype, get_opbits), (get_opflags, get_number_of_operands, parse_operand, gettrap), (handle_LoadStor, getconstant, check_range, getreg_image), (parse_operands, parse_insn, print_operand, print_constant), (exponent2scale, mask_reg, process_label_constant, set_operand), (assemble_insn, print_insn): Delete unnecessary forward declaration. (print_insn): Make static. (print_constant): Make "constant" unsigned. (assemble_insn): Tidy REVERSE_MATCH index calc. * expr.c (generic_bignum_to_int32): Cast elements to valueT.
2020-08-31PR26509 UBSAN: tc-z80.c:3656 shift exponent is too largeAlan Modra1-1/+1
PR 26509 * config/tc-z80.c (is_overflow): Use 1UL in mask shift expression.
2020-08-31tic4x-coff: ubsan: various shift UBAlan Modra1-10/+6
* config/tc-tic4x.c (tic4x_gen_to_words): Rewrite mantissa overflow test without UB. Avoid other UB shifts by making them unsigned.
2020-08-31CSKY: Refine operand format error reporting.Cooper Qu1-109/+174
Rename SET_ERROR_NUMBER to SET_ERROR_STRING, and add SET_ERROR_INTEGER to report error message which pass an integer argument. gas/ * config/tc-csky.c (csky_error_state): New member 'arg_int'. (SET_ERROR_NUMBER): Rename to SET_ERROR_STRING. (SET_ERROR_INTEGER): New. (err_formats): Add error format for ERROR_FREG_OVER_RANGE and ERROR_VREG_OVER_RANGE. (csky_show_error): Pass an integer argument for some error numbers. (parse_exp): Call SET_ERROR_STRING instead of SET_ERROR_NUMBER. (parse_rt): Likewise. (parse_type_ctrlreg): Likewise. (csky_get_reg_val): Likewise. (is_reglist_legal): Likewise. (is_freglist_legal): Likewise. (is_reglist_dash_comma_legal): Likewise. (is_reg_lshift_illegal): Likewise. (is_psr_bit): Likewise. (parse_type_cpreg): Likewise. (parse_type_cpcreg): Likewise. (parse_type_areg): Likewise. (parse_type_freg): Likewise. (parse_ldst_imm): Likewise and call SET_ERROR_INTEGER. (get_operand_value): Likewise. (parse_operands_op): Likewise and call is_imm_within_range, is_imm_within_range_ext and is_oimm_within_range. (md_assemble): Likewise. (is_imm_within_range): New. (is_imm_within_range_ext): Rename from is_imm_over_range. (is_oimm_within_range): Rename from is_oimm_over_range. (v2_work_add_sub): Call SET_ERROR_INTEGER. (csky_rolc): call is_imm_within_range instead of is_imm_over_range. opcodes/ * csky-dis.c (csky_output_operand): Assign dis_info.value for OPRND_TYPE_VREG.
2020-08-31CSKY: Add warning when -mdsp and -mcpu=ck803ern are both added.Cooper Qu1-3/+16
gas/ * config/tc-csky.c (md_begin): Add warning when -mdsp and -mcpu=ck803ern are both added. (parse_ldst_imm): Fix error message.
2020-08-30PR26437, PR26438 UBSAN: tc-cr16.c left shifts and overflowsAlan Modra1-801/+787
Always use unsigned constants in expressions generating masks. The following trys mightily to avoid UB (but hits it anyway with bits=32 and 0x7fffffff << 1), and worse, for 32-bit int, 64-bit long, bits=32 doesn't generate 0xffffffff. max = ((((1 << (bits - 1)) - 1) << 1) | 1); results in -1, or max = 0xffffffffffffffff. This patch fixes that problem, a possible shift exponent of -1U, removes some dead code, and makes general tidies. PR26437 PR26438 * config/tc-cr16.c: Include limits.h, formatting. (CR16_PRINT): Wrap params in parentheses. Remove parens from uses throughout file. (getconstant): Handle zero nbits. (print_operand): Simplify handling of index regs. (check_range): Use int32_t variables. Correct range checks.
2020-08-29PR26481 UBSAN: tc-pj.c:281 index out of boundsAlan Modra1-2/+2
PR 26481 * config/tc-pj.c (md_assemble): Don't loop past end of opcode->arg array.
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