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2018-09-20S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-11/+13
2018-09-20PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-1/+1
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki1-2/+2
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton2-1626/+2847
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina1-1/+1
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-11/+34
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-17/+14
2018-09-14csky: Support PC relative diff relocationLifang Xia2-0/+9
2018-09-14x86: fold CRC32 templatesJan Beulich1-11/+7
2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu1-3/+4
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-19/+22
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-9/+25
2018-09-13x86: improve operand reversalJan Beulich1-7/+33
2018-09-13x86: add code comment on deprecated status of pseudo-suffixesJan Beulich1-1/+2
2018-09-06PR23570, AVR .noinit section defaults to PROGBITSAlan Modra1-19/+0
2018-09-04gas, sparc: Allow non-fpop2 instructions before floating point branchesDaniel Cederman1-5/+6
2018-09-03Change the .section directive for the AVR assembler so that the .noinit secti...Nick Clifton1-0/+19
2018-08-31PowerPC64 higher REL16 relocationsAlan Modra2-13/+43
2018-08-31x86: Extend assembler to generate GNU property notesH.J. Lu2-12/+296
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-11/+21
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-1/+4
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-1/+4
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-2/+5
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-1/+16
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-2/+16
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-2/+17
2018-08-23RISC-V: Reject empty rouding mode and fence operand.Jim Wilson1-0/+3
2018-08-21Fix handling of undocumented SLL instruction for the Z80 target.Arnold Metselaar1-13/+29
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra1-78/+74
2018-08-18S12Z: Move opcode header to public include directory.John Darrington1-1/+1
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+6
2018-08-10x86: Don't display --32/--64/--x32 without BFD64H.J. Lu1-2/+2
2018-08-09x86: Display default x86-specific options for "as --help"H.J. Lu1-12/+27
2018-08-07Correct the parsing of derferred register addressing in the PDP11 assembler.James Patrick Conlon1-5/+13
2018-08-06[ARC] Check if an input asm file is rf16 compliantclaziss1-0/+25
2018-08-06[ARC] Add Tag_ARC_ATR_version.claziss1-1/+5
2018-08-06[ARC] Update handling AUX-registers.claziss1-1/+9
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich2-28/+16
2018-08-05R_PPC64_REL24_NOTOC supportAlan Modra1-0/+3
2018-08-03Update PRU assembler to corect hardware register numbering for DWARF.Dimitar Dimitrov2-6/+26
2018-08-03x86: drop "mem" operand type attributeJan Beulich2-8/+15
2018-08-01Fix bug in PDP11 assembler when handling a JSr instruction with deferred auto...James Patrick Conlon1-1/+15
2018-08-01Fix compile time warning problem with gcc 8 and the NS32K assembler sources.Nick Clifton1-1/+1
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich1-1/+16
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-6/+32
2018-07-31x86: don't abort() upon DATA16 prefix on (E)VEX encoded insnJan Beulich1-5/+19
2018-07-31x86: drop CpuVREXJan Beulich1-1/+1
2018-07-30x86: don't mistakenly scale non-8-bit displacementsJan Beulich1-1/+2
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner6-0/+7504
2018-07-29Fix unwind offset for start_symbol.John David Anglin1-1/+3
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