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AgeCommit message (Expand)AuthorFilesLines
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-3/+1
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich1-3/+2
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich1-0/+9
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich1-2/+3
2019-12-04x86: consolidate tracking of MMX register useJan Beulich1-9/+3
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich1-8/+14
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich1-1/+3
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess1-0/+6
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess1-0/+4
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess1-7/+1
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski1-3/+6
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-16/+17
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich2-34/+33
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich2-21/+35
2019-11-14x86: make AnySize an insn attributeJan Beulich1-1/+1
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu1-44/+65
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu1-2/+0
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu1-2/+1
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-34/+23
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-48/+2
2019-11-12x86: introduce operand type "instance"Jan Beulich1-29/+44
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-42/+33
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-6/+7
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-43/+45
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-14/+14
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich2-9/+10
2019-11-08x86: introduce operand type "class"Jan Beulich1-41/+59
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-4/+83
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+7
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson1-0/+49
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson1-0/+47
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson1-29/+54
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-24/+217
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+6
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+1
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+4
2019-11-04x86: re-arrange process_operands()Jan Beulich1-57/+49
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu1-0/+31
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-15/+29
2019-10-30x86: drop stray WJan Beulich1-5/+6
2019-10-26Add some missing casts to suppress implicit cast warningsJohn David Anglin1-5/+6
2019-10-16qsort: tc-xtensa.c tidyAlan Modra1-22/+26
2019-10-15remove more xmalloc in bfdAlan Modra1-6/+6
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel1-1/+1
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz1-4/+142
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-2/+2
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina1-7/+16
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni1-5/+5
2019-09-23ecoff bfd.h tidyAlan Modra2-0/+2
2019-09-23arm bfd.h tidyAlan Modra1-0/+1
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