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path: root/gas/config/tc-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-5/+5
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu1-0/+4
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu1-17/+40
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu1-0/+55
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-1/+3
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu1-11/+409
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei1-0/+29
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-87/+23
2021-11-04RISC-V: Clarify the behavior of .option rvc or norvc.Nelson Chu1-21/+18
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-288/+304
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+3
2021-09-17RISC-V: Merged extension string tables and their version tables into one.Nelson Chu1-119/+7
2021-08-31RISC-V: Extend .insn directive to support hardcode encoding.Nelson Chu1-3/+55
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-1/+200
2021-07-21as_bad_subtractAlan Modra1-2/+1
2021-07-06PR 28053: Fix spelling mistakes: usupported -> unsupported and relocatation -...Yuri Chornoivan1-1/+1
2021-06-11RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.Nelson Chu1-10/+8
2021-05-26RISC-V: Allow to link the objects with unknown prefixed extensions.Nelson Chu1-0/+1
2021-05-24RISC-V: PR25212, Report errors for invalid march and mabi combinations.Nelson Chu1-0/+18
2021-04-16RISC-V: PR27436, make operand C> work the same as >.Nelson Chu1-3/+2
2021-03-31Use bool in gasAlan Modra1-114/+114
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen1-0/+13
2021-02-19Fix compile time warnings when building riscv assembler.Nick Clifton1-3/+3
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-89/+92
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-24/+113
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu1-10/+0
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu1-56/+52
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-58/+66
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-161/+130
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich1-0/+2
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf1-1/+13
2021-01-06RISC-V: Implement support for big endian targets.Marcus Comstedt1-7/+25
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra1-2/+2
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+33
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-4/+10
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu1-1/+3
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu1-13/+10
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu1-47/+55
2020-09-24RISC-V: Error for relaxable branch in absolute section.Jim Wilson1-0/+7
2020-09-21PR26569, R_RISCV_RVC_JUMP results in buffer overflowAlan Modra1-3/+7
2020-08-31PR26493 UBSAN: tc-riscv.c left shift negative and not representableAlan Modra1-17/+17
2020-08-23PR26513, 629310abec breaks assembling PowerPC Linux kernelsAlan Modra1-5/+9
2020-08-21Rearrange symbol_create parametersAlan Modra1-2/+2
2020-08-20Port gas/config/* to str_htab.Martin Liska1-66/+27
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton1-1/+1
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-29/+24
2020-06-23RISC-V: Generate ELF priv attributes if priv instruction are explicited used.Nelson Chu1-6/+42
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-27/+9