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path: root/gas/config/tc-i386.c
AgeCommit message (Expand)AuthorFilesLines
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-11/+34
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-17/+14
2018-09-14x86: fold CRC32 templatesJan Beulich1-11/+7
2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu1-3/+4
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-19/+22
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-9/+25
2018-09-13x86: improve operand reversalJan Beulich1-7/+33
2018-09-13x86: add code comment on deprecated status of pseudo-suffixesJan Beulich1-1/+2
2018-08-31x86: Extend assembler to generate GNU property notesH.J. Lu1-12/+291
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+6
2018-08-10x86: Don't display --32/--64/--x32 without BFD64H.J. Lu1-2/+2
2018-08-09x86: Display default x86-specific options for "as --help"H.J. Lu1-12/+27
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-26/+15
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-6/+13
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich1-1/+16
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-6/+32
2018-07-31x86: don't abort() upon DATA16 prefix on (E)VEX encoded insnJan Beulich1-5/+19
2018-07-31x86: drop CpuVREXJan Beulich1-1/+1
2018-07-30x86: don't mistakenly scale non-8-bit displacementsJan Beulich1-1/+2
2018-07-27x86: Check for more than 2 memory referencesH.J. Lu1-0/+7
2018-07-26x86: Initialize broadcast_op.bytes to 0H.J. Lu1-0/+1
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu1-11/+33
2018-07-24x86: Use unsigned int to iterate through vector operandsH.J. Lu1-5/+5
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich1-4/+7
2018-07-23x86: Remove broadcast_not_on_src_operandH.J. Lu1-4/+0
2018-07-22x86: Determine vector length from the last vector operandH.J. Lu1-10/+25
2018-07-21gas/config/tc-i386.c: Break long lineH.J. Lu1-4/+6
2018-07-20x86: Rename match_reg_size to match_operand_sizeH.J. Lu1-11/+12
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-1/+19
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-2/+43
2018-07-16x86: fix operand size checkingJan Beulich1-54/+61
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich1-7/+2
2018-07-11x86: simplify legacy prefix emissionJan Beulich1-10/+4
2018-07-11x86: fix "REP RET" with -madd-bnd-prefixJan Beulich1-4/+10
2018-06-01x86: relax redundant REX prefix checkJan Beulich1-2/+3
2018-06-01x86: simplify control register checkJan Beulich1-5/+2
2018-06-01x86: tighten condition for emitting LOCK on control register accessesJan Beulich1-4/+3
2018-05-30Add znver2 support.Amit Pawar1-0/+2
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+41
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-3/+7
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-40/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+40
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-17/+54
2018-04-26x86: also optimize zeroing-masking variants of insnsJan Beulich1-1/+1
2018-04-26x86: properly force / avoid forcing EVEX encodingJan Beulich1-7/+5
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-11/+13
2018-04-26x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich1-0/+3
2018-04-26x86: x87-related adjustmentsJan Beulich1-6/+5
2018-04-26x86: fix indentation in build_modrm_byte()Jan Beulich1-39/+39
2018-04-26x86: move and fold common code in build_modrm_byte()Jan Beulich1-29/+13
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