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2022-07-04x86: fold Disp32S and Disp32Jan Beulich1-7/+2
The only case where 64-bit code uses non-sign-extended (can also be considered zero-extended) displacements is when an address size override is in place for a memory operand (i.e. particularly excluding displacements of direct branches, which - if at all - are controlled by operand size, and then are still sign-extended, just from 16 bits). Hence the distinction in templates is unnecessary, allowing code to be simplified in a number of places. The only place where logic becomes more complicated is when signed-ness of relocations is determined in output_disp(). The other caveat is that Disp64 cannot be specified anymore in an insn template at the same time as Disp32. Unlike for non-64-bit mode, templates don't specify displacements for both possible addressing modes; the necessary adjustment to the expected ones has already been done in match_template() anyway (but of course the logic there needs tweaking now). Hence the single template so far doing so is split.
2022-05-27x86/Intel: allow MASM representation of embedded rounding / SAEJan Beulich1-1/+4
MASM doesn't support the separate operand form; the modifier belongs after the instruction instead. Accept this form alongside the original (now legacy) one. Short of having access to a MASM version to actually check in how far "after the instruction" is a precise statement in their documentation, allow both that and the SDM mandated form where the modifier is on the last register operand (with a possible immediate operand following). Sadly the split out function, at least for the time being, needs to cast away constness at some point, as the two callers disagree in this regard. Adjust some, but not all of the testcases.
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich1-1/+22
As a preparatory step to allowing proper non-operand forms of specifying embedded rounding / SAE, convert the internal representation to non- operand form. While retaining properties (and in a few cases perhaps providing more meaningful diagnostics), this means doing away with a few hundred standalone templates, thus - as a nice side effect - reducing memory consumption / cache occupancy.
2022-05-27x86/Intel: allow MASM representation of embedded broadcastJan Beulich1-0/+17
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Accept these forms alongside the original (now legacy) ones. Acceptance of the original {1to<n>} operand suffix is retained both for backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes. I have no insight (yet) into how MASM expects those to be disambiguated. Adjust some, but not all of the testcases.
2022-03-23x86: improve resolution of register equatesJan Beulich1-0/+3
Allow transitive (or recursive) equates to work in addition to direct ones. The only requirements are that - the equate being straight of a register, i.e. no expressions involved (albeit I'm afraid something like "%eax + 0" will be viewed as %eax), - at the point of use there's no forward ref left which cannot be resolved, yet.
2022-03-23x86: don't attempt to resolve equates and alike from i386_parse_name()Jan Beulich1-0/+7
PR gas/28977 Perhaps right from its introduction in 4d1bb7955a8b it was wrong for i386_parse_name() to call parse_register(). This being a hook from the expression parser, it shouldn't be resolving e.g. equated symbols. That's relevant only for all other callers of parse_register(). To compensate, in Intel syntax mode check_register() needs calling; perhaps not doing so was an oversight right when the function was introduced. This is necessary in particular to force EVEX encoding when VRex registers are used (but of course also to reject bad uses of registers, i.e. fully matching what parse_register() needs it for).
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich1-1/+1
In the one case where non-NULL gets passed, passing NULL has the same effect. Hence the parameter is not needed at all.
2021-03-31Use bool in gasAlan Modra1-7/+7
* as.h (POISON_BFD_BOOLEAN): Define. * as.c, * as.h, * atof-generic.c, * config/atof-ieee.c, * config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h, * config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c, * config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c, * config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c, * config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h, * config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c, * config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h, * config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c, * config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h, * config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c, * config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c, * config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h, * config/tc-metag.c, * config/tc-metag.h, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c, * config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h, * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c, * config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h, * config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h, * config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c, * config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c, * config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h, * config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c, * config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xstormy16.h, * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c, * config/tc-z8k.c, * config/xtensa-istack.h, * config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c, * dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c, * frags.h, * listing.c, * macro.c, * output-file.c, * read.c, * read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true.
2021-03-30x86: drop seg_entryJan Beulich1-10/+4
Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich1-2/+2
The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-2/+4
Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-3/+6
Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-23x86: unbreak certain MPX insn operand formsJan Beulich1-2/+6
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") dropped the mandatory prefix bytes from legacy encoded insn templates, but failed to also adjust affected MPX-specific checks in two places. For the expressions to remain halfway readable, introduce local variables to hold current_templates->start.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-07-20x86: handle SVR4 escaped binary operatorsJan Beulich1-0/+10
PR gas/4572 When / is a comment character, its use as binary "divide" operator needs escaping by a backslash. Besides the scrubber needing to support this (addressed in an earlier change), there are also a few provisions needed in target specific operator handling. As the spec calls for % and * to also be escaped because of being "overloaded", also recognize these, despite the overloading there not really preventing their use as operators in most (%) or all (*) cases, given the way how the rest of the assembler works. To bring source and testsuite in line, also drop the TE_I386AIX part of the respective conditional, as i?86-*-aix* support had been removed a while ago.
2020-02-26Indent labelsAlan Modra1-1/+1
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-2/+4
AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich1-1/+2
In memory operand addressing, which forms of displacement are permitted besides Disp8 is pretty clearly limited - outside of 64-bit mode, Disp16 or Disp32 only, depending on address size (MPX being special in not allowing Disp16), - in 64-bit mode, Disp32s or Disp64 without address size override, and solely Disp32 with one. Adjust assembler and i386-gen to match this, observing that templates already get adjusted before trying to match them against input depending on the presence of an address size prefix. This adjustment logic gets extended to all cases, as certain DispNN values should also be dropped when there's no such prefix. In fact behavior of the assembler, perhaps besides the exact diagnostics wording, should not differ between there being templates applicable to 64-bit and non-64-bit at the same time, or there being fully separate sets of templates, with their DispNN settings already reduced accordingly. This adjustment logic further gets guarded such that there wouldn't be and Disp<N> conversion based on address size prefix when this prefix doesn't control the width of the displacement (on branches other than absolute ones). These adjustments then also allow folding two MOV templates, which had been split between 64-bit and non-64-bits variants so far. Once in this area also - drop the bogus DispNN from JumpByte templates, leaving just the correct Disp8 there (compensated by i386_finalize_displacement() now setting Disp8 on their operands), - add the missing Disp32S to XBEGIN. Note that the changes make it necessary to temporarily mark a test as XFAIL; this will get taken care of by a subsequent patch. The failing parts are entirely bogus and will get replaced.
2019-12-09x86/Intel: fold "xmmword" with "oword"Jan Beulich1-11/+9
These are full aliases of one another, so there's no real need to use distinct O_md* values for them.
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich1-2/+5
This is an alias of "qword ptr", commonly used with MMX insns. At this occasion also test (alongside the newly supported "mmword") - "zmmword" used as expression, - PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich1-3/+6
Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") broke rejecting of these for floating point insns. Fix this by setting the "byte" operand attribute, which will now (again) cause an error. Furthermore the diagnostic for the "far ptr" case in general and for the "near ptr" case in the non-float cases became "invalid instruction suffix" instead of the intended "operand size mismatch". Fix this by also setting the "tbyte" operand attribute (no insn template accepts both byte and tbyte operands).
2019-12-09x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich1-10/+5
There are extremely few insns accepting "tbyte ptr" operand, so the "tbyte" operand flag checking done by match_operand_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Fold the code with that setting the "byte" operand flag to force an error (no insn at all accepts both "byte ptr" and tbyte ptr" operands, except for AnySize ones where the two (conflicting) recorded types don't matter (operand_size_match() doesn't call match_operand_size() in this case).
2019-12-09x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich1-2/+0
No floating point insn accepts an "fword ptr" operand, so the "fword" operand flag checking done by match_mem_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09x86/Intel: drop pointless special casing of LxSJan Beulich1-6/+1
LDS et al don't accept "word ptr" operands anyway, as per their insn templates. Hence there's no need to special case this here; the check has become dysfunctional anyway by dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich1-0/+9
Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich1-2/+3
While dc2be329b950 ("i386: Only check suffix in instruction mnemonic") has made the assembler accept these in the first place (they were wrongly rejected before), the generated code was still wrong in that it lacked an operand size override. (In 64-bit code, other than in 16- and 32-bit ones, CALL and JMP with memory operands are all entirely unambiguous: No operand size can have two meanings.)
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-10/+11
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-7/+12
... instead of an operand one: There's only ever one operand here anyway.
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-2/+2
This is to further shrink the operand type representation.
2019-07-16x86: fold SReg{2,3}Jan Beulich1-3/+2
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-05-14Fix illegal memory access triggered when attempting to assemble a bogus i386 ↵Nick Clifton1-0/+6
source file. PR 24538 * config/tc-i386-intel.c (i386_intel_simplify_register): Reject illegal register numbers.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-2/+1
This allows to simplify the code in a number of places.
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-2/+2
No template specifies this bit, so there's no point recording it in the templates. Use a flags[] bit instead.
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-3/+0
They aren't really useful (anymore?): The conflicting operand size check isn't applicable to any insn validly using respective memory operand sizes (and if they're used wrongly, another error would result), and the logic in process_suffix() can be easily changed to work without them. While re-structuring conditionals in process_suffix() also drop the CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode table.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-3/+3
... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time.
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-3/+3
Use a combination of a single new Reg bit and Byte, Word, Dword, or Qword instead. Besides shrinking the number of operand type bits this has the benefit of making register handling more similar to accumulator handling (a generic flag is being accompanied by a "size qualifier"). It requires, however, to split a few insn templates, as it is no longer correct to have combinations like Reg32|Reg64|Byte. This slight growth in size will hopefully be outweighed by this change paving the road for folding a presumably much larger number of templates later on.
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich1-3/+26
While we shouldn't outright reject such (as was wrongly done by commit 4d36230d59 ("x86: Update segment register check in Intel syntax"), as MASM accepts them even silently, issue (by default) a warning for such questionable constructs.
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich1-1/+7
This reverts commit 4d36230d59903b92fbe2b53b31ed64a884860f0e. I was committed without maintainer ack and regresses intended functionality. A replacement will be committed shortly.
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich1-2/+4
Multiple errors are more confusing than helpful, as the more generic one often implies a sufficiently different adjustment than would actually be needed to fix the code. Additionally it makes it more cumbersome to add missing error checks, as the testsuite then needs extra updating.
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich1-1/+3
Just like we make rsp/esp a base register even if it comes second, make riz/eiz an index register even if it comes first.
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich1-24/+25
... rather than silently dropping it altogether. i386_finalize_displacement() expects baseindex to already be set, so the respective statement needs to be moved up. This then also allows a subsequent conditional to be simplified. For this to not regress on 32-bit addressing, break out address size guessing from i386_index_check(), invoking the new function earlier so that i386_finalize_displacement() has i.prefix[ADDR_PREFIX] available. i386_addressing_mode () in turn needs i.base_reg / i.index_reg set earlier.
2017-08-01x86: Update segment register check in Intel syntaxH.J. Lu1-7/+1
https://sourceware.org/ml/binutils/2009-04/msg00223.html introduced a new Intel syntax parser which accepts mov eax, fs:gs:[eax] It ignores anything between ':'s after fs and treats mov eax, DWORD PTR fs:foobar:16 mov eax, DWORD PTR fs:foobar:barfoo:16 mov eax, DWORD PTR fs:ds:16 mov eax, DWORD PTR fs:ds:cs:16 as mov eax, DWORD PTR fs:16 This patch updates segment register check and only allows a single ':'. PR gas/21874 * config/tc-i386-intel.c (i386_intel_operand): Update segment register check. * testsuite/gas/i386/intelok.s: Replace "fs:gs:[eax]" with "fs:[eax]". * testsuite/gas/i386/inval-seg.s: Add tests for invalid segment register. * testsuite/gas/i386/x86-64-inval-seg.s: Likewise. * testsuite/gas/i386/inval-seg.l: Updated. * testsuite/gas/i386/x86-64-inval-seg.l: Likewise.
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-1/+1
PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-0/+4
The dual purpose mnemonic (string move vs scalar double move) breaks the assumption that the isstring flag would be set on both the first and last entry in the current set of templates, which results in bogus or missing diagnostics for the string move variant of the mnemonic. Short of mostly rewriting i386_index_check() and its interaction with the rest of the code, simply shrink the template set to just string instructions when encountering the second memory operand, and run i386_index_check() a second time for the first memory operand after that reduction.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
generated by cgit v1.1 at 2025-02-27 12:51:13 +0000