Age | Commit message (Collapse) | Author | Files | Lines |
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* atof-generic.c: Replace "if (x) free (x)" with "free (x)"
throughout.
* config/obj-elf.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-tic30.c: Likewise.
* ecoff.c: Likewise.
* read.c: Likewise.
* stabs.c: Likewise.
* symbols.c: Likewise.
* testsuite/gas/all/test-gen.c: Likewise.
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PR 25992
gas * config/tc-arm.c : Add arm_ext_v8r feature.
(it_fsm_post_encode): Check arm_ext_v8r feature.
(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.
include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
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This fixes PR 25863 by fixing the condition in the parsing of vmul in
do_mve_vmull. It also simplifies the code in there fixing latent issues that
would lead to NEON code being accepted when it shouldn't.
gas/ChangeLog:
2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25863
* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
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As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl. This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub. I had forgotten to do this and this patch remedies that oversight.
gas/ChangeLog:
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
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instruction is detected in a section with insufficient alignment.
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
detected in a section which does not have at least 4 byte
alignment.
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
* testsuite/gas/arm/ldr-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
disassembly, ignoring any NOPs that may have been inserted because
of section alignment.
* testsuite/gas/arm/ldr-t.d: Likewise.
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The implementation of the Arm CDE CX*A instructions doesn't allow a
condition code on the instructions but does allow the instruction in an
ITBlock.
The specification has been recently updated, though this is yet to be
published.
The instructions now should allow a suffix, and should behave in the
standard way around ITBlocks.
This patch removes the custom pred_instruction_type and handling for
these instructions, and uses the standard INSIDE_IT_INSN predication
type to describe the new instructions.
gas/ChangeLog:
2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (enum pred_instruction_type): Remove
NEUTRAL_IT_NO_VPT_INSN predication type.
(cxn_handle_predication): Modify to require condition suffixes.
(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
* testsuite/gas/arm/cde-scalar.s: Update test.
* testsuite/gas/arm/cde-warnings.l: Update test.
* testsuite/gas/arm/cde-warnings.s: Update test.
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gettext("") returns the header entry with meta information, not the
empty string.
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
N_() on empty string.
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Labels don't go in the first column according to standard emacs C
indent rules, and I got annoyed enough at seeing diff -p show a label
rather than the function name to fix this.
bfd/
* aoutx.h: Indent labels correctly. Format error strings.
* archive.c: Likewise.
* archive64.c: Likewise.
* coff-arm.c: Likewise.
* coff-rs6000.c: Likewise.
* coff-stgo32.c: Likewise.
* cpu-arm.c: Likewise.
* dwarf2.c: Likewise.
* elf-ifunc.c: Likewise.
* elf-properties.c: Likewise.
* elf-s390-common.c: Likewise.
* elf-strtab.c: Likewise.
* elf.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-cr16.c: Likewise.
* elf32-csky.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-m68k.c: Likewise.
* elf32-msp430.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-nios2.c: Likewise.
* elf32-pru.c: Likewise.
* elf32-xtensa.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-x86-64.c: Likewise.
* elfcode.h: Likewise.
* elfcore.h: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfnn-riscv.c: Likewise.
* elfxx-mips.c: Likewise.
* elfxx-sparc.c: Likewise.
* elfxx-x86.c: Likewise.
* i386lynx.c: Likewise.
* merge.c: Likewise.
* pdp11.c: Likewise.
* plugin.c: Likewise.
* reloc.c: Likewise.
binutils/
* elfedit.c: Indent labels correctly.
* readelf.c: Likewise.
* resres.c: Likewise.
gas/
* config/obj-elf.c: Indent labels correctly.
* config/obj-macho.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-riscv.c: Likewise.
* config/tc-s12z.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* read.c: Likewise.
* symbols.c: Likewise.
* write.c: Likewise.
ld/
* emultempl/cskyelf.em: Indent labels correctly.
* ldfile.c: Likewise.
* ldlang.c: Likewise.
* plugin.c: Likewise.
opcodes/
* aarch64-asm.c: Indent labels correctly.
* aarch64-dis.c: Likewise.
* aarch64-gen.c: Likewise.
* aarch64-opc.c: Likewise.
* alpha-dis.c: Likewise.
* i386-dis.c: Likewise.
* nds32-asm.c: Likewise.
* nfp-dis.c: Likewise.
* visium-dis.c: Likewise.
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My previous patch introduced the use of a C99 feature. C99 standard is
not required for gas, so this feature should be removed.
Committed as obvious.
gas/ChangeLog:
2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (vcx_handle_register_arguments): Remove `for`
loop initial declaration.
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Here we implement the custom datapath extensions for MVE.
This required the following changes:
- Adding a new register argument type (that takes either an MVE vector or
a Neon S or D register).
- Adding two new immediate operands types (0-127 and 0-4095).
- Using the Neon type machinery to distinguish between instruction
types. This required the introduction of new neon shapes to account
for the coprocessor operands to these instructions.
- Adding a new disassembly character to `print_insn_cde` to handle the
new register types.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
instructions that can have 5 arguments.
(enum operand_parse_code): Add new operands.
(parse_operands): Account for new operands.
(S5): New macro.
(enum neon_shape_el): Introduce P suffixes for coprocessor.
(neon_select_shape): Account for P suffix.
(LOW1): Move macro to global position.
(HI4): Move macro to global position.
(vcx_assign_vec_d): New.
(vcx_assign_vec_m): New.
(vcx_assign_vec_n): New.
(enum vcx_reg_type): New.
(vcx_get_reg_type): New.
(vcx_size_pos): New.
(vcx_vec_pos): New.
(vcx_handle_shape): New.
(vcx_ensure_register_in_range): New.
(vcx_handle_register_arguments): New.
(vcx_handle_insn_block): New.
(vcx_handle_common_checks): New.
(do_vcx1): New.
(do_vcx2): New.
(do_vcx3): New.
* testsuite/gas/arm/cde-missing-fp.d: New test.
* testsuite/gas/arm/cde-missing-fp.l: New test.
* testsuite/gas/arm/cde-missing-mve.d: New test.
* testsuite/gas/arm/cde-missing-mve.l: New test.
* testsuite/gas/arm/cde-mve-or-neon.d: New test.
* testsuite/gas/arm/cde-mve-or-neon.s: New test.
* testsuite/gas/arm/cde-mve.s: New test.
* testsuite/gas/arm/cde-warnings.l:
* testsuite/gas/arm/cde-warnings.s:
* testsuite/gas/arm/cde.d:
* testsuite/gas/arm/cde.s:
opcodes/ChangeLog:
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (print_insn_cde): Define 'V' parse character.
(cde_opcodes): Add VCX* instructions.
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This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
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Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
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We noticed +mve was not enabling DSP instructions as it should, reported in PR
25472.
The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions.
This patch reflects that in the '+mve' command line option.
gas/ChangeLog:
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25472
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
+mve.
* testsuite/gas/arm/mve_dsp.d: New test.
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This patch adds support for assembly instructions vldmia, vldmdb, vstmia
and vstmdb in MVE. This instructions are already supported for Armv8-M
Floating-point Extension.
gas/ChangeLog:
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
to support VLDMIA instruction for MVE.
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
instruction for MVE.
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
instruction for MVE.
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
instruction for MVE.
* testsuite/gas/arm/mve-ldst.d: New test.
* testsuite/gas/arm/mve-ldst.s: Likewise.
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This patch moves MVE feature bits into the CORE_HIGH section. This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.
This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16 #does not disable mve.
vadd.i32 q0, q1, q2
This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.
gas/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
include/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
(ARM_ANY): Redefine to not include any MVE bits.
(ARM_FEATURE_ALL): Removed.
opcodes/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
any architecture.
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Fixes
../../gas/config/tc-arm.c: In function 'parse_reg_list':
../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion]
1946 | reg = arm_reg_parse (&str, REGLIST_RN);
| ^~~~~~~~~~
gas/ChangeLog:
* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
REGLIST_RN.
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Add a -m{no-}warn-restrict-it option to control IT related warnings in
ARMv8-A and ARMv8-R. This is disabled by default.
Committed on behalf of Wilco Dijkstra.
gas/ChangeLog:
2019-12-11 Wilco Dijkstra <wdijkstr@arm.com>
* config/tc-arm.c (warn_on_restrict_it): Add new variable.
(it_fsm_post_encode): Check warn_on_restrict_it.
(arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.
* testsuite/gas/arm/armv8-a-bad.d: Likewise.
* testsuite/gas/arm/armv8-a-it-bad.d: Likewise.
* testsuite/gas/arm/armv8-r-bad.d: Likewise.
* testsuite/gas/arm/armv8-r-it-bad.d: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.
* testsuite/gas/arm/udf.d: Likewise.
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This patch fixes .arch_extension behaviour.
Currently, context table for '.arch_extension' is only set while
"-march" processing, but it is not set while .arch processing,
so following code is rejected
.syntax unified
.thumb
.arch armv8.1-m.main
.arch_extension mve.fp
unless -march=armv8.1-m.main is given.
Committing on behalf of Vladimir Murzin
gas/ChangeLog:
2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
* testsuite/gas/arm/mve-arch-ext.s: New.
* testsuite/gas/arm/mve-arch-ext.d: New.
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This patch changes the CRC extension to use the core feature bits instead
of the coproc/fpu feature bits.
CRC is not an fpu feature and it causes issues with the new fpu reset
patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using
the '.arch_extension' directive, which sets bits in the coproc bitfield. When
a '.fpu' directive is encountered, the CRC feature bit gets removed and
there is no way to set it back using '.fpu'.
With this patch, CRC will be marked in the feature core bits, which prevents
it from getting removed when setting/changing the fpu options.
gas/ChangeLog:
* config/tc-arm.c (arm_ext_crc): New.
(crc_ext_armv8): Remove.
(insns): Rename crc_ext_armv8 to arm_ext_crc.
(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
(armv8a_ext_table, armv8r_ext_table,
arm_option_extension_value_table): Redefine the crc
extension in terms of ARM_EXT2_CRC.
* gas/testsuite/gas/arm/crc-ext.s: New.
* gas/testsuite/gas/arm/crc-ext.d: New.
include/ChangeLog:
* opcode/arm.h (ARM_EXT2_CRC): New extension feature
to replace CRC_EXT_ARMV8.
(CRC_EXT_ARMV8): Remove and mark bit as unused.
(ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A,
ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A,
ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of
CRC_EXT_ARMV8.
opcodes/ChangeLog:
* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
Change the coproc CRC conditions to use the extension
feature set, second word, base on ARM_EXT2_CRC.
|
|
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM,
VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M
Floating-point Extension is enabled. According to the ARMv8.1-M ARM,
section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point
Extension and/or Armv8.1-M MVE".
[1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for
both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm
instruction for mve_ext.
(do_vfp_nsyn_pop): Move in order to enable it for both
fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm
instruction for mve_ext.
(do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks.
(insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop,
vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead
of fpu_vfp_ext_v1xd.
* testsuite/gas/arm/v8_1m-mve.s: New.
* testsuite/gas/arm/v8_1m-mve.d: New.
|
|
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode.
Previously VMOV and VMVN with cmode 1101 were not allowed.
The cmode changes also required updating of the MVE conflict checking.
Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV
and VMVN, respectively.
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
cmode 1101.
(is_mve_encoding_conflict): Update cmode conflict checks for
MVE_VMVN_IMM.
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
|
|
This patch is fixes the '.fpu' behaviour.
Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them),
but does not reset previous FPU options selected by other means (ie. when using
'.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset).
Example:
.arch armv8-a @ SET BASE
.arch_extension fp @ ADD FP-ARMV8
.fpu vfpv2 @ ADD (already existing bits, does not reset)
vfms.f32 s0, s1, s2 @ OK
.arch armv8-a @ RESET
.fpu fp-armv8 @ ADD FP-ARMV8
vfms.f32 s0, s1, s2 @ OK
.fpu vfpv2 @ RESET to VFPV2
vfms.f32 s0, s1, s2 @ ERROR
After the patch this becomes:
.arch armv8-a @ SET BASE
.arch_extension fp @ ADD FP-ARMV8
.fpu vfpv2 @ RESET TO VFPV2
vfms.f32 s0, s1, s2 @ ERROR
.arch armv8-a @ RESET
.fpu fp-armv8 @ ADD FP-ARMV8
vfms.f32 s0, s1, s2 @ OK
.fpu vfpv2 @ RESET to VFPV2
vfms.f32 s0, s1, s2 @ ERROR
gas/ChangeLog:
2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits.
(fpu_any): Remove OBJ_ELF guards.
* gas/testsuite/gas/arm/fpu-rst.s: New.
* gas/testsuite/gas/arm/fpu-rst.d: New.
* gas/testsuite/gas/arm/fpu-rst.l: New.
|
|
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the arm backend.
The following Matrix Multiply instructions are added: vummla, vsmmla,
vusmmla, vusdot, vsudot[1].
[1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (arm_ext_i8mm): New feature set.
(do_vusdot): New.
(do_vsudot): New.
(do_vsmmla): New.
(do_vummla): New.
(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
(armv86a_ext_table): Add i8mm extension.
(arm_extensions): Move bf16 extension to context sensitive table.
(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
Move bf16 extension to context sensitive table.
(armv86a_ext_table): Add i8mm extension.
* doc/c-arm.texi: Document i8mm extension.
* testsuite/gas/arm/i8mm.s: New test.
* testsuite/gas/arm/i8mm.d: New test.
* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/arm.h (ARM_EXT2_I8MM): New feature macro.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
Regression tested on arm-none-eabi.
Is this ok for trunk?
Regards,
Mihail
|
|
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch implements the '.bfloat16' directive for the Arm backend.
The syntax for the directive is:
.bfloat16 <0-n numbers>
e.g.
.bfloat16 12.0
.bfloat16 0.123, 1.0, NaN, 5
This is implemented by utilizing the ieee_atof_detail function (included
in the previous patch) in order to encode the slightly different
bfloat16 format.
Added testcases to verify the correct encoding for various bfloat16
values (NaN, Infinity (+ & -), normals, subnormals etc...).
Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf
with no issues.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com>
2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (md_atof): Add encoding for bfloat16
* testsuite/gas/arm/bfloat16-directive-le.d: New test.
* testsuite/gas/arm/bfloat16-directive-be.d: New test.
* testsuite/gas/arm/bfloat16-directive.s: New test.
Is it ok for trunk?
Regards,
Mihail
|
|
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces BFloat16 instructions to the arm backend.
The following BFloat16 instructions are added: vdot, vfma{l/t},
vmmla, vfmal{t/b}, vcvt, vcvt{t/b}.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_archs): Add armv8.6-a option.
(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
* doc/c-arm.texi (-march): New armv8.6-a arch.
* config/tc-arm.c (arm_ext_bf16): New feature set.
(enum neon_el_type): Add NT_bfloat value.
(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
helpers.
(BAD_BF16): New message.
(parse_neon_type): Add bf16 type specifier.
(enum neon_type_mask): Add N_BF16 type.
(type_chk_of_el_type): Account for NT_bfloat.
(el_type_of_type_chk): Account for N_BF16.
(neon_three_args): Split out from neon_three_same.
(neon_three_same): Part split out into neon_three_args.
(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
(do_neon_cvt_1): Account for vcvt.bf16.f32.
(do_bfloat_vmla): New.
(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
vfmat and the MVE vfma in a VPT block with a 't'rue condition.
(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
(do_vdot): New
(do_vmmla): New
(insns): Add vdot and vmmla mnemonics.
(arm_extensions): Add "bf16" extension.
* doc/c-arm.texi: Document "bf16" extension.
* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
* testsuite/gas/arm/bfloat16-bad.d: New test.
* testsuite/gas/arm/bfloat16-bad.l: New test.
* testsuite/gas/arm/bfloat16-bad.s: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
* testsuite/gas/arm/bfloat16-neon.s: New test.
* testsuite/gas/arm/bfloat16-non-neon.s: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
* testsuite/gas/arm/bfloat16-thumb.d: New test.
* testsuite/gas/arm/bfloat16-vfp.d: New test.
* testsuite/gas/arm/bfloat16.d: New test.
* testsuite/gas/arm/bfloat16.s: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A,
ARM_ARCH_V8_6A): New.
* opcode/arm.h (ARM_EXT2_BF16): New feature macro.
(ARM_AEXT2_V8_6A): Include above macro in definition.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
Armv8.6-A.
(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
(neon_opcodes): Add bfloat SIMD instructions.
(print_insn_coprocessor): Add new control character %b to print
condition code without checking cp_num.
(print_insn_neon): Account for BFloat16 instructions that have no
special top-byte handling.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
|
|
If the extension is not found in the context sensitive table, the legacy
tables are still checked as a fallback. This is particularly useful for
Armv8.1-M as it enables the use of '.arch_extension' with the 'mve' and
'mve.fp' extensions which are not part of the legacy table.
* config/tc-arm.c (selected_ctx_ext_table) New static variable.
(arm_parse_arch): Set context sensitive extension table based on the
chosen base architecture.
(s_arm_arch_extension): Change to lookup extensions in the new context
sensitive tables.
* gas/testsuite/gas/arm/mve-ext.s: New.
* gas/testsuite/gas/arm/mve-ext.d: New.
* gas/testsuite/gas/arm/mvefp-ext.s: New.
* gas/testsuite/gas/arm/mvefp-ext.d: New.
|
|
The fix for PR12848 introduced an off by one error in the mask, this corrected
the negative overflows but not the positive overflows. As a result the
conditional branch instructions accepted a too wide positive immediate which
resulted in it corrupting the instruction during encoding.
The relocation I believe has been incorrectly named, to be consistent with the
other relocations it should have been named BRANCH21 which is why the masks for
it are confusing.
I've replaced the masks with a function out_of_range_p which should make it
harder to make such mistakes.
The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits
and so the mask should be checking for 24-bits for positive overflow.
gas/ChangeLog:
PR gas/24991
* config/tc-arm.c (out_of_range_p): New.
(md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20,
BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25
* testsuite/gas/arm/pr24991.d: New test.
* testsuite/gas/arm/pr24991.l: New test.
* testsuite/gas/arm/pr24991.s: New test.
|
|
instruction VLDR.
This patch modifies assembler to accept the equivalent sized floating
and signless datatypes for VLDR instruction but as alias for the unsigned version.
gas/ChangeLog:
2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float
* and signless datatypes for few cases of VLDR instruction.
* testsuite/gas/arm/mve-vldr-bad-3.l: Modify.
* testsuite/gas/arm/mve-vldr-bad-3.s: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.d: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
|
|
bfd/
* bfd-in.h: Move arm declaraions..
* cpu-arm.h: ..to here, new file..
* coff-arm.h: ..and here, new file..
* elf32-arm.h: ..and here, new file.
* cpu-arm.c: Include cpu-arm.h.
* coff-arm.c: Include cpu-arm.h and coff-arm.h.
* elf32-arm.c: Include cpu-arm.h and elf32-arm.h.
* pe-arm.c: Move function rename defines later.
* pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early.
* bfd-in2.h: Regenerate.
gas/
* config/tc-arm.c: Include cpu-arm.h.
ld/
* emultempl/armelf.em: Include elf32-arm.h.
* emultempl/pe.em: Move func defines later and include coff-arm.h.
|
|
This large patch removes the unnecessary bfd parameter from various
bfd section macros and functions. The bfd is hardly ever used and if
needed for the bfd_set_section_* or bfd_rename_section functions can
be found via section->owner except for the com, und, abs, and ind
std_section special sections. Those sections shouldn't be modified
anyway.
The patch also removes various bfd_get_section_<field> macros,
replacing their use with bfd_section_<field>, and adds
bfd_set_section_lma. I've also fixed a minor bug in gas where
compressed section renaming was done directly rather than calling
bfd_rename_section. This would have broken bfd_get_section_by_name
and similar functions, but that hardly mattered at such a late stage
in gas processing.
bfd/
* bfd-in.h (bfd_get_section_name, bfd_get_section_vma),
(bfd_get_section_lma, bfd_get_section_alignment),
(bfd_get_section_size, bfd_get_section_flags),
(bfd_get_section_userdata): Delete.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment): Lose bfd parameter.
(bfd_section_flags, bfd_section_userdata): New.
(bfd_is_com_section): Rename parameter.
* section.c (bfd_set_section_userdata, bfd_set_section_vma),
(bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section),
(bfd_set_section_size): Delete bfd parameter, rename section parameter.
(bfd_set_section_lma): New.
* bfd-in2.h: Regenerate.
* mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param,
update callers.
* aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c,
* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
* compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c,
* elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c,
* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
* elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c,
* elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c,
* elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c,
* elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c,
* elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c,
* elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c,
* elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
* elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c,
* elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c,
* mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c,
* peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c,
* xcofflink.c: Update throughout for bfd section macro and function
changes.
binutils/
* addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c,
* objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c,
* od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c,
* resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update
throughout for bfd section macro and function changes.
gas/
* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,
* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,
* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,
* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,
* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,
* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,
* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,
* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,
* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,
* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,
* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,
* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,
* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,
* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,
* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,
* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,
* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,
* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for
bfd section macro and function changes.
* write.c (compress_debug): Use bfd_rename_section.
gdb/
* aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c,
* coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c,
* dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c,
* exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h,
* hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c,
* i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c,
* maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c,
* mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c,
* objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c,
* ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c,
* rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c,
* s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c,
* solib-spu.c, * solib-svr4.c, * solib-target.c,
* spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c,
* symmisc.c, * symtab.c, * target.c, * windows-nat.c,
* xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c,
* mi/mi-interp.c: Update throughout for bfd section macro and
function changes.
* gcore (gcore_create_callback): Use bfd_set_section_lma.
* spu-tdep.c (spu_overlay_new_objfile): Likewise.
gprof/
* corefile.c, * symtab.c: Update throughout for bfd section
macro and function changes.
ld/
* ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c,
* emultempl/aarch64elf.em, * emultempl/aix.em,
* emultempl/armcoff.em, * emultempl/armelf.em,
* emultempl/cr16elf.em, * emultempl/cskyelf.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update
throughout for bfd section macro and function changes.
libctf/
* ctf-open-bfd.c: Update throughout for bfd section macro changes.
opcodes/
* arc-ext.c: Update throughout for bfd section macro changes.
sim/
* common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c,
* erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c,
* m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c,
* rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c,
* rx/trace.c: Update throughout for bfd section macro changes.
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This patch adds support for MVE VCTP instruction in assembler.
gas ChangeLog:
2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic.
(do_mve_vctp): Add function to encode VCTP instruction.
* testsuite/gas/arm/mve-vctp-bad.d: New test.
* testsuite/gas/arm/mve-vctp-bad.l: Likewise.
* testsuite/gas/arm/mve-vctp-bad.s: Likewise.
* testsuite/gas/arm/mve-vctp.d: Likewise.
* testsuite/gas/arm/mve-vctp.s: Likewise.
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correctly.
This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b".
a: VMOV<c><q> <Dd>, <Dm>
b: VMOV<c><q>.F64 <Dd>, <Dm>
gas/ChangeLog:
2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_neon_mov): Modify "if" statement.
* testsuite/gas/arm/mve-vmov-bad-3.d: New test.
* testsuite/gas/arm/mve-vmov-bad-3.l: Likewise.
* testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
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instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction.
gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector
register to both the arguments in VMOV instruction.
* testsuite/gas/arm/mve-vmov-1.d: Modify.
* testsuite/gas/arm/mve-vmov-1.s: Likewise.
* testsuite/gas/arm/mve-vorr.d: Likewise.
opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
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This patch adds support for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.
Related specifications can be found at https://developer.arm.com/ip-products/processors.
gas/ChangeLog:
* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,
and Cortex-A76AE.
* doc/c-arm.texi: Document new processors.
* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.
* testsuite/gas/arm/cpu-cortex-a77.d: New test.
* testsuite/gas/arm/cpu-cortex-m35p.d: New test.
bfd/ChangeLog:
* cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
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The tests were failing due to md_atof trying to do word-wise endian
switching on the float16 (for little-endian targets sometimes
multi word values have their word order changed).
However since a float16 is only 1 word wide, it would end up writing
incorrect data, as you cannot switch the word order of just one word.
* config/tc-arm.c (md_atof): Add precision check. Formatting.
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This is a change to the first published specifications [1][a] but since there is no hardware
out there that uses the old instructions we do not want to support the old variant.
This changes are done based on the latest published specifications [1][b].
[1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual
[a] version bf
[b] version bh
gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
48 or 64.
(parse_operands): Add case OP_I48_I64.
(do_mve_scalar_shift1): Add function to encode the MVE shift
instructions with 4 arguments.
* testsuite/gas/arm/mve-shift-bad.l: Modify.
* testsuite/gas/arm/mve-shift-bad.s: Likewise.
* testsuite/gas/arm/mve-shift.d: Likewise.
* testsuite/gas/arm/mve-shift.s: Likewise.
opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
cases MVE_SQRSHRL and MVE_UQRSHLL.
(print_insn_mve): Add case for specifier 'k' to check
specific bit of the instruction.
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point numbers to the assembler.
Half precision floating point numbers will be encoded using the IEEE 754
half precision floating point format - 16 bits in total, 1 for sign, 5
for exponent and 10 bits of mantissa.
This patch implements the float16 directive for both the IEEE 754 format
and the Arm alternative format for the Arm backend.
The syntax of the directive is:
.float16 <0-n decimal numbers>
e.g.
.float16 12.0
.float16 0.23, 433.1, 0.06
The Arm alternative format is almost identical to the IEEE 754 format,
except that it doesn't encode for NaNs or Infinity (instead an exponent
of 0x1F represents a normalized number in the range 65536 to 131008).
The alternative format is documented in the reference manual:
https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439
Which format is used is controlled by the .float16_format <format>
directive, where if <format> = ieee, then use the IEEE 754
half-precision format else if <format> = alternative, then use the
Arm alternative format
Or the format can be set on the command line via the -mfp16-format
option that has a similar syntax. -mfp16-format=<ieee|alternative>.
This also fixes the format and it cannot be changed by any directives.
Once the format has been set (either by the command line option or a directive) it cannot be changed,
and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the
line being ignored.
For ELF targets the appropriate EABI attribute will be written out at the end of assembling
if the format has been explicitly specified. If no format has been explicitly specified then no
EABI attributes will be written.
If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008
format by default until the format is fixed or changed with the float16_format directive.
gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.
(md_atof): Set precision for float16 type.
(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative
format.
(set_fp16_format): Parse a float16_format directive.
(arm_parse_fp16_opt): Parse the fp16-format command line option.
(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.
* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to
arm_is_largest_exponent_ok.
(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.
* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=
* testsuite/gas/arm/float16-bad.d: New test.
* testsuite/gas/arm/float16-bad.l: New test.
* testsuite/gas/arm/float16-bad.s: New test.
* testsuite/gas/arm/float16-be.d: New test.
* testsuite/gas/arm/float16-format-bad.d: New test.
* testsuite/gas/arm/float16-format-bad.l: New test.
* testsuite/gas/arm/float16-format-bad.s: New test.
* testsuite/gas/arm/float16-format-opt-bad.d: New test.
* testsuite/gas/arm/float16-format-opt-bad.l: New test.
* testsuite/gas/arm/float16-le.d: New test.
* testsuite/gas/arm/float16.s: New test.
* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.
* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.
* testsuite/gas/arm/float16-eabi-no-format.d: New test.
* testsuite/gas/arm/float16-eabi.s: New test.
* config/atof-ieee.c (H_PRECISION): Macro for precision of float16
type.
(atof_ieee): Set precision and exponent bits for encoding float16
types.
(gen_to_words): NaN and Infinity encoding for float16.
(ieee_md_atof): Set precision for encoding float16 type.
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VQ(R)DMLAH and VQ(R)DMLASH MVE instructions.
Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183
gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
(do_neon_qrdmlah): Use N_S_32 macro.
* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.
opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
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specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size.
The instructions that this change apply to are:
VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH
The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf
Fixed this by removing the check for this warning from GAS as well as opcodes.
Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size
and the same source and destination operand. Also fixed tests that would previously check for this warning.
gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmladh.d: New tests.
* testsuite/gas/arm/mve-vqdmladh.s: New tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.
opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
instructions as UNPREDICTABLE.
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4 bits (0xF) could be passed to the SMC (Secure Monitor Call) instruction.
For example, this code is invalid:
smc #0x6951
The code would previously check for and encode for up to 16 bit immediate values, however
this immediate should instead be only a 4 bit value
(as documented herehttps://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf ).
Fixed this by adding range checks in the relevant areas and also removing code that would
encode more than the first 4 bits of the immediate (code that is now redundant, as any immediate operand
larger than 0xF would error now anyway).
gas * config/tc-arm.c (do_smc): Add range check for immediate operand.
(do_t_smc): Add range check for immediate operand. Remove
obsolete immediate encoding.
(md_apply_fix): Fix range check. Remove obsolete immediate encoding.
* testsuite/gas/arm/arch6zk.d: Fix test.
* testsuite/gas/arm/arch6zk.s: Fix test.
* testsuite/gas/arm/smc-bad.d: New test.
* testsuite/gas/arm/smc-bad.l: New test.
* testsuite/gas/arm/smc-bad.s: New test.
* testsuite/gas/arm/thumb32.d: Fix test.
* testsuite/gas/arm/thumb32.s: Fix test.
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This patch makes changes to the <spec_reg> operand for VMRS and VMSR
instructions as per the Armv8.1-M Mainline.
New <spec_reg> options to support are:
0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags.
0b1100: VPR, privileged only access to the VPR register.
0b1101: P0, access to VPR.P0 predicate fields
0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating
point context.
0b1111: FPCXT_S, enables saving and restoring of Secure floating point
context
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
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This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
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This patch adds the following instructions which are part of
Armv8.1-M MVE:
ASRL (imm)
ASRL (reg)
LSLL (imm)
LSLL (reg)
LSRL
SQRSHRL
SRQSHR
SQSHLL
SQSHL
SRSHRL
SRSHR
UQRSHLL
UQRSHL
UQSHLL
UQSHL
URSHLL
URSHL
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): New entries for
OP_RRnpcsp_I32 (register or integer operands).
(do_mve_scalar_shift): New.
(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
* testsuite/gas/arm/mve-shift.d: New.
* testsuite/gas/arm/mve-shift.s: New.
* testsuite/gas/arm/mve-shift-bad.d: New.
* testsuite/gas/arm/mve-shift-bad.s: New.
* testsuite/gas/arm/mve-shift-bad.l: New.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (emun mve_instructions): Updated for new instructions.
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
uqshl, urshrl and urshr.
(is_mve_okay_in_it): Add new instructions to TRUE list.
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
(print_insn_mve): Updated to accept new %j,
%<bitfield>m and %<bitfield>n patterns.
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gas/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0
for MOVW replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
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gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (check_simd_pred_availability): Refactor.
(do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability.
(do_neon_dyadic_i64_su): Likewise.
(do_neon_shl): Likewise.
(do_neon_qshl): Likewise.
(do_neon_rshl): Likewise.
(do_neon_logic): Likewise.
(do_neon_dyadic_if_su): Likewise.
(do_neon_addsub_if_i): Likewise.
(do_neon_mac_maybe_scalar): Likewise.
(do_neon_fmac): Likewise.
(do_neon_mul): Likewise.
(do_neon_qdmulh): Likewise.
(do_neon_qrdmlah): Likewise.
(do_neon_abs_neg): Likewise.
(do_neon_sli): Likewise.
(do_neon_sri): Likewise.
(do_neon_qshlu_imm): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_cvttb_1): Likewise.
(do_neon_mvn): Likewise.
(do_neon_rev): Likewise.
(do_neon_dup): Likewise.
(do_neon_mov): Likewise.
(do_neon_rshift_round_imm): Likewise.
(do_neon_sat_abs_neg): Likewise.
(do_neon_cls): Likewise.
(do_neon_clz): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(do_vcmla): Likewise.
(do_vcadd): Likewise.
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and lctp
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): Add new instructions.
(do_t_loloop): Changed to handle tail predication variants.
(md_apply_fix): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-tailpredloop-bad.d: New test.
* testsuite/gas/arm/mve-tailpredloop-bad.l: New test.
* testsuite/gas/arm/mve-tailpredloop-bad.s: New test.
* testsuite/gas/arm/mve-tailpredloop.d: New test.
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gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vshll): New encoding function.
(do_mve_vshlc): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vshlc-bad.d: New test.
* testsuite/gas/arm/mve-vshlc-bad.l: New test.
* testsuite/gas/arm/mve-vshlc-bad.s: New test.
* testsuite/gas/arm/mve-vshll-bad.d: New test.
* testsuite/gas/arm/mve-vshll-bad.l: New test.
* testsuite/gas/arm/mve-vshll-bad.s: New test.
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gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_shl_imm): Accept MVE variants.
(do_neon_shl): Likewise.
(do_neon_qshl_imm): Likewise.
(do_neon_qshl): Likewise.
(do_neon_qshlu_imm): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vqshl-bad.d: New test.
* testsuite/gas/arm/mve-vqshl-bad.l: New test.
* testsuite/gas/arm/mve-vqshl-bad.s: New test.
* testsuite/gas/arm/mve-vshl-bad.d: New test.
* testsuite/gas/arm/mve-vshl-bad.l: New test.
* testsuite/gas/arm/mve-vshl-bad.s: New test.
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vsri, vrev16, vrev32 and vrev64
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_sli): Accept MVE variants.
(do_neon_sri): Likewise.
(do_neon_rev): Likewise.
(do_neon_rshift_round_imm): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vrev-bad.d: New test.
* testsuite/gas/arm/mve-vrev-bad.l: New test.
* testsuite/gas/arm/mve-vrev-bad.s: New test.
* testsuite/gas/arm/mve-vshr-bad.d: New test.
* testsuite/gas/arm/mve-vshr-bad.l: New test.
* testsuite/gas/arm/mve-vshr-bad.s: New test.
* testsuite/gas/arm/mve-vsli-bad.d: New test.
* testsuite/gas/arm/mve-vsli-bad.l: New test.
* testsuite/gas/arm/mve-vsli-bad.s: New test.
* testsuite/gas/arm/mve-vsri-bad.d: New test.
* testsuite/gas/arm/mve-vsri-bad.l: New test.
* testsuite/gas/arm/mve-vsri-bad.s: New test.
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