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path: root/gas/config/tc-arm.c
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2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni1-1/+9
For mve vldr/vstr instructions assembler is throwing wrong error message. Instead of 'Error: syntax error' assembler fails with 'Error: lo register required'. This patch fixes the issue. eg: $ cat x.s .syntax unified .thumb vldrb.s16 q0, r0 Before this patch: $ arm-none-eabi-as x.s -march=armv8.1-m.main+mve -mfloat-abi=hard x.s: Assembler messages: x.s:4: Error: lo register required -- `vldrb.s16 q0,r0' After this patch: $ arm-none-eabi-as x.s -march=armv8.1-m.main+mve -mfloat-abi=hard x.s: Assembler messages: x.s:4: Error: syntax error -- `vldrb.s16 q0,r0' gas/ChangeLog: 2020-10-21 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/26763 * config/tc-arm.c (parse_address_main): Add new MVE addressing mode check. * testsuite/gas/arm/mve-vldr-vstr-bad.d: New test. * testsuite/gas/arm/mve-vldr-vstr-bad.l: Likewise. * testsuite/gas/arm/mve-vldr-vstr-bad.s: Likewise.
2020-10-05[PATCH][GAS][arm] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-1/+1
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Update Cortex-X1 feature flags.
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+6
bfd/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * cpu-arm.c: Add cortex-a78 and cortex-a78ae. gas/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. * doc/c-arm.texi: Update docs. * NEWS: Update news. * testsuite/gas/arm/cpu-cortex-a78.d: New test. * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus1-0/+3
bfd * cpu-arm.c: (processors) Add Cortex-X1. gas * config/tc-arm.c: (arm_cpus): Add Cortex-X1. * doc/c-arm.texi: Document -mcpu=cortex-x1. * testsuite/gas/arm/cpu-cortex-x1.d: New test.
2020-09-28arm: Add missing Neoverse V1 featureAlex Coplan1-1/+3
This simple follow-on patch adds a feature bit (FP16) that was missing from the initial Neoverse V1 support. gas/ChangeLog: * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan1-0/+3
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse V1. * doc/c-arm.texi: Document Neoverse V1 support.
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan1-0/+5
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the AArch32 assembler. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
2020-09-15PR26610, ARM's "VFPv3 vldr to vmov" gas testcase failAlan Modra1-19/+20
I removed a few too many parentheses in git commit 7af677524e2. This patch fixes that problem, rewriting the expression so it won't happen again. The patch also avoids more UB with shifts of signed values. PR 26610 * config/tc-arm.c (move_or_literal_pool): Correct extraction of bignum. Use unsigned "v" (is_double_a_single): Make "v" and "mantissa" unsigned. Formatting. (double_to_single): Likewise.
2020-09-01PR26420, PR26421, PR26425, PR26427 UBSAN: tc-arm.c left shiftsAlan Modra1-78/+78
PR 26420 PR 26421 PR 26425 PR 26427 * config/tc-arm.c (struct arm_it): Make size, size_req, cond and uncond_value unsigned. (parse_vfp_reg_list): Make setmask unsigned, vpr_str_len size_t. (parse_big_immediate): Cast generic_bignum elements to unsigned. (encode_thumb32_immediate): Shift left 0xffU. (double_to_single): Make sign unsigned. Tidy. (move_or_literal_pool): Cast LITTLE_NUM elements to uint64_t or valueT. (vfp_or_neon_is_neon): Adjust inst.uncond_value expression. (md_assemble): Likewise. (handle_pred_state): Make cond unsigned. (thumb32_negate_data_op): Make variables unsigned. (md_apply_fix): Make value and newval unsigned, adjust uses.
2020-08-25PR26426, ASAN: neon_quad tc-arm.c:15175Alan Modra1-0/+5
PR 26426 * config/tc-arm.c (do_neon_mvn, do_neon_swp): Bail out on NS_NULL shape.
2020-08-24Remove "memory exhausted" messagesAlan Modra1-10/+9
Since we use xcalloc to set up hash table memory, htab_create won't ever return a failure. * config/tc-aarch64.c (md_begin): Don't bother checking for out of memory failure from str_htab_create. * config/tc-arc.c (arc_insert_opcode, md_begin): Likewise. (arc_extcorereg, arc_stralloc): Likewise. * config/tc-arm.c (md_begin): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. * config/tc-score.c (s3_build_reg_hsh, s3_begin): Likewise. * config/tc-score7.c (s7_build_reg_hsh, s7_begin): Likewise.
2020-08-24gcc-4 -Og false positive "may be used uninitialised"Alan Modra1-6/+4
binutils/ * readelf.c (dump_section_as_strings) Avoid false positive "may be used uninitialised". gas/ * config/tc-arm.c (move_or_literal_pool): Avoid false positive "may be used uninitialised". (opcode_lookup): Likewise.
2020-08-23PR26513, 629310abec breaks assembling PowerPC Linux kernelsAlan Modra1-22/+23
Inserting with replacement is wrong for some gas hash table uses. This patch implements an htab_insert that conditionally replaces, and similarly for str_hash_insert. str_hash_insert with replace=0 is roughly equivalent to the older hash_insert, and str_hash_insert with replace=1 to the older hash_jam, but return values are different. I found it useful to know whether the slot was occupied prior to inserting/replacing. I've also reinstated the fatal errors on messing up opcode tables with duplicates. PR 26513 * hash.h (htab_insert): Update prototype and comment. (struct string_tuple): Make "value" a const void*. (string_tuple_alloc): Likewise. (str_hash_find, str_hash_find_n): Cast returned value. (str_hash_insert): Add "replace" parameter, and return slot pointer. Free alloc'd element when not inserted. * hash.c (htab_insert): Likewise. Return slot when element exists, otherwise return NULL. * read.c (pop_insert): Insert into hash table without first searching. * config/tc-avr.c (md_begin): Likewise. * config/tc-msp430.c (md_begin): Likewise. * config/tc-nds32.c (nds32_init_nds32_pseudo_opcodes): Likewise. * config/tc-v850.c (md_begin): Likewise. * macro.c (do_formals, define_macro, macro_expand_body): Likewise. (delete_macro): Delete from hash table. * config/tc-tic54x.c (subsym_create_or_replace): Correct logic. * symbols.c (local_symbol_make, symbol_table_insert): Allow replacement of hash table entries. * config/obj-coff-seh.c (seh_hash_insert): Likewise. * config/obj-coff.c (tag_insert): Likewise. * config/tc-iq2000.c (iq2000_add_macro): Likewise. * config/tc-m68k.c (md_begin): Likewise for aliases. * config/tc-tic4x.c (tic4x_asg): Likewise. * config/tc-tic6x.c (md_begin): Likewise. * dw2gencfi.c (dwcfi_hash_find_or_make): Disallow replacement of hash table entries. * ecoff.c (add_string, get_tag): Likewise. * macro.c (expand_irp): Likewise. * config/obj-elf.c (build_additional_section_info): Likewise. * config/tc-aarch64.c (insert_reg_alias): Likewise. (checked_hash_insert): Likewise. * config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise. * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. (declare_addrtype, md_begin, arc_extcorereg): Likewise. * config/tc-arm.c (insert_reg_alias): Likewise. (arm_tc_equal_in_insn, md_begin): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-csky.c (md_begin): Likewise. * config/tc-d10v.c (md_begin): Likewise. * config/tc-dlx.c (md_begin): Likewise. * config/tc-ft32.c (md_begin): Likewise. * config/tc-h8300.c (md_begin): Likewise. * config/tc-hppa.c (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. (md_begin, dot_alias): Likewise. * config/tc-m68hc11.c (md_begin): Likewise. * config/tc-m68k.c (md_begin): Likewise. * config/tc-mcore.c (md_begin): Likewise. * config/tc-microblaze.c (md_begin): Likewise. * config/tc-mips.c (md_begin): Likewise. * config/tc-mmix.c (md_begin): Likewise. * config/tc-mn10200.c (md_begin): Likewise. * config/tc-mn10300.c (md_begin): Likewise. * config/tc-moxie.c (md_begin): Likewise. * config/tc-nds32.c (nds32_relax_hint, md_begin): Likewise. * config/tc-nios2.c (md_begin): Likewise. * config/tc-ns32k.c (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. * config/tc-pj.c (fake_opcode, md_begin): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. * config/tc-pru.c (md_begin): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. (riscv_init_csr_hash): Likewise. * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. * config/tc-score.c (s3_insert_reg): Likewise. (s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (s7_build_score_ops_hsh): Likewise. (s7_build_dependency_insn_hsh, s7_insert_reg): Likewise. * config/tc-sh.c (md_begin): Likewise. * config/tc-sparc.c (md_begin): Likewise. * config/tc-spu.c (md_begin): Likewise. * config/tc-tic30.c (md_begin): Likewise. * config/tc-tic4x.c (tic4x_inst_insert): Likewise. * config/tc-tic54x.c (stag_add_field_symbols, md_begin): Likewise. (tic54x_endstruct, tic54x_var, tic54x_macro_info): Likewise. (subsym_substitute): Likewise. * config/tc-tilegx.c (md_begin): Likewise. * config/tc-tilepro.c (md_begin): Likewise. * config/tc-vax.c (vip_begin): Likewise. * config/tc-wasm32.c (md_begin): Likewise. * config/tc-xgate.c (md_begin): Likewise. * config/tc-z8k.c (md_begin): Likewise. * testsuite/gas/ppc/dcbt.d, * testsuite/gas/ppc/dcbt.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * ecoff.c (add_string): Report fatal error on duplicates. * config/tc-alpha.c (md_begin): Likewise. * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. (declare_addrtype, md_begin, arc_extcorereg): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-dlx.c (md_begin): Likewise. * config/tc-hppa.c (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. (md_begin): Likewise. * config/tc-m68k.c (md_begin): Likewise. * config/tc-mips.c (md_begin): Likewise. * config/tc-nios2.c (md_begin): Likewise. * config/tc-ns32k.c (md_begin): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. * config/tc-pru.c (md_begin): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. * config/tc-sparc.c (md_begin): Likewise. * config/tc-tic30.c (md_begin): Likewise. * config/tc-tic4x.c (tic4x_inst_insert): Likewise. * config/tc-tilegx.c (md_begin): Likewise. * config/tc-tilepro.c (md_begin): Likewise. * config/tc-vax.c (vip_begin): Likewise. * config/tc-alpha.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-cr16.c, * config/tc-csky.c, * config/tc-i386.c, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-microblaze.c, * config/tc-ns32k.c, * config/tc-pj.c, * config/tc-ppc.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-xgate.c: Formatting.
2020-08-21Rearrange symbol_create parametersAlan Modra1-5/+5
These functions take an offset within frag, frag within section, and section parameter. So it makes sense to order the parameters as section, frag, offset. * symbols.h (symbol_new, symbol_create, local_symbol_make), (symbol_temp_new): Arrange params as section, frag, offset. * symbols.c: Adjust to suit. * as.c: Likewise. * cgen.c: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * expr.c: Likewise. * itbl-ops.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * subsegs.c: Likewise. * config/obj-coff.c: Likewise. * config/obj-elf.c: Likewise. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-csky.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise.
2020-08-20Port gas/config/* to str_htab.Martin Liska1-59/+62
* config/obj-coff-seh.c (seh_hash_insert): Port to use new str_htab type. (seh_hash_find): Likewise. (seh_hash_find_or_make): Likewise. * config/obj-coff.c (tag_init): Likewise. (tag_insert): Likewise. (tag_find): Likewise. * config/obj-elf.c (struct group_list): Likewise. (build_additional_section_info): Likewise. (free_section_idx): Likewise. (elf_adjust_symtab): Likewise. (elf_frob_file_after_relocs): Likewise. * config/tc-aarch64.c (INSN_SIZE): Likewise. (parse_reg): Likewise. (insert_reg_alias): Likewise. (create_register_alias): Likewise. (s_unreq): Likewise. (parse_shift): Likewise. (parse_pldop): Likewise. (parse_barrier): Likewise. (parse_barrier_psb): Likewise. (parse_bti_operand): Likewise. (parse_sys_reg): Likewise. (parse_sys_ins_reg): Likewise. (lookup_mnemonic): Likewise. (opcode_lookup): Likewise. (parse_operands): Likewise. (checked_hash_insert): Likewise. (sysreg_hash_insert): Likewise. (fill_instruction_hash_table): Likewise. (md_begin): Likewise. * config/tc-alpha.c (struct alpha_reloc_tag): Likewise. (get_alpha_reloc_tag): Likewise. (assemble_tokens_to_insn): Likewise. (assemble_tokens): Likewise. (md_begin): Likewise. * config/tc-arc.c (arc_find_opcode): Likewise. (arc_insert_opcode): Likewise. (find_opcode_match): Likewise. (declare_register): Likewise. (declare_addrtype): Likewise. (md_begin): Likewise. (arc_parse_name): Likewise. (tc_arc_regname_to_dw2regnum): Likewise. (arc_extcorereg): Likewise. * config/tc-arm.c (MVE_BAD_QREG): Likewise. (arm_reg_parse_multi): Likewise. (parse_reloc): Likewise. (insert_reg_alias): Likewise. (create_register_alias): Likewise. (s_unreq): Likewise. (parse_shift): Likewise. (parse_psr): Likewise. (parse_cond): Likewise. (parse_barrier): Likewise. (do_vfp_nsyn_opcode): Likewise. (opcode_lookup): Likewise. (arm_tc_equal_in_insn): Likewise. (md_begin): Likewise. * config/tc-avr.c (md_begin): Likewise. (avr_ldi_expression): Likewise. (md_assemble): Likewise. (avr_update_gccisr): Likewise. (avr_emit_insn): Likewise. * config/tc-cr16.c (get_register): Likewise. (get_register_pair): Likewise. (get_index_register): Likewise. (get_index_register_pair): Likewise. (get_pregister): Likewise. (get_pregisterp): Likewise. (initialise_reg_hash_table): Likewise. (md_begin): Likewise. (cr16_assemble): Likewise. (md_assemble): Likewise. * config/tc-cris.c (cris_insn_first_word_frag): Likewise. (md_begin): Likewise. (cris_process_instruction): Likewise. * config/tc-crx.c (get_register): Likewise. (get_copregister): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-csky.c (md_begin): Likewise. (parse_opcode): Likewise. (get_operand_value): Likewise. (v1_work_jbsr): Likewise. (v2_work_rotlc): Likewise. (v2_work_bgeni): Likewise. (v2_work_not): Likewise. * config/tc-d10v.c (sizeof): Likewise. (md_begin): Likewise. (do_assemble): Likewise. (md_apply_fix): Likewise. * config/tc-d30v.c (sizeof): Likewise. (md_begin): Likewise. (do_assemble): Likewise. * config/tc-dlx.c (RELOC_DLX_VTENTRY): Likewise. (md_begin): Likewise. (machine_ip): Likewise. * config/tc-ft32.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-h8300.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. (i386_print_statistics): Likewise. (parse_insn): Likewise. (process_operands): Likewise. (i386_index_check): Likewise. (parse_real_register): Likewise. * config/tc-ia64.c (dot_rot): Likewise. (dot_entry): Likewise. (declare_register): Likewise. (md_begin): Likewise. (ia64_parse_name): Likewise. (md_assemble): Likewise. (dot_alias): Likewise. (do_alias): Likewise. (ia64_adjust_symtab): Likewise. (do_secalias): Likewise. (ia64_frob_file): Likewise. * config/tc-m68hc11.c (m68hc11_print_statistics): Likewise. (md_begin): Likewise. (print_insn_format): Likewise. (md_assemble): Likewise. * config/tc-m68k.c (tc_gen_reloc): Likewise. (m68k_ip): Likewise. (md_begin): Likewise. * config/tc-mcore.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-microblaze.c (md_begin): Likewise. (md_assemble): Likewise. (md_apply_fix): Likewise. * config/tc-mips.c (nopic_need_relax): Likewise. (md_begin): Likewise. (macro_build): Likewise. (mips16_macro_build): Likewise. (mips_lookup_insn): Likewise. (mips_ip): Likewise. (mips16_ip): Likewise. * config/tc-mmix.c (sizeof): Likewise. (mmix_md_begin): Likewise. (md_assemble): Likewise. * config/tc-mn10200.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-mn10300.c (HAVE_AM30): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-moxie.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-msp430.c (md_begin): Likewise. (msp430_operands): Likewise. (md_assemble): Likewise. * config/tc-nds32.c (PV_DONT_CARE): Likewise. (builtin_isreg): Likewise. (builtin_regnum): Likewise. (nds32_init_nds32_pseudo_opcodes): Likewise. (nds32_lookup_pseudo_opcode): Likewise. (nds32_relax_hint): Likewise. (md_begin): Likewise. (nds32_find_reloc_table): Likewise. (nds32_elf_append_relax_relocs_traverse): Likewise. (nds32_relax_branch_instructions): Likewise. (md_convert_frag): Likewise. (nds32_elf_analysis_relax_hint): Likewise. (tc_nds32_regname_to_dw2regnum): Likewise. * config/tc-nios2.c (nios2_opcode_lookup): Likewise. (nios2_reg_lookup): Likewise. (nios2_ps_lookup): Likewise. (md_begin): Likewise. * config/tc-ns32k.c (struct hash_control): Likewise. (parse): Likewise. (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-pj.c (fake_opcode): Likewise. (alias): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. (md_assemble): Likewise. * config/tc-pru.c (pru_opcode_lookup): Likewise. (pru_reg_lookup): Likewise. (md_begin): Likewise. (md_end): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_set_arch): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (enum reg_class): Likewise. (hash_reg_name): Likewise. (riscv_init_csr_hash): Likewise. (reg_csr_lookup_internal): Likewise. (reg_lookup_internal): Likewise. (init_opcode_hash): Likewise. (md_begin): Likewise. (DECLARE_CSR): Likewise. (macro_build): Likewise. (riscv_ip): Likewise. * config/tc-s390.c (register_name): Likewise. (s390_setup_opcodes): Likewise. (md_begin): Likewise. (md_assemble): Likewise. (s390_insn): Likewise. * config/tc-score.c (struct s3_reg_map): Likewise. (s3_score_reg_parse): Likewise. (s3_dependency_type_from_insn): Likewise. (s3_parse_16_32_inst): Likewise. (s3_parse_48_inst): Likewise. (s3_insert_reg): Likewise. (s3_build_reg_hsh): Likewise. (s3_build_score_ops_hsh): Likewise. (s3_build_dependency_insn_hsh): Likewise. (s3_begin): Likewise. * config/tc-score7.c (struct s7_reg_map): Likewise. (s7_score_reg_parse): Likewise. (s7_dependency_type_from_insn): Likewise. (s7_parse_16_32_inst): Likewise. (s7_build_score_ops_hsh): Likewise. (s7_build_dependency_insn_hsh): Likewise. (s7_insert_reg): Likewise. (s7_build_reg_hsh): Likewise. (s7_begin): Likewise. * config/tc-sh.c (EMPTY): Likewise. (md_begin): Likewise. (find_cooked_opcode): Likewise. * config/tc-sparc.c (md_begin): Likewise. (sparc_ip): Likewise. * config/tc-spu.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-tic30.c (md_begin): Likewise. (tic30_operand): Likewise. (tic30_parallel_insn): Likewise. (md_assemble): Likewise. * config/tc-tic4x.c (TIC4X_ALT_SYNTAX): Likewise. (tic4x_asg): Likewise. (tic4x_inst_insert): Likewise. (tic4x_inst_add): Likewise. (md_begin): Likewise. (tic4x_operand_parse): Likewise. (md_assemble): Likewise. * config/tc-tic54x.c (MAX_SUBSYM_HASH): Likewise. (stag_add_field_symbols): Likewise. (tic54x_endstruct): Likewise. (tic54x_tag): Likewise. (tic54x_remove_local_label): Likewise. (tic54x_clear_local_labels): Likewise. (tic54x_var): Likewise. (tic54x_macro_start): Likewise. (tic54x_macro_info): Likewise. (tic54x_macro_end): Likewise. (subsym_isreg): Likewise. (subsym_structsz): Likewise. (md_begin): Likewise. (is_mmreg): Likewise. (is_type): Likewise. (encode_condition): Likewise. (encode_cc3): Likewise. (encode_cc2): Likewise. (encode_operand): Likewise. (tic54x_parse_insn): Likewise. (tic54x_parse_parallel_insn_firstline): Likewise. (subsym_create_or_replace): Likewise. (subsym_lookup): Likewise. (subsym_substitute): Likewise. (tic54x_undefined_symbol): Likewise. * config/tc-tic6x.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-tilegx.c (O_hw2_last_plt): Likewise. (INSERT_SPECIAL_OP): Likewise. (md_begin): Likewise. (tilegx_parse_name): Likewise. (parse_reg_expression): Likewise. (md_assemble): Likewise. * config/tc-tilepro.c (O_tls_ie_load): Likewise. (INSERT_SPECIAL_OP): Likewise. (tilepro_parse_name): Likewise. (parse_reg_expression): Likewise. (md_assemble): Likewise. * config/tc-v850.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-vax.c (md_ri_to_chars): Likewise. (vip_begin): Likewise. (vip): Likewise. (main): Likewise. (md_begin): Likewise. * config/tc-wasm32.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-xgate.c (xgate_parse_operand): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-z8k.c (md_begin): Likewise. (md_assemble): Likewise.
2020-08-12[PATCH] gas: arm: Fix IT-predicated MVE vcvtJoe Ramsay1-8/+10
* config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for NS_FD shape when MVE is present * testsuite/gas/arm/mve-vcvtne-it-bad.d: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.l: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.s: New test. * testsuite/gas/arm/mve-vcvtne-it.d: New test. * testsuite/gas/arm/mve-vcvtne-it.s: New test.
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton1-1/+1
PR 26204 gas * config/tc-arm.c: Fix spelling mistake. * config/tc-riscv.c: Likewise. * config/tc-z80.c: Likewise. * po/gas.pot: Regenerate. ld * lexsup.c: Fix spelling mistake. * po/ld.pot: Regenerate. opcodes * arc-dis.c: Fix spelling mistake. * po/opcodes.pot: Regenerate.
2020-06-25Stop the assembler from generating R_ARM_THM_JMP11 relocations as these are ↵Nick Clifton1-0/+1
not supported by the kernel. PR 26141 * config/tc-arm.c (arm_force_relocation): Force resolution of BFD_RELOC_THUMB_PCREL_BRANCH12 relocations. * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan1-0/+7
gas/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (insns): Add dfb. * testsuite/gas/arm/dfb.d: New test. * testsuite/gas/arm/dfb.s: Input for test. opcodes/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * arm-dis.c (arm_opcodes): Add dfb. (thumb32_opcodes): Add dfb.
2020-05-21Replace "if (x) free (x)" with "free (x)", gasAlan Modra1-6/+3
* atof-generic.c: Replace "if (x) free (x)" with "free (x)" throughout. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-tic30.c: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * testsuite/gas/all/test-gen.c: Likewise.
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov1-6/+10
PR 25992 gas * config/tc-arm.c : Add arm_ext_v8r feature. (it_fsm_post_encode): Check arm_ext_v8r feature. (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-04gas: PR 25863: Fix scalar vmul inside it block when assembling for MVEAndre Simoes Dias Vieira1-9/+3
This fixes PR 25863 by fixing the condition in the parsing of vmul in do_mve_vmull. It also simplifies the code in there fixing latent issues that would lead to NEON code being accepted when it shouldn't. gas/ChangeLog: 2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com> PR gas/25863 * config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul. * testsuite/gas/arm/mve-scalar-vmult-it.d: New test. * testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
2020-03-13gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVEAndre Vieira1-3/+12
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e' as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with lt and le conditions to be initially parsed as vaddl and vsubl. This means the operand parsing for these must allow for the same operands as the scalar vadd and vsub. I had forgotten to do this and this patch remedies that oversight. gas/ChangeLog: 2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25660 * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ. (parse_operands): Handle new operand codes. (do_neon_dyadic_long): Make shape check accept the scalar variants. (asm_opcode_insns): Fix operand codes for vaddl and vsubl. * testsuite/gas/arm/mve-vaddsub-it.s: New test. * testsuite/gas/arm/mve-vaddsub-it.d: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test. * testsuite/gas/arm/nomve-vaddsub-it.d: New test.
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load ↵Alexandre Oliva1-0/+3
instruction is detected in a section with insufficient alignment. * config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is detected in a section which does not have at least 4 byte alignment. * testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive. * testsuite/gas/arm/ldr-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of disassembly, ignoring any NOPs that may have been inserted because of section alignment. * testsuite/gas/arm/ldr-t.d: Likewise.
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson1-24/+6
The implementation of the Arm CDE CX*A instructions doesn't allow a condition code on the instructions but does allow the instruction in an ITBlock. The specification has been recently updated, though this is yet to be published. The instructions now should allow a suffix, and should behave in the standard way around ITBlocks. This patch removes the custom pred_instruction_type and handling for these instructions, and uses the standard INSIDE_IT_INSN predication type to describe the new instructions. gas/ChangeLog: 2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (enum pred_instruction_type): Remove NEUTRAL_IT_NO_VPT_INSN predication type. (cxn_handle_predication): Modify to require condition suffixes. (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. * testsuite/gas/arm/cde-scalar.s: Update test. * testsuite/gas/arm/cde-warnings.l: Update test. * testsuite/gas/arm/cde-warnings.s: Update test.
2020-02-26gas gettext warningAlan Modra1-1/+1
gettext("") returns the header entry with meta information, not the empty string. * config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use N_() on empty string.
2020-02-26Indent labelsAlan Modra1-7/+7
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-02-11[binutils][gas] Fix build failure with -std=c89Matthew Malcomson1-2/+2
My previous patch introduced the use of a C99 feature. C99 standard is not required for gas, so this feature should be removed. Committed as obvious. gas/ChangeLog: 2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (vcx_handle_register_arguments): Remove `for` loop initial declaration.
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson1-4/+252
Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson1-3/+318
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-02ELF: Add support for unique section ID to assemblerH.J. Lu1-5/+5
Clang's integrated assembler supports multiple section with the same name: .section .text,"ax",@progbits,unique,1 nop .section .text,"ax",@progbits,unique,2 nop "unique,N" assigns the number, N, as the section ID, to a section. The valid values of the section ID are between 0 and 4294967295. It can be used to distinguish different sections with the same section name. This is useful with -fno-unique-section-names -ffunction-sections. -ffunction-sections by default generates .text.foo, .text.bar, etc. Using the same string can save lots of space in .strtab. This patch adds section_id to bfd_section and reuses the linker internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler internal use to mark valid section_id. It also updates objdump to compare section pointers if 2 sections comes from the same file since 2 different sections can have the same section name. bfd/ PR gas/25380 * bfd-in2.h: Regenerated. * ecoff.c (bfd_debug_section): Add section_id. * section.c (bfd_section): Add section_id. (SEC_ASSEMBLER_SECTION_ID): New. (BFD_FAKE_SECTION): Add section_id. binutils/ PR gas/25380 * objdump.c (sym_ok): Return FALSE if 2 sections are in the same file with different section pointers. gas/ PR gas/25380 * config/obj-elf.c (section_match): Removed. (get_section): Also match SEC_ASSEMBLER_SECTION_ID and section_id. (obj_elf_change_section): Replace info and group_name arguments with match_p. Also update the section ID and flags from match_p. (obj_elf_section): Handle "unique,N". Update call to obj_elf_change_section. * config/obj-elf.h (elf_section_match): New. (obj_elf_change_section): Updated. * config/tc-arm.c (start_unwind_section): Update call to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texi: Document "unique,N" in .section directive. * testsuite/gas/elf/elf.exp: Run "unique,N" tests. * testsuite/gas/elf/section15.d: New file. * testsuite/gas/elf/section15.s: Likewise. * testsuite/gas/elf/section16.s: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. * testsuite/gas/elf/section17.d: Likewise. * testsuite/gas/elf/section17.l: Likewise. * testsuite/gas/elf/section17.s: Likewise. * testsuite/gas/i386/unique.d: Likewise. * testsuite/gas/i386/unique.s: Likewise. * testsuite/gas/i386/x86-64-unique.d: Likewise. * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique. ld/ PR gas/25380 * testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section directives. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-01-31arm: PR gas/25472 Enable DSP instructions with +mveAndre Vieira1-6/+8
We noticed +mve was not enabling DSP instructions as it should, reported in PR 25472. The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions. This patch reflects that in the '+mve' command line option. gas/ChangeLog: 2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com> PR gas/25472 * config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding. (armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for +mve. * testsuite/gas/arm/mve_dsp.d: New test.
2020-01-31[ARM]: Add support for vldmia/vldmdb/vstmia/vstmdb instructions in MVE.Srinath Parvathaneni1-4/+6
This patch adds support for assembly instructions vldmia, vldmdb, vstmia and vstmdb in MVE. This instructions are already supported for Armv8-M Floating-point Extension. gas/ChangeLog: 2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMIA instruction for MVE. (fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB instruction for MVE. (fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA instruction for MVE. (fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB instruction for MVE. * testsuite/gas/arm/mve-ldst.d: New test. * testsuite/gas/arm/mve-ldst.s: Likewise.
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira1-7/+6
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-02[ARM][gas] fix build breakage with gcc-10 by using correct enum typeSzabolcs Nagy1-1/+1
Fixes ../../gas/config/tc-arm.c: In function 'parse_reg_list': ../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion] 1946 | reg = arm_reg_parse (&str, REGLIST_RN); | ^~~~~~~~~~ gas/ChangeLog: * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of REGLIST_RN.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira1-0/+7
Add a -m{no-}warn-restrict-it option to control IT related warnings in ARMv8-A and ARMv8-R. This is disabled by default. Committed on behalf of Wilco Dijkstra. gas/ChangeLog: 2019-12-11 Wilco Dijkstra <wdijkstr@arm.com> * config/tc-arm.c (warn_on_restrict_it): Add new variable. (it_fsm_post_encode): Check warn_on_restrict_it. (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise. * testsuite/gas/arm/armv8-a-bad.d: Likewise. * testsuite/gas/arm/armv8-a-it-bad.d: Likewise. * testsuite/gas/arm/armv8-r-bad.d: Likewise. * testsuite/gas/arm/armv8-r-it-bad.d: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise. * testsuite/gas/arm/udf.d: Likewise.
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira1-0/+1
This patch fixes .arch_extension behaviour. Currently, context table for '.arch_extension' is only set while "-march" processing, but it is not set while .arch processing, so following code is rejected .syntax unified .thumb .arch armv8.1-m.main .arch_extension mve.fp unless -march=armv8.1-m.main is given. Committing on behalf of Vladimir Murzin gas/ChangeLog: 2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com> * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table. * testsuite/gas/arm/mve-arch-ext.s: New. * testsuite/gas/arm/mve-arch-ext.d: New.
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-16/+17
This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu1-44/+65
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM, VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M Floating-point Extension is enabled. According to the ARMv8.1-M ARM, section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point Extension and/or Armv8.1-M MVE". [1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm instruction for mve_ext. (do_vfp_nsyn_pop): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm instruction for mve_ext. (do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks. (insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop, vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead of fpu_vfp_ext_v1xd. * testsuite/gas/arm/v8_1m-mve.s: New. * testsuite/gas/arm/v8_1m-mve.d: New.
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu1-2/+0
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu1-2/+1
This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-4/+83
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson1-0/+47
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat16' directive for the Arm backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function (included in the previous patch) in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-arm.c (md_atof): Add encoding for bfloat16 * testsuite/gas/arm/bfloat16-directive-le.d: New test. * testsuite/gas/arm/bfloat16-directive-be.d: New test. * testsuite/gas/arm/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-24/+217
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu1-0/+31
If the extension is not found in the context sensitive table, the legacy tables are still checked as a fallback. This is particularly useful for Armv8.1-M as it enables the use of '.arch_extension' with the 'mve' and 'mve.fp' extensions which are not part of the legacy table. * config/tc-arm.c (selected_ctx_ext_table) New static variable. (arm_parse_arch): Set context sensitive extension table based on the chosen base architecture. (s_arm_arch_extension): Change to lookup extensions in the new context sensitive tables. * gas/testsuite/gas/arm/mve-ext.s: New. * gas/testsuite/gas/arm/mve-ext.d: New. * gas/testsuite/gas/arm/mvefp-ext.s: New. * gas/testsuite/gas/arm/mvefp-ext.d: New.
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina1-7/+16
The fix for PR12848 introduced an off by one error in the mask, this corrected the negative overflows but not the positive overflows. As a result the conditional branch instructions accepted a too wide positive immediate which resulted in it corrupting the instruction during encoding. The relocation I believe has been incorrectly named, to be consistent with the other relocations it should have been named BRANCH21 which is why the masks for it are confusing. I've replaced the masks with a function out_of_range_p which should make it harder to make such mistakes. The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits and so the mask should be checking for 24-bits for positive overflow. gas/ChangeLog: PR gas/24991 * config/tc-arm.c (out_of_range_p): New. (md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9, BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20, BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25 * testsuite/gas/arm/pr24991.d: New test. * testsuite/gas/arm/pr24991.l: New test. * testsuite/gas/arm/pr24991.s: New test.
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ↵Srinath Parvathaneni1-5/+5
instruction VLDR. This patch modifies assembler to accept the equivalent sized floating and signless datatypes for VLDR instruction but as alias for the unsigned version. gas/ChangeLog: 2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float * and signless datatypes for few cases of VLDR instruction. * testsuite/gas/arm/mve-vldr-bad-3.l: Modify. * testsuite/gas/arm/mve-vldr-bad-3.s: Likewise. * testsuite/gas/arm/mve-vstrldr-1.d: Likewise. * testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
2019-09-23arm bfd.h tidyAlan Modra1-0/+1
bfd/ * bfd-in.h: Move arm declaraions.. * cpu-arm.h: ..to here, new file.. * coff-arm.h: ..and here, new file.. * elf32-arm.h: ..and here, new file. * cpu-arm.c: Include cpu-arm.h. * coff-arm.c: Include cpu-arm.h and coff-arm.h. * elf32-arm.c: Include cpu-arm.h and elf32-arm.h. * pe-arm.c: Move function rename defines later. * pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c: Include cpu-arm.h. ld/ * emultempl/armelf.em: Include elf32-arm.h. * emultempl/pe.em: Move func defines later and include coff-arm.h.
2019-09-19bfd_section_* macrosAlan Modra1-5/+4
This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
generated by cgit v1.1 at 2024-11-19 22:10:28 +0000