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2018-01-09[Arm] Add CSDB instructionJames Greenhalgh1-0/+15
CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-01-02Fix typo in do_mrs function in ARM assembler.Nick Clifton1-1/+1
PR 18119 * config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked version of ARM MRS instruction.
2017-12-18Resolve PR 22493 - the encoding to be used when pushing the stack pointer ↵Nick Clifton1-0/+5
onto the stack. PR 22493 * config/tc-arm.c (encode_ldmstm): Do not use A2 encoding of the PUSH insn when pushing the stack pointer.
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme1-23/+26
Uses of reg_expected_msgs rely on each arm_reg_type enumerator to have a message entry in the same order as the enumerator declaration. This is not clearly stated in the definition of both the arm_reg_type enum and the reg_expected_msgs. Worse, there is nothing to ensure both are kept in sync. As an attempt towards this, this patch uses C99 array designators to ensure that each message is associated with the right arm_reg_type. A comment is also added near the definition of arm_reg_type to point to the reg_expected_msgs array. Finally, the array is synced with arm_reg_type by adding the missing error message for REG_TYPE_RNB. 2017-11-22 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_reg_type): Comment on the link with reg_expected_msgs. (reg_expected_msgs): Initialize using array designators with arm_reg_type index.
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a ↵Tamar Christina1-1/+8
into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
2017-11-08Adds command line support for Armv8.4-A, via the new command line option ↵Jiong Wang1-3/+165
-march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by ↵Tamar Christina1-68/+81
default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions. gas * config/tc-arm.c (arm_cpus): Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD. include * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): New macro.
2017-11-07gas and ld pluralization fixesAlan Modra1-1/+3
gas/ * as.c (main): Properly pluralize messages. * frags.c (frag_grow): Likewise. * read.c (emit_expr_with_reloc, emit_expr_fix): Likewise. (parse_bitfield_cons): Likewise. * write.c (fixup_segment, compress_debug, write_contents): Likewise. (relax_segment): Likewise. * config/tc-arm.c (s_arm_elf_cons): Likewise. * config/tc-cr16.c (l_cons): Likewise. * config/tc-i370.c (i370_elf_cons): Likewise. * config/tc-m68k.c (m68k_elf_cons): Likewise. * config/tc-msp430.c (msp430_operands): Likewise. * config/tc-s390.c (s390_elf_cons, s390_literals): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-tic54x.c (md_assemble): Likewise. * config/tc-xtensa.c (xtensa_elf_cons): Likewise. (xg_expand_assembly_insn): Likewise. * config/xtensa-relax.c (build_transition): Likewise. ld/ * ldlang.c (lang_size_sections_1): Properly pluralize messages. (lang_check_section_addresses): Likewise.
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme1-1/+1
A few coprocessor instructions introduced in ARMv2 are currently accepted by GAS when targeting ARMv1 due to a typo in the code. This patch fixes the issue and introduce a more fine grained testing for coprocessor instructions availability. Coprocessor instructions are grouped as follows: * ARM coprocessor instructions introduced in ARMv2 Includes: ldc, stc, mcr, mrc, cdp, ldcl, stcl Guarded by: ARM_EXT_V2 Tests: copro-arm_v2plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5 Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2 Guarded by: ARM_EXT_V5 Tests: copro-arm_v5plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5TE Includes: mcrr, mrrc Guarded by: ARM_EXT_V5E Tests: copro-arm_v5teplus-arm_v*.d * ARM coprocessor instructions introduced in ARMv6 Includes: mcrr2, mrrc2 Guarded by: ARM_EXT_V6 Tests: copro-arm_v6plus-arm_v*.d * Thumb coprocessor instructions introduced in ARMv6T2 Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc, cdp, ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2, mrrc2 Guarded by: ARM_EXT_V6T2 Tests: copro-thumb_v6t2plus-thumb_v*.d For each of these groups, at least 2 tests are performed: * instructions are not available in earlier architecture * instructions are available in architecture where they were introduced More tests need to be performed when instructions in a group span several assembly files. Note that an instruction in the original coprocessor testcase is changed to unified syntax to allow the testcase to be assembled for ARM and Thumb state. Correct processing of legacy syntax is covered in other testcases. 2017-11-01 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit. * testsuite/gas/arm/copro.s: Split into ... * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while changing it to unified syntax and ... * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ... * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ... * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This. * testsuite/gas/arm/copro.d: Split into ... * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2 and ... * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5 and ... * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target ARMv5TE and ... * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6. * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase. * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang1-2/+0
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions in Thumb mode. It is REG_PC that will cause unpredictable behaviours on both ARM and Thumb. This patch removes the incorrect warning on Thumb mode. Meanwhile the disassembler is updated to use format "<bitfield>R" instead of "<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related code from the disassembler. gas/ * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. * testsuite/gas/arm/crc32-bad.l: Update expected error message. opcode/ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for register operands in CRC instructions. (print_insn_thumb32): Remove "<bitfield>S" support. Updated the comments.
2017-07-24Stop the generation of mapping symbols in the debug sections of ARM and ↵Nick Clifton1-1/+6
AArch64 binaries. PR 21809 * config/tc-aarch64.c (aarch64_init_frag): Do not set a mapping state for frags in debug sections. * config/tc-arm.c (arm_init_frag): Likewise.
2017-07-18Fix spelling typos.Yuri Chornovian1-2/+2
2017-07-05[ARM] Add support for Cortex-A55 and Cortex-A75.James Greenhalgh1-0/+6
This patch adds support for the ARM Cortex-A55 and Cortex-A75 processors. The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions, including support for the 16-bit floating point extensions. The 16-bit floating-point extensions are optional, and we haven't defined an option mapping straight to them thus far, so this patch first needs to add one of those in include/opcode/arm.h, then we can simply add the CPU names as usual in config/tc-arm.c . Tested on arm-none-eabi. 2017-07-05 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75. * doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+11
This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). Tristan - are you ok with the backports ? Applied to trunk. regards Ramana 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-1/+93
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-26Fix compile time warning building gas for arm-wince target.Nick Clifton1-0/+2
* config/tc-arm.c (fpu_any): Only define for ELF based targets.
2017-06-24[ARM] Add support for ARM Cortex-R52 processorThomas Preud'homme1-0/+3
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARM Cortex-R52 processor. === Patch description === This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC extensions. 2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * NEWS: Mention support of ARM Cortex-R52 processor. * config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor. * doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme1-6/+6
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro.
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme1-26/+11
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to remove special casing for ARMv6S-M autodetection. === Motivation === Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor architectures with extra checks in the handler function (do_t_swi) to give an error message when ARMv6-M is targeted and some more special casing in aeabi_set_public_attributes. This was made to exclude these mnemonics for ARMv6-M unless the OS extension is in use. However this logic is superfluous: there is already code to check whether an instruction is available based on the feature bit it is part of and whether the targeted architecture has that feature bit. This patch aims at removing that unneeded complexity. === Patch description === The OS extension is already limited to the ARMv6-M architecture so all this patch does is redefined availability of the ARM_EXT_OS feature bit to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any change either because it already includes ARM_EXT_OS. The patch also make sure that the error message that was given by do_t_swi when SWI/SVC is unavailable is still the same by detecting the situation in md_assemble. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v6m): Delete. (arm_ext_v7m): Delete. (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M profile. (arm_arch_v6m_only): Delete. (do_t_swi): Remove special case for ARMv6S-M. (md_assemble): Display error message previously in do_t_swi when SVC is not available. (insns): Guard swi and svc by arm_ext_os for Thumb mode. (aeabi_set_public_attributes): Remove special case for ARMv6S-M. include/ * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set. (ARM_AEXT_V4T): Likewise. (ARM_AEXT_V5TxM): Likewise. (ARM_AEXT_V5T): Likewise. (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-22Fix compile time warning about unused static variable.Nick Clifton1-1/+1
* config/tc-arm.c (arm_ext_v7m): Add ATTRIBUTE_UNUSED.
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme1-63/+212
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to rework the Tag_CPU_arch build attribute value selection to (i) match architecture or CPU if specified by user without any need for hack and (ii) match an architecture with all the features used if in autodetection mode or return an error. === Motivation === Currently, Tag_CPU_arch build attribute value selection assumes that an architecture is always a superset of architectures released earlier. As such, the logic is to browse architectures in chronological order of release and selecting the Tag_CPU_arch value of the last one to contribute a feature used[1]/requested[2] not contributed by earlier architectures. [1] in case of autodetection mode [2] otherwise, ie. in case of -mcpu/-march or associated directives This logic fails the two objectives mentionned in the Context section. First, due to the assumption it does an architecture can be selected while not having all the features used/requested which fails the second objective. Second, not doing an exact match when an architecture or CPU is selected by the user means the wrong value is chosen when a later architecture provides a subset of the feature bits of an earlier architecture. This is the case for the implementation of ARMv8-R (see later patch). An added benefit of this patch is that it is possible to easily generate more consistent build attribute by setting the feature bits from the architecture matched in aeabi_set_public_attributes in autodetection mode. This is better done as a separate patch because lots of testcase' expected results must then be updated accordingly. === Patch description === The patch changes the main logic for Tag_CPU_arch and Tag_CPU_arch_profile values selection to: - look for an exact match in case an architecture or CPU was specified on the command line or in a directive - select the first released architecture that provides a superset of the feature used in the autodetection case - select the most featureful architecture in case of -march=all The array cpu_arch_ver is updated to include all architectures in order to make the first point work. Note that when looking for an exact match, the architecture with selected extension is tried first and then only the architecture. This is because some architectures are exactly equivalent to an earlier architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS extension) and ARMv6KZ (ARMv6K + security extension) are two such examples. Other adjustments are also necessary in aeabi_set_public_attributes to make this change work. 1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the absence of feature bit used/requested to decide whether to give the default value for empty files (see EABI attribute defaults test). It was previously checking that arch == 0 which would only happen if no feature bit could be matched by any architecture, ie there is no feature bit to match. 2) A fallback to a superset match must exist when no_cpu_selected () returns true. This is because aeabi_set_public_attributes is called again after relaxation and at this point selected_cpu is set from the previous execution of that function. There is therefore no way to check whether the user specified an architecture or CPU. 3) Tag_CPU_arch lines are removed from expected output when the detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch value for pre-ARMv4 architectures and default value for an absent entry is 0. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (fpu_any): Defined from FPU_ANY. (cpu_arch_ver): Add all architectures and sort by release date. (have_ext_for_needed_feat_p): New. (get_aeabi_cpu_arch_from_fset): New. (aeabi_set_public_attributes): Call above function to determine Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use and Tag_THUMB_ISA_use selection logic to check absence of feature bit accordingly. * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build attribute value. * testsuite/gas/arm/attr-march-armv2.d: Likewise. * testsuite/gas/arm/attr-march-armv2a.d: Likewise. * testsuite/gas/arm/attr-march-armv2s.d: Likewise. * testsuite/gas/arm/attr-march-armv3.d: Likewise. * testsuite/gas/arm/attr-march-armv3m.d: Likewise. * testsuite/gas/arm/pr12198-2.d: Likewise. include/ * opcode/arm.h (FPU_ANY): New macro.
2017-06-21[ARM] Allow Thumb division as an extension for ARMv7Thomas Preud'homme1-0/+15
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to allow ARMv7 to be selected in automatic architecture selection in presence of Thumb division instructions. === Motivation === any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect autodetection code to select ARMv7 in presence of Thumb integer division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do not contain these instructions and the idiv extension is only available for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic detection code proposed in the subsequent patch of the series ARMv7 is refused if a Thumb division instruction is present. === Patch description === This patch adds a new "idiv" extension after the existing one that is available to all ARMv7 targets. This new entry is ignored by all current code parsing arm_extensions such that it would be unavailable on the command-line and remain a purely internal hack, easily removed in favor of a better solution later. This is considered though by the subsequent patch reworking automatic detection of build attributes such that ARMv7 is allowed to match in present of Thumb division instructions. For good measure, comments are added in all instances of code browsing arm_extensions to mention the expected behavior in case of duplicate entries as well as a new testcase. 2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable Thumb division for ARMv7 architecture. (arm_parse_extension): Document expected behavior for duplicate entries. (s_arm_arch_extension): Likewise. * testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test. * testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for above test.
2017-06-21[ARM] Rework selection of feature bits to base build attributes onThomas Preud'homme1-16/+24
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to set the feature bits on which to decide what the build attributes should be according to the mode (autodetection, user specified architecture or CPU, or -march/-mcpu=all). === Motivation === Currently, the flags variable which is used to determine the build attribute is constructed from the instruction used (arm_arch_used and thumb_arch_used) as well as the user specified architecture or CPU (selected_cpu). This means when several .arch are specified the resulting feature bits can be such that no architecture provide them all and can thus result in incorrect Tag_CPU_arch. See for instance what having both .arch armv8-a and .arch armv8-m.base would result in. This is not caught by the testsuite because of further bugs in the Tag_CPU_arch build attribute value selection logic (see next patch in the series). === Patch description === As one would expect, this patch solves the problem by setting flags from feature bits used if in autodetection mode [1] and from selected_cpu otherwise. The logic to set arm_ext_v1, arm_ext_v4t and arm_ext_os feature bits is also moved to only run in autodetection mode since otherwise the architecture or CPU would have a consistent set of feature bits already. [1] No architecture or CPU was specified by the user 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Populate flags from feature bits used or selected_cpu depending on whether a CPU was selected by the user.
2017-06-21[ARM] Simplify Tag_DSP_extension selection logicThomas Preud'homme1-23/+5
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to simplify the logic to decide whether to set Tag_DSP_extension. === Motivation === To decide whether to set Tag_DSP_extension, the current code was checking whether the flags had DSP instruction but the architecture selected for Tag_CPU_arch did not have any. This was necessary because extension feature bit were not available separately. This is no longer necessary and can be simplified. === Patch description === The patch change the logic to set Tag_DSP_extension to check whether any DSP feature bit is set in the extension feature bit, as per the definition of that build attribute. The patch also removes all definitions of arm_arch which is now unneeded. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to decide whether to set Tag_DSP_extension build attribute value. Remove now useless arm_arch variable.
2017-06-21[ARM] Keep separation between extensions and architecture bits throughout ↵Thomas Preud'homme1-27/+68
execution === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to keep the distinction between architecture feature bits and extension ones after parsing has occured. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. The previous patch in the patch series makes the distinction possible when parsing -mcpu and .cpu directives but the distinction gets lost after. Similarly feature bits contributed by extensions in -march or .arch_extensions directive are mixed together with architecture extensions. === Patch description === The patch adds new feature bit pointer for extension feature bits. Information from the parsing regarding extensions can then be kept separate in those. This requires adapting arm_parse_extension to deal with two feature bits, allowing the architecture bits to be marked as const. It also requires extra care when setting cpu_variant and selected_cpu because the extension bits are optional since there might not be any extension in use. Note that contrary to cpu feature bits, the extension feature bits are made read/write and are always dynamically allocated. This allows to unconditionally free them in arm_md_post_relax added for this occasion, thereby fixing a longstanding memory leak when arm_parse_extension was invoked (XNEW of ext_fset without corresponding XDELETE). Introduction of arm_md_post_relax is necessary to only free the extension feature bits after aeabi_set_attribute_string has been called for the last time. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (dyn_mcpu_ext_opt): New static variable. (dyn_march_ext_opt): Likewise. (md_begin): Copy extension feature bits alongside architecture ones. Merge extensions feature bits in selected_cpu and cpu_variant if there is some. (arm_parse_extension): Pass architecture and extension feature bits in separate parameters, with architecture bits being read only. Update **opt_p directly rather than *ext_set and initialize it if needed. (arm_parse_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Adapt to change in parameters of arm_parse_extension. (arm_parse_arch): Adapt to change in parameters of arm_parse_extension. (aeabi_set_attribute_string): Make function static. (arm_md_post_relax): New function. (s_arm_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Merge extension feature bits in cpu_variant if there is any. (s_arm_arch): Reset extension feature bit. Set selected_cpu from *mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for consistency with s_arm_cpu. (s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than selected_cpu, allocating it before hand if needed. Set selected_cpu from it and then cpu_variant. (s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant. * config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax. (aeabi_set_public_attributes): Delete external declaration. (arm_md_post_relax): Declare externally.
2017-06-21[ARM] Separate extensions from architectures in arm_cpusThomas Preud'homme1-162/+370
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to distinguish for a CPU the feature bits coming from its architecture from the feature bits coming from extension(s) available in this CPU. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. === Patch description === The patch creates a new field in the arm_cpus table to hold the feature set for the extensions available in each CPU. The existing architecture feature set is then updated to remove those feature bit. The patch also takes advantage of all the lines being changed to reindent the whole table. Note: This patch *adds* a memory leak due to mcpu_cpu_opt sometimes pointing to dynamically allocated feature bits which is never freeed. The subsequent patch in the series solves this issue as well as a preexisting identical issue in arm_parse_extension. The patches are kept separate for ease of review since they are both big enough already. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_cpu_option_table): New ext field. (ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical name field just after the name field. (arm_cpus): Move extension feature bit from value field to ext field, reorder parameter according to changes in ARM_CPU_OPT and reindent. (arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and ext field from the selected arm_cpus entry. (s_arm_cpu): Likewise.
2017-06-06[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-AJiong Wang1-15/+34
For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through the "reject_bad_reg" macro and several scattered checks. This patch only rejects REG_SP in "reject_bad_reg" and several related places for legacy architectures before ARMv8-A. I have checked those affected instructions , all of them qualify such relaxations. Testcases adjusted accordingly. * ld-sp-warn.d was written without .arch and without -march options passed. By default it assumes all architectures, so I deleted the REG_SP warning on ldrsb as it's supported on ARMv8-A. There are actually quite a few seperate tests on other architectures, for example ld-sp-warn-v7.l etc., so there the test for ldrsb on legacy architectures are still covered. * sp-pc-validations-bad-t has been extended to armv8-a. * strex-bad-t.d restricted on armv7-a. * Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*. gas/ * config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A. (parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on ARMv8-A. (do_co_reg): Allow REG_SP for Rd on ARMv8-A. (do_t_add_sub): Likewise. (do_t_mov_cmp): Likewise. (do_t_tb): Likewise. * testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for ldrsb. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test. * testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a. * testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a". * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax.s: New test. * testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
2017-06-05Drop arm support for falkor/qdf24xx targets, not present in released hardware.Jim Wilson1-6/+0
gas/ * config/tc-arm.c (arm_cpus): Delete falkor and qdf24xx entries. * doc/c-arm.texi (-mcpu): Likewise.
2017-05-15Fix use of ARM ADR and ADRl pseudo-instructions with thumb function symbols.Nick Clifton1-1/+18
PR gas/21458 * config/tc-arm.c (do_adr): If the ADR involves a thumb function symbol, ensure that the T bit will be set. (do_adrl): Likewise. (do_t_adr): Likewise. * testsuite/gas/arm/pr21458.s: New test. * testsuite/gas/arm/pr21458.d: New test driver.
2017-04-24[GAS/ARM] Fix expansion of ldr pseudo instructionThomas Preud'homme1-9/+5
The LDR rX, =cst pseudo-instruction suffers from two issues for loading integer constants in Thumb mode: - movs is used if the constant and register can be encoded using that instruction which leads to unexpected behavior due to its flag-setting behavior - mov.w, movw and mvn are used for r13 (sp) and r15 (pc) but these encoding are marked as UNPREDICTABLE This patch fixes those issues and update testing accordingly. 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS. Forbid MOV.W and MOVW if destination is SP or PC. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain expectation of LDR not generating a MOVS for low registers and small constants. Add tests of MOVW generation. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update expected disassembly.
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu1-1/+2
Mark an ALLOC section, which should be placed in special memory area, with SHF_GNU_MBIND. Its sh_info field indicates the special memory type. GNU_MBIND section names start with ".mbind" so that they are placed as orphan sections by linker. All input GNU_MBIND sections with the same sh_type, sh_flags and sh_info are placed in one output GNU_MBIND section. In executable and shared object, create a GNU_MBIND segment for each GNU_MBIND section and its segment type is PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is aligned at page boundary. The assembler syntax: .section .mbind.foo,"adx",%progbits ^ 0: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.foo,"adx",%progbits,0x1 ^ 1: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2 ^ 2: Special memory type. | 'd' for SHF_GNU_MBIND. bfd/ * elf.c (get_program_header_size): Add a GNU_MBIND segment for each GNU_MBIND section and align GNU_MBIND section to page size. (_bfd_elf_map_sections_to_segments): Create a GNU_MBIND segment for each GNU_MBIND section. (_bfd_elf_init_private_section_data): Copy sh_info from input for GNU_MBIND section. binutils/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX. (get_elf_section_flags): Handle SHF_GNU_MBIND. (process_section_headers): Likewise. * testsuite/binutils-all/mbind1.s: New file. * testsuite/binutils-all/objcopy.exp: Run readelf test on mbind1.s. gas/ * NEWS: Mention support for ELF SHF_GNU_MBIND. * config/obj-elf.c (section_match): New. (get_section): Match both sh_info and group name. (obj_elf_change_section): Add argument for sh_info. Pass both sh_info and group name to get_section. Issue an error for SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info. (obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'. (obj_elf_section): Support SHF_GNU_MBIND section info. * config/obj-elf.h (obj_elf_change_section): Add argument for sh_info. * config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texinfo: Document 'd' for SHF_GNU_MBIND. * testsuite/gas/elf/elf.exp: Run section12a, section12b and section13. * testsuite/gas/elf/section10.d: Updated. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section12.s: New file. * testsuite/gas/elf/section12a.d: Likewise. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.l: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.s: Likewise. include/ * elf/common.h (PT_GNU_MBIND_NUM): New. (PT_GNU_MBIND_LO): Likewise. (PT_GNU_MBIND_HI): Likewise. (SHF_GNU_MBIND): Likewise. ld/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place input GNU_MBIND sections with the same type, attributes and sh_info field into a single output GNU_MBIND section. * testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b. * testsuite/ld-elf/mbind1.s: New file. * testsuite/ld-elf/mbind1a.d: Likewise. * testsuite/ld-elf/mbind1b.d: Likewise. * testsuite/ld-elf/mbind1c.d: Likewise. * testsuite/ld-elf/mbind2a.s: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise.
2017-03-24[GAS/ARM] Fix selected_cpu with default CPU and -mcpuThomas Preud'homme1-2/+2
When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or -march option, selected_cpu will be set to the default CPU. This means the -mcpu is ignored which is surprising behavior. This commit instead sets selected_cpu from the value passed to -mcpu/-march. 2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when CPU_DEFAULT is defined.
2017-03-20[arm] Document missing -mfpu entries.Richard Earnshaw1-3/+3
Nick pointed out that I hadn't documented the new -mfpu option neon-vfpv3 and mentioned that some others were missing. Having looked through the list only one (neon-fp16) really should be documented; the other two entries in the real table should not be documented as they are aliases kept for legacy compatibility reasons. This patch adds the missing entries and notes in the main table that the other two entries should not be documented. I've also fixed a small spelling error in the accompanying text. * config/tc-arm.c (arm_fpus): Note entires that should not be documented. * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and neon-fp16. Fix spelling error.
2017-03-20[arm] Add neon-vfp3 as an alias for neon to -mfpu.Richard Earnshaw1-0/+1
GCC recently added neon-vfpv3 as an alias for neon in -mfpu. This patch adds a similar alias in GAS. * config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-02-13[ARM] Allow immediate without prefix in unified syntax for VCMPThomas Preud'homme1-3/+7
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified syntax. * testsuite/gas/arm/vcmp-noprefix-imm.d: New file. * testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-11/+11
PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-08ARM/GAS: Correct an `index' global shadowing errorMaciej W. Rozycki1-4/+4
Fix a commit 008a97eff0ca ("[GAS][ARM]Generate unpredictable warning for pc used in data processing instructions with register-shifted register operand.") build regression: cc1: warnings being treated as errors .../gas/config/tc-arm.c: In function 'encode_arm_shift': .../gas/config/tc-arm.c:7439: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [tc-arm.o] Error 1 in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command line options used when compiling the binutils."). gas/ * config/tc-arm.c (encode_arm_shift): Rename `index' local variable to `op_index'.
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy1-0/+80
Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy1-0/+18
Add support for VJCVT javascript conversion instruction. gas/ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define. (insns): Add vjcvt. * testsuite/gas/aarch64/armv8_3-a-fp.s: New. * testsuite/gas/aarch64/armv8_3-a-fp.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vjcvt.
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+1
ARMv8.3 is an architectural extension of ARMv8. Add the feature macro and -march=armv8.3-a gas command line option for the ARM target. https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions gas/ * config/tc-arm.c (arm_archs): Add "armv8.3-a". * doc/c-arm.texi (-march): Add "armv8.3-a". include/ * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New. (ARM_ARCH_V8_3A): New.
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani1-5/+5
* as.h: Fix spelling in comments. * config/obj-ecoff.c: Fix spelling in comments. * config/obj-macho.c: Fix spelling in comments. * config/tc-aarch64.c: Fix spelling in comments. * config/tc-arc.c: Fix spelling in comments. * config/tc-arm.c: Fix spelling in comments. * config/tc-avr.c: Fix spelling in comments. * config/tc-cr16.c: Fix spelling in comments. * config/tc-epiphany.c: Fix spelling in comments. * config/tc-frv.c: Fix spelling in comments. * config/tc-hppa.c: Fix spelling in comments. * config/tc-hppa.h: Fix spelling in comments. * config/tc-i370.c: Fix spelling in comments. * config/tc-m68hc11.c: Fix spelling in comments. * config/tc-m68k.c: Fix spelling in comments. * config/tc-mcore.c: Fix spelling in comments. * config/tc-mep.c: Fix spelling in comments. * config/tc-metag.c: Fix spelling in comments. * config/tc-mips.c: Fix spelling in comments. * config/tc-mn10200.c: Fix spelling in comments. * config/tc-mn10300.c: Fix spelling in comments. * config/tc-nds32.c: Fix spelling in comments. * config/tc-nios2.c: Fix spelling in comments. * config/tc-ns32k.c: Fix spelling in comments. * config/tc-pdp11.c: Fix spelling in comments. * config/tc-ppc.c: Fix spelling in comments. * config/tc-riscv.c: Fix spelling in comments. * config/tc-rx.c: Fix spelling in comments. * config/tc-score.c: Fix spelling in comments. * config/tc-score7.c: Fix spelling in comments. * config/tc-sparc.c: Fix spelling in comments. * config/tc-tic54x.c: Fix spelling in comments. * config/tc-vax.c: Fix spelling in comments. * config/tc-xgate.h: Fix spelling in comments. * config/tc-xtensa.c: Fix spelling in comments. * config/tc-z80.c: Fix spelling in comments. * dwarf2dbg.c: Fix spelling in comments. * input-file.h: Fix spelling in comments. * itbl-ops.c: Fix spelling in comments. * read.c: Fix spelling in comments. * stabs.c: Fix spelling in comments. * symbols.c: Fix spelling in comments. * write.c: Fix spelling in comments. * testsuite/gas/all/itbl-test.c: Fix spelling in comments. * testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
2016-11-21[GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL ↵Renlin Li1-2/+5
syntax). gas/ 2016-11-21 Renlin Li <renlin.li@arm.com> PR gas/20827 * config/tc-arm.c (encode_arm_shift): Don't assert for operands not presented. * testsuite/gas/arm/add-shift-two.d: New. * testsuite/gas/arm/add-shift-two.s: New.
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+2
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (cortex-m33): Declare new processor. * doc/c-arm.texi (-mcpu ARM command line option): Document new Cortex-M33 processor. * NEWS: Mention ARM Cortex-M33 support.
2016-11-04Add support for ARM Cortex-M23 processorThomas Preud'homme1-0/+2
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (cortex-m23): Declare new processor. * doc/c-arm.texi (-mcpu ARM command line option): Document new Cortex-M23 processor. * NEWS: Mention ARM Cortex-M23 support.
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar1-0/+3
This adds an option for the Qualcomm falkor core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html This was tested with aarch64 and armhf builds and make check and also by building and running SPEC2006. * config/tc-aarch64.c (aarch64_cpus): Add falkor. * config/tc-arm.c (arm_cpus): Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-arm.texi: Likewise.
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang1-16/+69
gas/ * config/tc-arm.c (SBIT_SHIFT): New. (T2_SBIT_SHIFT): Likewise. (t32_insn_ok): Return TRUE for MOV in ARMv8-M Baseline. (md_apply_fix): Try UINT16 encoding when ARM/Thumb modified immediate encoding failed. * testsuite/gas/arm/archv6t2-bad.s: New error case. * testsuite/gas/arm/archv6t2-bad.l: New error match. * testsuite/gas/arm/archv6t2.s: New testcase. * testsuite/gas/arm/archv6t2.d: New expected result. * testsuite/gas/arm/archv8m.s: New testcase. * testsuite/gas/arm/archv8m-base.d: New expected result. * testsuite/gas/arm/archv8m-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing ↵Renlin Li1-0/+15
instructions with register-shifted register operand. gas/ 2016-10-19 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (encode_arm_shift): Generate unpredictable warning for register-shifted register instructions. * testsuite/gas/arm/shift-bad-pc.d: New. * testsuite/gas/arm/shift-bad-pc.l: New. * testsuite/gas/arm/shift-bad-pc.s: New.
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-1/+11
Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
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