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In a later commit I'll be adding a new version of the ".nt" flag for an
ARC700 extension (NPS400) which does not require this same special
handling.
In this commit I have restricted the special flag handling to only apply
if we are assembling for ARCv2. This is a restructuring commit, and
there should be no user visible changes after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
specially for ARCv2.
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Fix assembler relaxation step for add, ld, mov, mpy and sub
instructions. Add tests to it.
gas/
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
information from input expression.
(assemble_insn): Make sure pcrel is correctly set.
(arc_pcrel_adjust): Compensate for PCL rounding.
* testsuite/gas/arc/relax-add01.d: New file.
* testsuite/gas/arc/relax-add01.s: Likewise.
* testsuite/gas/arc/relax-add02.d: Likewise.
* testsuite/gas/arc/relax-add02.s: Likewise.
* testsuite/gas/arc/relax-add03.d: Likewise.
* testsuite/gas/arc/relax-add03.s: Likewise.
* testsuite/gas/arc/relax-add04.d: Likewise.
* testsuite/gas/arc/relax-add04.s: Likewise.
* testsuite/gas/arc/relax-ld01.d: Likewise.
* testsuite/gas/arc/relax-ld01.s: Likewise.
* testsuite/gas/arc/relax-ld02.d: Likewise.
* testsuite/gas/arc/relax-ld02.s: Likewise.
* testsuite/gas/arc/relax-mov01.d: Likewise.
* testsuite/gas/arc/relax-mov01.s: Likewise.
* testsuite/gas/arc/relax-mov02.d: Likewise.
* testsuite/gas/arc/relax-mov02.s: Likewise.
* testsuite/gas/arc/relax-mpy01.d: Likewise.
* testsuite/gas/arc/relax-mpy01.s: Likewise.
* testsuite/gas/arc/relax-sub01.d: Likewise.
* testsuite/gas/arc/relax-sub01.s: Likewise.
* testsuite/gas/arc/relax-sub02.d: Likewise.
* testsuite/gas/arc/relax-sub02.s: Likewise.
* testsuite/gas/arc/relax-sub03.d: Likewise.
* testsuite/gas/arc/relax-sub03.s: Likewise.
* testsuite/gas/arc/relax-sub04.d: Likewise.
* testsuite/gas/arc/relax-sub04.s: Likewise.
opcodes/
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (UIMM6_20R): Define.
(SIMM12_20): Use above.
(SIMM12_20R): Define.
(SIMM3_5_S): Use above.
(UIMM7_A32_11R_S): Define.
(UIMM7_9_S): Use above.
(UIMM3_13R_S): Define.
(SIMM11_A32_7_S): Use above.
(SIMM9_8R): Define.
(UIMM10_A32_8_S): Use above.
(UIMM8_8R_S): Define.
(W6): Use above.
(arc_relax_opcodes): Use all above defines.
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gas/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.
include/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
flag classes.
opcode/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (arc_disassemble_info): New structure.
(init_arc_disasm_info): New function.
(find_format_from_table): Ignore implicit flags.
(find_format): Update dissassembler private data.
(print_flags): Likewise.
(print_insn_arc): Likewise.
(arc_opcode_to_insn_type): Consider the new added instruction
classes.
(arcAnalyzeInstr): Remove.
(arc_insn_decode): New function.
* arc-dis.h (arc_ldst_writeback_mode): New enum.
(arc_ldst_data_size): Likewise.
(arc_condition_code): Likewise.
(arc_operand_kind): Likewise.
(arc_insn_kind): New struct.
(arc_instruction): Likewise.
(arc_insn_decode): Declare function.
(ARC_Debugger_OperandType): Deleted.
(Flow): Likewise.
(NullifyMode): Likewise.
(allOperandsSize): Likewise.
(arcDisState): Likewise.
(arcAnalyzeInstr): Likewise.
* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
insn_class_t enums.
* arc-opc.c (F_SIZED): New define.
(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
* opcodes/arc-tbl.h: Update instructions to include new
F_CLASS_IMPLICIT flags.
(bbit0, lp): Change class.
(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
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PR gas/21072
* asintl.h: Fix spelling mistakes and typos.
* atof-generic.c: Likewise.
* bit_fix.h: Likewise.
* config/atof-ieee.c: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff-seh.h: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-evax.c: Likewise.
* config/obj-macho.c: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-epiphany.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mep.h: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-msp430.h: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-nios2.h: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-pru.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/te-vms.c: Likewise.
* config/xtensa-relax.c: Likewise.
* doc/as.texinfo: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-nds32.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-riscv.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-tilegx.texi: Likewise.
* doc/c-tilepro.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* itbl-ops.c: Likewise.
* listing.c: Likewise.
* macro.c: Likewise.
* po/gas.pot: Likewise.
* read.c: Likewise.
* struc-symbol.h: Likewise.
* symbols.h: Likewise.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* write.c: Likewise.
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Fix a commit a9752fdf8398 ("[ARC] Sync cpu names with the ones accepted
by GCC.") build regression:
cc1: warnings being treated as errors
.../gas/config/tc-arc.c: In function 'arc_show_cpu_list':
.../gas/config/tc-arc.c:3452: error: declaration of 'spaces' shadows a global declaration
.../gas/../include/libiberty.h:248: error: shadowed declaration is here
make[4]: *** [tc-arc.o] Error 1
in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
gas/
* config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local
variable to `space_buf'.
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gas/
2016-12-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister-1.d: New file.
* testsuite/gas/arc/textauxregister-1.s: Likewise.
* testsuite/gas/arc/textcondcode-err.s: Likewise.
* testsuite/gas/arc/textcoreregister-err.s: Likewise.
* config/tc-arc.c (tokenize_extregister): Return bfd_boolean,
don't check second argument of extension auxiliary register for
signess.
(arc_extcorereg): Consider the return of tokenize_extregister
function call.
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gas/
2016-12-02 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cpu-em-err.s: New file.
* testsuite/gas/arc/cpu-em4-err.s: Likewise.
* testsuite/gas/arc/cpu-fpuda-err.s: Likewise.
* testsuite/gas/arc/cpu-hs-err.s: Likewise.
* testsuite/gas/arc/cpu-quarkse-err.s: Likewise.
* testsuite/gas/arc/noargs_a7.s: Add .cpu.
* config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define.
(ARC_CPU_TYPE_A7xx): Likewise.
(ARC_CPU_TYPE_AV2EM): Likewise.
(ARC_CPU_TYPE_AV2HS): Likewise.
(cpu_types): Update list of known CPU names.
(arc_show_cpu_list): New function.
(md_show_usage): Print accepted CPU names.
(cl_features): New variable.
(arc_select_cpu): Use cl_features.
(arc_option): Allow various .cpu names.
(md_parse_option): Set cl_features.
* doc/c-arc.texi: Update -mcpu and .cpu documentation.
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gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
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* as.h: Fix spelling in comments.
* config/obj-ecoff.c: Fix spelling in comments.
* config/obj-macho.c: Fix spelling in comments.
* config/tc-aarch64.c: Fix spelling in comments.
* config/tc-arc.c: Fix spelling in comments.
* config/tc-arm.c: Fix spelling in comments.
* config/tc-avr.c: Fix spelling in comments.
* config/tc-cr16.c: Fix spelling in comments.
* config/tc-epiphany.c: Fix spelling in comments.
* config/tc-frv.c: Fix spelling in comments.
* config/tc-hppa.c: Fix spelling in comments.
* config/tc-hppa.h: Fix spelling in comments.
* config/tc-i370.c: Fix spelling in comments.
* config/tc-m68hc11.c: Fix spelling in comments.
* config/tc-m68k.c: Fix spelling in comments.
* config/tc-mcore.c: Fix spelling in comments.
* config/tc-mep.c: Fix spelling in comments.
* config/tc-metag.c: Fix spelling in comments.
* config/tc-mips.c: Fix spelling in comments.
* config/tc-mn10200.c: Fix spelling in comments.
* config/tc-mn10300.c: Fix spelling in comments.
* config/tc-nds32.c: Fix spelling in comments.
* config/tc-nios2.c: Fix spelling in comments.
* config/tc-ns32k.c: Fix spelling in comments.
* config/tc-pdp11.c: Fix spelling in comments.
* config/tc-ppc.c: Fix spelling in comments.
* config/tc-riscv.c: Fix spelling in comments.
* config/tc-rx.c: Fix spelling in comments.
* config/tc-score.c: Fix spelling in comments.
* config/tc-score7.c: Fix spelling in comments.
* config/tc-sparc.c: Fix spelling in comments.
* config/tc-tic54x.c: Fix spelling in comments.
* config/tc-vax.c: Fix spelling in comments.
* config/tc-xgate.h: Fix spelling in comments.
* config/tc-xtensa.c: Fix spelling in comments.
* config/tc-z80.c: Fix spelling in comments.
* dwarf2dbg.c: Fix spelling in comments.
* input-file.h: Fix spelling in comments.
* itbl-ops.c: Fix spelling in comments.
* read.c: Fix spelling in comments.
* stabs.c: Fix spelling in comments.
* symbols.c: Fix spelling in comments.
* write.c: Fix spelling in comments.
* testsuite/gas/all/itbl-test.c: Fix spelling in comments.
* testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
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gas/
2016-11-18 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cl-warn.s: New file.
* testsuite/gas/arc/cpu-pseudop-1.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.s: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.s: Likewise.
* testsuite/gas/arc/cpu-warn2.s: Likewise.
* config/tc-arc.c (selected_cpu): Initialize.
(feature_type): New struct.
(feature_list): New variable.
(arc_check_feature): New function.
(arc_select_cpu): Check for .cpu duplicates. Don't overwrite the
current cpu features. Check if a feature is available for a given
cpu.
(md_parse_option): Test if features are available for a given cpu.
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When we match against an address type operand within an instruction it
is important that we match exactly the right address type operand early
on, during the opcode selection phase. If we wait until the operand
insertion phase to check that we have the correct address operand, then
it is too late to select an alternative opcode. This becomes important
only when we have multiple opcodes with the same mnemonic, and operand
lists that differ only in the type of the address operands.
This commit fixes this issue, and adds some example instructions that
require this issue to be fixed (the instructions are identical except
for the address type operand).
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_operands): Add F_DI14.
(arc_flag_classes): Add C_DI14.
* arc-nps400-tbl.h: Add new exc instructions.
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The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
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In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
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When assembling an instruction replace the short_insn boolean flag with
an integer field for holding the instruction length. This is in
preparation for moving to a world where instructions can be 2, 4, 6, or
8 bytes in length.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Replace short_insn flag with
len field.
(apply_fixups): Update to use len field.
(emit_insn0): Simplify code, making use of len field.
(md_convert_frag): Update to use len field.
(assemble_insn): Update to use len field.
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In the ARC assembler, when a cpu type is specified using the .cpu
directive, we rely on the bfd list of arc machine types in order to
validate the cpu name passed in.
This validation is only used in order to check that the cpu type passed
to the .cpu directive matches any machine type selected earlier on the
command line. Once that initial check has passed a full check is
performed using the assemblers internal list of know cpu types.
The problem is that the assembler knows about more cpu types than bfd,
some cpu types known by the assembler are actually aliases for a base
cpu type plus a specific set of assembler extensions. One such example
is NPS400, though more could be added later.
This commit removes the need for the assembler to use the bfd list of
machine types for validation. Instead the error checking, to ensure
that any value passed to a '.cpu' directive matches any earlier command
line selection, is moved into the function arc_select_cpu.
I have taken the opportunity to bundle the 4 separate static globals
that describe the currently selected machine type into a single
structure (called selected_cpu).
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delete.
(arc_target_name): Delete.
(arc_features): Delete.
(arc_mach_type): Delete.
(mach_type_specified_p): Delete.
(enum mach_selection_type): New enum.
(mach_selection_mode): New static global.
(selected_cpu): New static global.
(arc_eflag): Rename to ...
(arc_initial_eflag): ...this, and make const.
(arc_select_cpu): Update comment, new parameter, check how
previous machine type selection was made, and record this
selection. Use selected_cpu instead of old globals.
(arc_option): Remove use of arc_get_mach, instead use
arc_select_cpu to validate machine type selection. Use
selected_cpu over old globals.
(allocate_tok): Use selected_cpu over old globals.
(find_opcode_match): Likewise.
(assemble_tokens): Likewise.
(arc_cons_fix_new): Likewise.
(arc_extinsn): Likewise.
(arc_extcorereg): Likewise.
(md_begin): Update default machine type selection, use
selected_cpu over old globals.
(md_parse_option): Update machine type selection option handling,
use selected_cpu over old globals.
* testsuite/gas/arc/nps400-0.s: Add .cpu directive.
bfd/ChangeLog:
* cpu-arc.c (arc_get_mach): Delete.
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gas/
2016-10-06 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: New file.
* testsuite/gas/arc/leave_enter.s: Likewise.
* testsuite/gas/arc/regnames.d: Likewise.
* testsuite/gas/arc/regnames.s: Likewise.
* config/tc-arc.c (arc_parse_name): Don't match reg names against
confirmed symbol names.
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Comment changes.
bfd/
* coff-h8300.c: Spell fall through comments consistently.
* coffgen.c: Likewise.
* elf32-hppa.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elf64-ppc.c: Likewise.
* elfxx-aarch64.c: Likewise.
* elfxx-mips.c: Likewise.
* cpu-ns32k.c: Add missing fall through comments.
* elf-m10300.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-frv.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-microblaze.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-rx.c: Likewise.
* elf32-s390.c: Likewise.
* elf32-sh.c: Likewise.
* elf32-tic6x.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-s390.c: Likewise.
* elf64-x86-64.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* ieee.c: Likewise.
* oasys.c: Likewise.
* pdp11.c: Likewise.
* srec.c: Likewise.
* versados.c: Likewise.
opcodes/
* aarch64-opc.c: Spell fall through comments consistently.
* i386-dis.c: Likewise.
* aarch64-dis.c: Add missing fall through comments.
* aarch64-opc.c: Likewise.
* arc-dis.c: Likewise.
* arm-dis.c: Likewise.
* i386-dis.c: Likewise.
* m68k-dis.c: Likewise.
* mep-asm.c: Likewise.
* ns32k-dis.c: Likewise.
* sh-dis.c: Likewise.
* tic4x-dis.c: Likewise.
* tic6x-dis.c: Likewise.
* vax-dis.c: Likewise.
binutils/
* dlltool.c: Spell fall through comments consistently.
* objcopy.c: Likewise.
* readelf.c: Likewise.
* dwarf.c: Add missing fall through comments.
* elfcomm.c: Likewise.
* sysinfo.y: Likewise.
* readelf.c: Likewise. Also remove extraneous comments.
gas/
* app.c: Add missing fall through comments.
* dw2gencfi.c: Likewise.
* expr.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/obj-elf.c: Likewise.
* config/tc-i386.c: Likewise.
* depend.c: Spell fall through comments consistently.
* config/tc-arm.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z8k.c: Likewise.
gprof/
* gprof.c: Add missing fall through comments.
ld/
* lexsup.c: Spell fall through comments consistently and add
missing fall through comments.
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Well, not all are errors, but a little more substantive than just
fiddling with comments.
bfd/
* coffcode.h (coff_slurp_symbol_table): Revert accidental commit
made 2015-01-08.
* elf32-nds32.c (nds32_elf_grok_psinfo): Add missing break.
* reloc.c (bfd_default_reloc_type_lookup): Add missing breaks.
opcodes/
* arc-ext.c (create_map): Add missing break.
* msp430-decode.opc (encode_as): Likewise.
* msp430-decode.c: Regenerate.
binutils/
* coffdump.c (dump_coff_where): Add missing break.
* stabs.c (stab_xcoff_builtin_type): Likewise.
gas/
* config/tc-arc.c (find_opcode_match): Add missing break.
* config/tc-i960.c (get_cdisp): Likewise.
* config/tc-metag.c (parse_swap, md_apply_fix): Likewise.
* config/tc-mt.c (md_parse_option): Likewise.
* config/tc-nds32.c (nds32_apply_fix): Likewise.
* config/tc-hppa.c (pa_ip): Assert rather than testing last
condition of multiple if statements.
* config/tc-s390.c (s390_exp_compare): Return 0 on error.
* config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break
out of case rather than falling into next case. Formatting.
ld/
* plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning
by adding return.
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The assembler accepts dtpoff complex relocation expression like
identifier@dtpoff + const. However, it doesn't accept an expression such
as identifier@dtpoff@base + const. This patch solves this issue, and adds
a number of tests.
ld/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/tls-dtpoff.dd: New file.
* testsuite/ld-arc/tls-dtpoff.rd: Likewise.
* testsuite/ld-arc/tls-dtpoff.s: Likewise.
* testsuite/ld-arc/tls-relocs.ld: Likewise.
* testsuite/ld-arc/arc.exp: Add new tdpoff test.
gas/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/tls-relocs2.d: New file.
* testsuite/gas/arc/tls-relocs2.s: Likewise.
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
is used.
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|
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
|
|
gas/ChangeLog:
2016-07-05 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is
no longer needed.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
|
|
gas * config.in (TARGET_WITH_CPU): Undefine.
* configure.ac: Add --with-cpu support, and define in config.h.
* configure: Regenerate.
* config/tc-arc.c: Use TARGET_WITH_CPU to select default CPU.
* NEWS: Mention new configure option.
|
|
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
cfi_add_CFA_def_cfa to generate default CFA with offset
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
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|
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
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|
gas * config/tc-arc.c (check_cpu_feature, md_parse_option):
Add nps400 option and feature. Add check for nps400
feature. Refactor existing checks to check subclass before
feature enablement.
(md_show_usage): Document flags for NPS-400 and add some other
undocumented flags.
(cpu_type): Remove nps400 CPU type entry
(check_zol): Remove bfd_mach_arc_nps400 case.
(md_show_usage): Add help on -mcpu=nps400.
(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
set.
* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
-fpuda flags. Document -mcpu=nps400.
* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
expected flags to match ARC700 instead of NPS400.
* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
* testsuite/gas/arc/nps-400-2.d: Likewise.
* testsuite/gas/arc/nps-400-3.d: Likewise.
* testsuite/gas/arc/nps-400-4.d: Likewise.
* testsuite/gas/arc/nps-400-5.d: Likewise.
* testsuite/gas/arc/nps-400-6.d: Likewise.
* testsuite/gas/arc/nps-400-7.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
avoid clash with cbba instruction.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
case.
ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
* testsuite/ld-arc/nps-1b.d: Likewise.
include * opcode/arc.h: Add nps400 extension and instruction
subclass.
Remove ARC_OPCODE_NPS400
* elf/arc.h: Remove E_ARC_MACH_NPS400
opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length.
Use same method for determining instruction length on ARC700 and
NPS-400.
(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
with the NPS400 subclass.
* arc-opc.c: Likewise.
bfd * archures.c: Remove bfd_mach_arc_nps400.
* bfd-in2.h: Likewise.
* cpu-arc.c (arch_info_struct): Likewise.
* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
Likewise.
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etc * texi2pod.pl: Escape curly braces, whilst searching for keyword
strong.
gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets
that are not supported.
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
constant.
* config/tc-cr16.c (check_range): Likewise.
* config/tc-nios2.c (nios2_check_overflow): Likewise.
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|
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
|
|
gas/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_begin): Add XY registers.
(cpu_types): Code density is default off for ARC EM.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (neg): New instruction variant.
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|
gas/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (attributes_t): Renamed attribute class to
attr_class.
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
opcode/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* arc-dis.c (find_format, find_format, get_auxreg)
(print_insn_arc): Changed.
* arc-ext.h (INSERT_XOP): Likewise.
include/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* opcode/arc.h (struct arc_opcode): Renamed attribute class to
insn_class.
(struct arc_flag_class): Renamed attribute class to flag_class.
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|
By making the flgp field of struct arc_flags constant we can remove a
place where we cast away the const-ness of a variable. Also, given that
the value assigned to this field almost always comes from compile-time
constant data, having the field non-constant is probably a bad thing.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Remove casting away of
const.
* config/tc-arc.h (struct arc_flags): Make flgp field const.
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Some debug code has the wrong printf format specifier for some types
that are (ultimately) bfd_vma. Fixed by using BFD_VMA_FMT string. This
only becomes an issue when building the tc-arc.c file with -DDEBUG=1 to
build in the debug code.
gas/ChangeLog:
* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
appropriate.
(md_convert_frag): Likewise.
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|
The opcode array iterator mechanism can, in some situations, result in
reading memory outside of the opcode array. When using the
iterator-next mechanism to find the next possible arc_opcode, if we find
an opcode where the name field is NULL, or the name does not match, then
the cached opcode pointer is not set to NULL. The result is that
another call to iterator-next will again increment the opcode
pointer (which might now point outside the opcode array) and attempt to
access the name field of this undefined opcode.
Fixed in this commit by clearing the cached opcode pointer.
I've added a test case, which currently shows the bug, however, this
will only expose this bug while the opcode used (dsp_fp_cmp) is the last
opcode in the table.
gas/ChangeLog:
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
cached opcode to NULL when we reach a non-matching opcode.
* testsuite/gas/arc/asm-errors-2.d: New file.
* testsuite/gas/arc/asm-errors-2.err: New file.
* testsuite/gas/arc/asm-errors-2.s: New file.
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|
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.
This change checks that we don't access outside the limits of the
operand array.
gas/ChangeLog:
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
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|
Its a bit shorter and simpler than raw xmalloc.
gas/ChangeLog:
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* app.c (app_push): Use XNEW and related macros.
* as.c (parse_args): Likewise.
* cgen.c (make_right_shifted_expr): Likewise.
(gas_cgen_tc_gen_reloc): Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff.c (stack_init): Likewise.
(stack_push): Likewise.
(coff_obj_symbol_new_hook): Likewise.
(coff_obj_symbol_clone_hook): Likewise.
(add_lineno): Likewise.
(coff_frob_symbol): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(build_group_lists): Likewise.
* config/obj-evax.c (evax_symbol_new_hook): Likewise.
* config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise.
* config/tc-aarch64.c (insert_reg_alias): Likewise.
(find_or_make_literal_pool): Likewise.
(add_to_lit_pool): Likewise.
(fill_instruction_hash_table): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(emit_jsrjmp): Likewise.
(s_alpha_ent): Likewise.
(s_alpha_end): Likewise.
(s_alpha_linkage): Likewise.
(md_begin): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (arc_insert_opcode): Likewise.
(arc_extcorereg): Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c (preprocess_reglist): Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-frv.c (frv_insert_vliw_insn): Likewise.
(frv_tomcat_shuffle): Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-i370.c (i370_macro): Likewise.
* config/tc-i386.c (lex_got): Likewise.
(md_parse_option): Likewise.
* config/tc-ia64.c (alloc_record): Likewise.
(set_imask): Likewise.
(save_prologue_count): Likewise.
(dot_proc): Likewise.
(dot_endp): Likewise.
(ia64_frob_label): Likewise.
(add_qp_imply): Likewise.
(add_qp_mutex): Likewise.
(mark_resource): Likewise.
(dot_alias): Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c (m68k_frob_label): Likewise.
(s_save): Likewise.
(mri_control_label): Likewise.
(push_mri_control): Likewise.
(build_mri_control_operand): Likewise.
(s_mri_else): Likewise.
(s_mri_break): Likewise.
(s_mri_next): Likewise.
(s_mri_for): Likewise.
(s_mri_endw): Likewise.
* config/tc-metag.c (create_mnemonic_htab): Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mmix.c (s_loc): Likewise.
* config/tc-nds32.c (nds32_relax_hint): Likewise.
* config/tc-nios2.c (nios2_insn_reloc_new): Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c (rx_include): Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c (shmedia_frob_section_type): Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-spu.c: Likewise.
* config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise.
(tic6x_start_unwind_section): Likewise.
* config/tc-tilegx.c: Likewise.
* config/tc-tilepro.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise.
(new_resource_table): Likewise.
(resize_resource_table): Likewise.
(xtensa_create_trampoline_frag): Likewise.
(xtensa_maybe_create_literal_pool_frag): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c (append_transition): Likewise.
(append_condition): Likewise.
(append_value_condition): Likewise.
(append_constant_value_condition): Likewise.
(append_literal_op): Likewise.
(append_label_op): Likewise.
(append_constant_op): Likewise.
(append_field_op): Likewise.
(append_user_fn_field_op): Likewise.
(enter_opname_n): Likewise.
(enter_opname): Likewise.
(split_string): Likewise.
(parse_insn_templ): Likewise.
(clone_req_or_option_list): Likewise.
(clone_req_option_list): Likewise.
(parse_option_cond): Likewise.
(parse_insn_pattern): Likewise.
(parse_insn_repl): Likewise.
(build_transition): Likewise.
(build_transition_table): Likewise.
* dw2gencfi.c (alloc_fde_entry): Likewise.
(alloc_cfi_insn_data): Likewise.
(cfi_add_CFA_remember_state): Likewise.
(dot_cfi_escape): Likewise.
(dot_cfi_fde_data): Likewise.
(select_cie_for_fde): Likewise.
* dwarf2dbg.c (dwarf2_directive_loc): Likewise.
* ecoff.c (ecoff_add_bytes): Likewise.
(ecoff_build_debug): Likewise.
* input-scrub.c (input_scrub_push): Likewise.
(input_scrub_begin): Likewise.
(input_scrub_next_buffer): Likewise.
* itbl-ops.c (append_insns_as_macros): Likewise.
(alloc_entry): Likewise.
(alloc_field): Likewise.
* listing.c (listing_newline): Likewise.
(listing_listing): Likewise.
* macro.c (get_any_string): Likewise.
(delete_macro): Likewise.
* stabs.c (generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
* subsegs.c (subseg_change): Likewise.
(subseg_get): Likewise.
* symbols.c (define_dollar_label): Likewise.
(symbol_relc_make_sym): Likewise.
* write.c (write_relocs): Likewise.
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gas/ChangeLog:
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/obj-coff.c (obj_coff_def): Simplify string copying.
(weak_name2altname): Likewise.
(weak_uniquify): Likewise.
(obj_coff_section): Likewise.
(obj_coff_init_stab_section): Likewise.
* config/obj-elf.c (obj_elf_section_name): Likewise.
(obj_elf_init_stab_section): Likewise.
* config/obj-evax.c (evax_shorten_name): Likewise.
* config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise.
* config/tc-aarch64.c (create_register_alias): Likewise.
* config/tc-alpha.c (load_expression): Likewise.
(s_alpha_file): Likewise.
(s_alpha_section_name): Likewise.
(tc_gen_reloc): Likewise.
* config/tc-arc.c (md_assemble): Likewise.
* config/tc-arm.c (create_neon_reg_alias): Likewise.
(start_unwind_section): Likewise.
* config/tc-hppa.c (pa_build_unwind_subspace): Likewise.
(hppa_elf_mark_end_of_function): Likewise.
* config/tc-nios2.c (nios2_modify_arg): Likewise.
(nios2_negate_arg): Likewise.
* config/tc-rx.c (rx_section): Likewise.
* config/tc-sh64.c (sh64_consume_datalabel): Likewise.
* config/tc-tic30.c (tic30_find_parallel_insn): Likewise.
* config/tc-tic54x.c (tic54x_include): Likewise.
(tic54x_macro_info): Likewise.
(subsym_get_arg): Likewise.
(subsym_substitute): Likewise.
(tic54x_start_line_hook): Likewise.
* config/tc-xtensa.c (xtensa_literal_prefix): Likewise.
(xg_reverse_shift_count): Likewise.
* config/xtensa-relax.c (enter_opname_n): Likewise.
(split_string): Likewise.
* dwarf2dbg.c (get_filenum): Likewise.
(process_entries): Likewise.
* expr.c (operand): Likewise.
* itbl-ops.c (alloc_entry): Likewise.
* listing.c (listing_message): Likewise.
(listing_title): Likewise.
* macro.c (check_macro): Likewise.
* stabs.c (s_xstab): Likewise.
* symbols.c (symbol_relc_make_expr): Likewise.
* write.c (compress_debug): Likewise.
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gas/
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
(arc_extinsn): Handle new introduced syntax.
* testsuite/gas/arc/textinsn1op.d: New file.
* testsuite/gas/arc/textinsn1op.s: Likewise.
* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.
opcodes/
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
(arcExtMap_genOpcode): Likewise.
* arc-opc.c (arg_32bit_rc): Define new variable.
(arg_32bit_u6): Likewise.
(arg_32bit_limm): Likewise.
include/
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_SYNTAX_1OP): Declare
(ARC_SYNTAX_NOP): Likewsie.
(ARC_OP1_MUST_BE_IMM): Update defined value.
(ARC_OP1_IMM_IMPLIED): Likewise.
(arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
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This reverts commit 9a452709fe126ea6da23a53426362e4435d2dc06.
This change was committed as obvious, but it has been rightly been
pointed out to me that this change is not obvious, and as such I am
reverting it.
gas/ChangeLog:
Revert prevous change.
* config/tc-arc.c (arc_option): Make .cpu directive
case-sensitive again.
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gas/ChangeLog:
* config/tc-arc.c (arc_option): Make .cpu directive
case-insensitive.
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gas/ChangeLog:
* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
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gas/
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (mach_type_specified_p): Change type to
bfd_boolean.
(arc_option): Set private flags when parsing cpu pseudo-op.
(md_parse_option): Set mach_type_specified_p to TRUE.
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gas/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
(arc_flags): Delete code, add flgp.
include/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (flag_class_t): Update.
(ARC_OPCODE_NONE): Define.
(ARC_OPCODE_ARCALL): Likewise.
(ARC_OPCODE_ARCFPX): Likewise.
(ARC_REGISTER_READONLY): Likewise.
(ARC_REGISTER_WRITEONLY): Likewise.
(ARC_REGISTER_NOSHORT_CUT): Likewise.
(arc_aux_reg): Add cpu.
opcodes/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Check for extension flags.
(print_flags): New function.
(print_insn_arc): Update for .extCondCode, .extCoreRegister and
.extAuxRegister.
* arc-ext.c (arcExtMap_coreRegName): Use
LAST_EXTENSION_CORE_REGISTER.
(arcExtMap_coreReadWrite): Likewise.
(dump_ARC_extmap): Update printing.
* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
(arc_aux_regs): Add cpu field.
* arc-regs.h: Add cpu field, lower case name aux registers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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gas/
2016-03-31 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
(arc_adjust_symtab): New function.
* config/tc-arc.h (ARC_FLAG_AUX): Define.
(obj_adjust_symtab): Likewise.
* testsuite/gas/arc/taux.d: New file.
* testsuite/gas/arc/taux.s: Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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This commit completes support for having multiple instructions with the
same mnemonic in non-contiguous blocks within the arc_opcodes table.
The commit adds an iterator mechanism for the arc_opcode_hash_entry
structure, which is then used in find_opcode_match to consider all
arc_opcode entries with the same mnemonic, even when these instructions
are stored in non-contiguous blocks.
I extend the comment on the arc_opcodes table to discuss how entries
within the table are organised, and to mention how instructions can be
split into multiple groups if needed, but that the table is still
searched in table order.
There should be no user visible changes after this commit.
gas/ChangeLog:
* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
structure.
(arc_opcode_hash_entry_iterator_init): New function.
(arc_opcode_hash_entry_iterator_next): New function.
(find_opcode_match): Iterate over all arc_opcode entries
referenced by the arc_opcode_hash_entry passed in as a parameter.
opcodes/ChangeLog:
* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
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Building on earlier commits, this commit moves along support for having
multiple arc_opcode entries in the arc_opcodes table that have the same
mnemonic (name) field, but are not stored in a contiguous block in the
table.
In this commit we support looking up the arc_opcode_hash_entry from the
hash table, and passing this along to the find_opcode_match function,
which then finds the specific arc_opcode that we're assembling. We
still don't actually support the multiple chains of arc_opcode entries
in this commit, but the limitation is now isolated to the
find_opcode_match function.
There is no user visible change after this commit.
gas/ChangeLog:
* config/tc-arc.c (arc_find_opcode): Now returns
arc_opcode_hash_entry pointer.
(find_opcode_match): Update argument type, extract arc_opcode from
incoming arc_opcode_hash_entry.
(find_special_case_pseudo): Update return type.
(find_special_case_flag): Update return type.
(find_special_case): Update return type.
(assemble_tokens): Lookup arc_opcode_hash_entry based on
instruction mnemonic, then use find_opcode_match to identify
specific arc_opcode.
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The arc assembler builds a hash table to hold references to arc_opcode
entries in the arc_opcodes table. This hash assumes that each mnemonic
will always appear in a contiguous blocks within the arc_opcodes table;
all ADD instruction will be together, all AND instructions will likewise
be together and so on.
The problem with this is that as different variations of arc are added,
then it is often more convenient to split instructions apart, so all the
base ADD instructions are together, but, variants of ADD specific to one
variation of arc are grouped with other instructions specific to that
arc variant. The current data structures don't support splitting the
instructions in this way.
This commit is a first step towards addressing this limitation. In this
commit the hash table that currently holds arc_opcode pointers directly,
instead holds a pointer to a new, intermediate, data structure. This
new data structure holds the pointer to the arc_opcode. In this way, we
can, in the future support having the intermediate structure hold
multiple pointers to different arc_opcode groups.
There should be no visible functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
(arc_find_opcode): New function.
(find_special_case_pseudo): Use arc_find_opcode.
(find_special_case_flag): Likewise.
(assemble_tokens): Likewise.
(md_begin): Build hash using struct arc_opcode_hash_entry.
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gas/
2016-04-07 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_option): Prepare string for automatic
translation.
(declare_register): Likewise.
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An upcoming commit will add a new arc instruction flag that uses
characters that have never appeared in an arc instruction flag before.
Currently the assembler is very conservative about which characters can
or cannot appear in an instruction flag.
This commit relaxes these constraints a little. After this commit all
alpha-numeric characters are now allowed into instruction flags. This
complete set is not required for the upcoming change, however, having
this slightly larger set does not impact the assemblers ability to
correctly parse input, but does make it easier to add new flag to the
instruction table.
gas/ChangeLog:
* config/tc-arc.c (tokenize_flags): Allow greater range of
characters into flag names.
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The preprocess_operands function changes the incoming list of assembler
tokens based on the assumption that the first arc_operand found will be
the same instruction class as all of the arc_operands for the same
mnemonic.
Though this assumption is probably fine, removing this assumption, and
pushing the token change down into assemble_tokens makes the code no
more complex, and might even be easier to follow.
There should be no user visible changes after this commit.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
new de_fault label.
(preprocess_operands): Delete.
(assemble_tokens): Remove call to preprocess_operands.
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