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path: root/gas/config/tc-aarch64.c
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2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-6/+46
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+20
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li1-0/+84
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-2/+8
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-3/+3
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li1-1/+1
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+3
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich1-5/+6
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+8
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+6
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-1/+7
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar1-0/+3
2017-09-01Enable support for the AArch64 dot-prod instruction in the Cortex A55 and A75...Tamar Christina1-2/+2
2017-08-15[Patch AArch64] Turn lr, fp, ip0 and ip1 into proper aliasesRamana Radhakrishnan1-5/+6
2017-07-24Stop the generation of mapping symbols in the debug sections of ARM and AArch...Nick Clifton1-0/+5
2017-07-13Add RDMA support for falkot/qdf24xx.Jim Wilson1-2/+4
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-3/+7
2017-06-21Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 archite...James Greenhalgh1-0/+6
2017-06-07Add support for AArch64 system register names IP0, IP1, FP and LR.Michael Collison1-0/+5
2017-05-22[AArch64, gas] Support ILP32 triplet aarch64*-linux-gnu_ilp32Jiong Wang1-3/+27
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-5/+5
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton1-6/+6
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-3/+10
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+3
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-15/+15
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+2
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-15/+15
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani1-1/+1
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+3
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+21
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+2
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy1-2/+2
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar1-0/+3
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-1/+1
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-4/+4
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-25/+33
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+16
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-3/+38
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+27
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-15/+59
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-23/+222
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-1/+41
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+64
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-4/+52
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-31/+130
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+5
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