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path: root/gas/config/tc-aarch64.c
AgeCommit message (Expand)AuthorFilesLines
2019-09-19bfd_section_* macrosAlan Modra1-1/+1
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks1-1/+2
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang1-0/+22
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect structural...Barnaby Wilks1-0/+9
2019-05-24aarch64: override default elf .set handling in gasSzabolcs Nagy1-0/+32
2019-05-24aarch64: handle .variant_pcs directive in gasSzabolcs Nagy1-0/+23
2019-05-14A series of fixes to addres problems detected by compiling the assembler with...Nick Clifton1-3/+0
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-4/+48
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+13
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+3
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+2
2019-04-10te-cloudabi.hAlan Modra1-5/+8
2019-02-22[AArch64][gas] Add support for Neoverse E1Kyrylo Tkachov1-0/+5
2019-02-22[AArch64][gas] Add support for Neoverse N1Kyrylo Tkachov1-0/+5
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das1-0/+2
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-16/+3
2019-01-08[AArch64][gas] Add -mcpu support for Arm AresKyrylo Tkachov1-0/+5
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-05[aarch64] Add support for pointer authentication B keySam Tebbs1-0/+9
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-3/+17
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-0/+6
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+2
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das1-0/+2
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-0/+52
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+17
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+1
2018-10-03AArch64: Close sequences at the end of sectionsTamar Christina1-0/+18
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-2/+4
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-8/+22
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina1-1/+1
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan1-0/+16
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+2
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka011-0/+3
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina1-0/+2
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports A...Sameera Deshpande1-1/+1
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-51/+81
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-10/+19
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina1-21/+4
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-6/+46
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+20
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li1-0/+84