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2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus1-0/+2
This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.
2021-02-11Re: Remove arm-symbianelfAlan Modra1-0/+2
gas/ * NEWS: Mention arm-symbianelf removal. ld/ * NEWS: Mention arm-symbianelf removal.
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-6/+2
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-09Add Changelog entries and NEWS entries for 2.36 branchNick Clifton1-0/+2
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus1-1/+2
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-11-18Support SHF_GNU_RETAIN ELF section flagJozef Lawrynowicz1-0/+5
The SHF_GNU_RETAIN section flag is an extension to the GNU ELF OSABI. It is defined as follows: ========================================================= Section Attribute Flags +-------------------------------------+ | Name | Value | +-------------------------------------+ | SHF_GNU_RETAIN | 0x200000 (1 << 21) | +-------------------------------------+ SHF_GNU_RETAIN The link editor should not garbage collect the section. ========================================================= The .section directive accepts the "R" flag, which indicates SHF_GNU_RETAIN should be applied to the section. There is not a direct mapping of SHF_GNU_RETAIN to the BFD section flag SEC_KEEP. Keeping these flags distinct allows SHF_GNU_RETAIN sections to be explicitly removed by placing them in /DISCARD/. bfd/ChangeLog: * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_retain. (struct elf_obj_tdata): Increase has_gnu_osabi to 4 bits. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_retain for SHF_GNU_RETAIN. (_bfd_elf_final_write_processing): Report if SHF_GNU_RETAIN is not supported by the OSABI. Adjust error messages. * elflink.c (elf_link_input_bfd): Copy enabled has_gnu_osabi bits from input BFD to output BFD. (bfd_elf_gc_sections): gc_mark the section if SHF_GNU_RETAIN is set. binutils/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * readelf.c (get_elf_section_flags): Handle SHF_GNU_RETAIN. Recognize SHF_GNU_RETAIN and SHF_GNU_MBIND only for supported OSABIs. * testsuite/binutils-all/readelf.exp: Run new tests. Don't run run_dump_test when there isn't an assembler available. * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Adjust comment. * testsuite/binutils-all/readelf-maskos-1a.d: New test. * testsuite/binutils-all/readelf-maskos-1b.d: New test. * testsuite/binutils-all/readelf-maskos.s: New test. * testsuite/binutils-all/retain1.s: New test. * testsuite/binutils-all/retain1a.d: New test. * testsuite/binutils-all/retain1b.d: New test. gas/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit between section declarations. (obj_elf_parse_section_letters): Handle 'R' flag. Handle numeric flag values within the SHF_MASKOS range. (obj_elf_section): Validate SHF_GNU_RETAIN usage. * doc/as.texi: Document 'R' flag to .section directive. * testsuite/gas/elf/elf.exp: Run new tests. * testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section22.d: New test. * testsuite/gas/elf/section22.s: New test. * testsuite/gas/elf/section23.s: New test. * testsuite/gas/elf/section23a.d: New test. * testsuite/gas/elf/section23b.d: New test. * testsuite/gas/elf/section23b.err: New test. * testsuite/gas/elf/section24.l: New test. * testsuite/gas/elf/section24.s: New test. * testsuite/gas/elf/section24a.d: New test. * testsuite/gas/elf/section24b.d: New test. include/ChangeLog: * elf/common.h (SHF_GNU_RETAIN): Define. ld/ChangeLog: * NEWS: Announce support for SHF_GNU_RETAIN. * ld.texi (garbage collection): Document SHF_GNU_RETAIN. (Output Section Discarding): Likewise. * testsuite/ld-elf/elf.exp: Run new tests. * testsuite/ld-elf/retain1.s: New test. * testsuite/ld-elf/retain1a.d: New test. * testsuite/ld-elf/retain1b.d: New test. * testsuite/ld-elf/retain2.d: New test. * testsuite/ld-elf/retain2.ld: New test. * testsuite/ld-elf/retain2.map: New test. * testsuite/ld-elf/retain3.d: New test. * testsuite/ld-elf/retain3.s: New test. * testsuite/ld-elf/retain4.d: New test. * testsuite/ld-elf/retain4.s: New test. * testsuite/ld-elf/retain5.d: New test. * testsuite/ld-elf/retain5.map: New test. * testsuite/ld-elf/retain5lib.s: New test. * testsuite/ld-elf/retain5main.s: New test. * testsuite/ld-elf/retain6a.d: New test. * testsuite/ld-elf/retain6b.d: New test. * testsuite/ld-elf/retain6lib.s: New test. * testsuite/ld-elf/retain6main.s: New test.
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus1-0/+3
New -march option +pauth enables PAuth vel PAC (Pointer Authentication) feature.
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-1/+3
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+3
Armv8.7 architecture introduces the "accelerator extension", aka load/store of 64 bytes. New atomic load/store instructions are: LD64B, ST64B, ST64BV and ST64BV0. This patch adds: + New feature +ls64 to -march command line. + New atomic load/store instructions associated with above feature. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-1/+1
This patch adds new to Armv8.7 WFIT instruction which take one operand: WFIT <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 570 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn. * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn. opcodes/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+3
This patch adds: + New feature +csre to -march command line. + New instruction CSR PDEC associated with CSRE feature. Please note that CSRE system registers were already upstreamed. This patch should finalize CSRE feature implementation. CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. Although this instruction has operand (PDEC) it's instruction's only operand. PDEC forces instruction field Rt to be set to 0b1111. This results in fixed opcode of the instruction. gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * config/tc-aarch64.c (parse_csr_operand): New operand parser. (parse_operands): Call to CSR operand parser. * testsuite/gas/aarch64/csre_csr-invalid.d: New test. * testsuite/gas/aarch64/csre_csr-invalid.l: New test. * testsuite/gas/aarch64/csre_csr-invalid.s: New test. * testsuite/gas/aarch64/csre_csr.d: New test. * testsuite/gas/aarch64/csre_csr.s: New test. include/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature. (enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. * aarch64-tbl.h (CSRE): New CSRE feature handler. (_CSRE_INSN): New CSRE instruction type. (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-1/+2
This patch adds new to Armv8.7 WFET instruction which take one operand: WFET <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFET (Wait For Event with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 565 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: New test. * testsuite/gas/aarch64/system-5.s: New test. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding and operand description. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+2
This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-1/+1
This patch adds support for AArch64 -march=armv8.7-a command line option in GAS. Please note that this change ONLY extends -march= command line interface with a new "armv8.7-a" option. Architectural changes like new instructions will be added in following patches. gas/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (armv8.7-a): New arch. * doc/c-aarch64.texi (-march=armv8.7-a): Update docs. include/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask. (AARCH64_ARCH_V8_7): New arch feature set. opcodes/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (ARMV8_7): New macro.
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-2/+3
This patch introduces BRBE (Branch Record Buffer Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/brbe-invalid.d: New test. * testsuite/gas/aarch64/brbe-invalid.l: New test. * testsuite/gas/aarch64/brbe-invalid.s: New test. * testsuite/gas/aarch64/brbe.d: New test. * testsuite/gas/aarch64/brbe.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add BRBE system registers.
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-1/+2
This patch introduces CSRE (Call Stack Recorder Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. This instruction will be added in a following, separate patch. This change only adds CSRE system registers. gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/csre-invalid.d: New test. * testsuite/gas/aarch64/csre-invalid.l: New test. * testsuite/gas/aarch64/csre-invalid.s: New test. * testsuite/gas/aarch64/csre.d: New test. * testsuite/gas/aarch64/csre.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: New CSRE system registers defined.
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+2
Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded with the EVEX prefix. The pseudo {vex} prefix can be used to encode mnemonics of Intel VNNI instructions with the VEX prefix. gas/ * NEWS: Add Intel AVX VNNI. * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. (cpu_flags_match): Support CpuVEX_PREFIX. * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to encode Intel VNNI instructions with VEX prefix. * testsuite/gas/i386/avx-vnni.d: New file. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F3850): New. (PREFIX_VEX_0F3851): Likewise. (PREFIX_VEX_0F3852): Likewise. (PREFIX_VEX_0F3853): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3852_P_2): Likewise. (VEX_W_0F3853_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. (putop): Add support for "XV" to print "{vex3}" pseudo prefix. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and CPU_ANY_AVX_VNNI_FLAGS. (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. * i386-opc.h (CpuAVX_VNNI): New. (CpuVEX_PREFIX): Likewise. (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. * i386-opc.tbl: Add Intel AVX VNNI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+2
gas/ * NEWS: Add Intel HRESET. * config/tc-i386.c (cpu_arch): Add .hreset. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .hreset, nohreset. * testsuite/gas/i386/i386.exp: Run HRESET tests. * testsuite/gas/i386/hreset.d: New file. * testsuite/gas/i386/x86-64-hreset.d: Likewise. * testsuite/gas/i386/hreset.s: Likewise. opcodes/ * i386-dis.c (PREFIX_0F3A0F): New. (MOD_0F3A0F_PREFIX_1): Likewise. (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. (prefix_table): Add PREFIX_0F3A0F. (mod_table): Add MOD_0F3A0F_PREFIX_1. (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, CPU_ANY_HRESET_FLAGS. (cpu_flags): Add CpuHRESET. (output_i386_opcode): Allow 4 byte base_opcode. * i386-opc.h (enum): Add CpuHRESET. (i386_cpu_flags): Add cpuhreset. * i386-opc.tbl: Add Intel HRESET instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel UINTRLili Cui1-0/+2
gas/ * NEWS: Add Intel UINTR. * config/tc-i386.c (cpu_arch): Add .uintr. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .uintr and nouintr. * testsuite/gas/i386/i386.exp: Run UINTR tests. * testsuite/gas/i386/x86-64-uintr.d: Likewise. * testsuite/gas/i386/x86-64-uintr.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_3_0F01_REG_5_RM_4, PREFIX_MOD_3_0F01_REG_5_RM_5, PREFIX_MOD_3_0F01_REG_5_RM_6, PREFIX_MOD_3_0F01_REG_5_RM_7, X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1. (prefix_table): New instructions (see prefixes above). (rm_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, CPU_ANY_UINTR_FLAGS. (cpu_flags): Add CpuUINTR. * i386-opc.h (enum): Add CpuUINTR. (i386_cpu_flags): Add cpuuintr. * i386-opc.tbl: Add UINTR insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-05i386: Allow non-absolute segment values for lcall/ljmpT.K. Chia1-0/+3
Allow an unresolved or non-absolute symbol as the segment operand of an immediate far jump (`ljmp SEG, OFF') or far call (`lcall SEG, OFF'). gas/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * NEWS: Updated for i386 lcall and ljmp change. * config/tc-i386.c (output_interseg_jump): Allow non-absolute segment operand for immediate lcall and ljmp. * testsuite/gas/i386/jump.d, * testsuite/gas/i386/jump.s, * testsuite/gas/i386/jump16.d, * testsuite/gas/i386/jump16.e, * testsuite/gas/i386/jump16.s: Add tests for non-absolute segment operand for immediate ljmp. ld/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * testsuite/ld-i386/ljmp.s, * testsuite/ld-i386/ljmp1.d, * testsuite/ld-i386/ljmp1.s, * testsuite/ld-i386/ljmp2.d, * testsuite/ld-i386/ljmp2.s, * testsuite/ld-x86-64/ljmp1.d, * testsuite/ld-x86-64/ljmp2.d: New testcases. * testsuite/ld-i386/i386.exp, * testsuite/ld-x86-64/x86-64.exp: Run them.
2020-10-05GAS: Update the .section directive so that a numeric section index can be ↵Nick Clifton1-15/+6
provided when the "o" flag is used. PR 26253 gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for the "o" section flag. Interpret it as a section index. Allow an index of zero. * doc/as.texi: Document the new behaviour. * NEWS: Mention the new feature. Tidy entries. * testsuite/gas/elf/sh-link-zero.s: New test. * testsuite/gas/elf/sh-link-zero.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/section21.l: Updated expected assembler output. bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an sh_link value of zero when the SLF_LINK_ORDER flag is set. (assign_section_numbers): Likewise.
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
bfd/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * cpu-arm.c: Add cortex-a78 and cortex-a78ae. gas/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. * doc/c-arm.texi: Update docs. * NEWS: Update news. * testsuite/gas/arm/cpu-cortex-a78.d: New test. * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+2
* config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. * doc/c-aarch64.texi: Update docs. * NEWS: Update news.
2020-09-30NEWS: Mention recent Arm CPU supportAlex Coplan1-0/+5
Mentions Armv8-R AArch64, Cortex-R82, Neoverse V1, and Neoverse N2. gas/ChangeLog: 2020-09-30 Alex Coplan <alex.coplan@arm.com> * NEWS: Mention recent Arm processor support.
2020-09-29Add a note about recent changes to the AArch64 assembler: TRBE, ETE and ↵Przemyslaw Wirkus1-0/+11
ETMv4 system registers and Cortex-X1 enablement. gas * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+1
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+2
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op ↵Nick Clifton1-0/+4
instructions in an architeture neutral manner. * read.c (s_nop): New function. Handles the .nop directive. (potable): Add entry for "nop". (s_nops): Code tidy. * read.h (s_nop): Add prototype. * config/tc-bpf.h (md_single_noop_insn): Define. * config/tc-mmix.h (md_single_noop_insn): Define. * config/tc-or1k.h (md_single_noop_insn): Define. * config/tc-s12z.c (md_assemble): Preserve the input line pointer, rather than corrupting it. * write.c (relax_segment): Update error message regarding non-absolute values passed to .fill and .nops. * NEWS: Mention the new directive. * doc/as.texi: Document the new directive. * doc/internals.texi: Document the new internal macros used to implement the new directive. * testsuite/gas/all/nop.s: New test. * testsuite/gas/all/nop.d: New test control file. * testsuite/gas/all/gas.exp: Run the new test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test control file. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/space1.l: Adjust expected output.
2020-08-20Remove --reduce-memory-overheads and --hash-size arguments.Martin Liska1-0/+3
* NEWS: Mention --reduce-memory-overheads and --hash-size arguments options. * as.c: Remove the options from help. * doc/as.texi: Remove options. * doc/internals.texi: Remove hash from documentation. * hash.c (struct hash_entry): Remove. (struct hash_control): Likewise. (set_gas_hash_table_size): Likewise. (hash_new_sized): Likewise. (hash_new): Likewise. (hash_die): Likewise. (hash_lookup): Likewise. (hash_insert): Likewise. (hash_jam): Likewise. (hash_replace): Likewise. (hash_find): Likewise. (hash_find_n): Likewise. (hash_delete): Likewise. (hash_traverse): Likewise. (hash_print_statistics): Likewise. (TABLES): Likewise. (STATBUFSIZE): Likewise. (main): Likewise. (what): Likewise. (destroy): Likewise. (applicatee): Likewise. (whattable): Likewise. * hash.h (struct hash_control): Likewise. (set_gas_hash_table_size): Likewise. (hash_new): Likewise. (hash_new_sized): Likewise. (hash_die): Likewise. (hash_insert): Likewise. (hash_jam): Likewise. (hash_replace): Likewise. (hash_find): Likewise. (hash_find_n): Likewise. (hash_delete): Likewise. (hash_traverse): Likewise. (hash_print_statistics): Likewise.
2020-08-04gas/NEWS: Mention {disp16} pseudo prefixH.J. Lu1-0/+2
* NEWS: Mention {disp16} pseudo prefix.
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+2
gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-07-09Linux/x86: Configure gas with --enable-x86-used-note by defaultH.J. Lu1-0/+2
* configure.ac: Configure with --enable-x86-used-note by default for Linux/x86. * configure: Regenerated.
2020-07-04Add markers for binutils 2.35 branchNick Clifton1-0/+2
2020-06-30Remove x86 NaCl target supportH.J. Lu1-0/+2
NaCl has been deprecated: https://developer.chrome.com/native-client/migration and NaCl will completely disappear in 2021: https://lists.llvm.org/pipermail/llvm-dev/2020-April/141107.html Remove x86 NaCl target support from bfd, binutils, gas and ld. bfd/ * archures.c (bfd_mach_i386_nacl): Removed. (bfd_mach_i386_i386_nacl): Likewise. (bfd_mach_x86_64_nacl): Likewise. (bfd_mach_x64_32_nacl): Likewise. * config.bfd: Remove *-*-nacl* targets. * configure.ac: Remove x86 NaCl target vectors. * cpu-i386.c (bfd_arch_i386_onebyte_nop_fill): Removed. (bfd_x64_32_nacl_arch): Likewise. (bfd_x86_64_nacl_arch): Likewise. (bfd_i386_nacl_arch): Likewise. (bfd_x64_32_arch_intel_syntax): Updated. * elf32-i386.c: Don't include "elf-nacl.h". (elf_i386_nacl_plt): Removed. (elf_i386_nacl_plt0_entry): Likewise. (elf_i386_nacl_plt_entry): Likewise. (elf_i386_nacl_pic_plt0_entry): Likewise. (elf_i386_nacl_pic_plt_entry): Likewise. (elf_i386_nacl_eh_frame_plt): Likewise. (elf_i386_nacl_plt): Likewise. (elf32_i386_nacl_elf_object_p): Likewise. (elf_i386_get_synthetic_symtab): Updated. (elf_i386_link_setup_gnu_properties): Likewise. * elf64-x86-64.c: Don't include "elf-nacl.h". (elf_x86_64_nacl_plt): Removed. (elf64_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_nacl_plt0_entry): Likewise. (elf_x86_64_nacl_plt_entry): Likewise. (elf_x86_64_nacl_eh_frame_plt): Likewise. (elf_x86_64_nacl_plt): Likewise. (elf32_x86_64_nacl_elf_object_p): Likewise. (elf_x86_64_get_synthetic_symtab): Updated. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Likewise. * targets.c: Remove x86 NaCl target vectors. * bfd-in2.h: Regenerated. * configure: Likewise. binutils/ * NEWS: Mention x86 NaCl target support removal. * dwarf.c (init_dwarf_regnames_by_bfd_arch_and_mach): Remove x86 NaCl target support. * testsuite/binutils-all/elfedit-1.d: Likewise. * testsuite/binutils-all/i386/i386.exp: Likewise. * testsuite/binutils-all/x86-64/objects.exp: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/x86-64.exp: Likewise. gas/ * NEWS: Mention x86 NaCl target support removal. * config/tc-i386.c: Remove x86 NaCl target support. * config/tc-i386.h: Likewise. * configure.tgt: Likewise. * testsuite/gas/i386/i386.exp: Likewise. * testsuite/gas/i386/iamcu-1.d: Likewise. * testsuite/gas/i386/iamcu-2.d: Likewise. * testsuite/gas/i386/iamcu-3.d: Likewise. * testsuite/gas/i386/iamcu-4.d: Likewise. * testsuite/gas/i386/iamcu-5.d: Likewise. * testsuite/gas/i386/k1om.d: Likewise. * testsuite/gas/i386/l1om.d: Likewise. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_nacl.c, eelf32_x86_64_nacl.c, eelf_x86_64_nacl.c. Remove x86 NaCl dep files. * NEWS: Mention x86 NaCl target support removal. * configure.tgt: Remove x86 NaCl target support. * testsuite/ld-elf/binutils.exp: Likewise. * testsuite/ld-elf/elf.exp: Likewise. * testsuite/ld-elfvers/vers.exp: Likewise. * testsuite/ld-i386/align-branch-1.d: Likewise. * testsuite/ld-i386/export-class.exp: Likewise. * testsuite/ld-i386/i386.exp: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/pie1.d: Likewise. * testsuite/ld-i386/pr12570a.d: Likewise. * testsuite/ld-i386/pr12570b.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1l.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-i386/pr19636-2d.d: Likewise. * testsuite/ld-i386/pr19636-2e.d: Likewise. * testsuite/ld-i386/pr20244-1a.d: Likewise. * testsuite/ld-i386/pr20244-1b.d: Likewise. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-4a.d: Likewise. * testsuite/ld-i386/pr20244-4b.d: Likewise. * testsuite/ld-i386/pr21884.d: Likewise. * testsuite/ld-ifunc/binutils.exp: Likewise. * testsuite/ld-ifunc/ifunc-10-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-10-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-11-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-11-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-12-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-12-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-13-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14c-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14d-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14e-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-14f-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-15-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-16-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-17b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-19b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-20-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-20-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-21-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-6b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-7b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-8-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-8-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-9-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-9-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-i386-now.d: Likewise. * testsuite/ld-ifunc/pr17154-i386.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-x86-64/align-branch-1.d: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Likewise. * testsuite/ld-x86-64/line.exp: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-x86-64/load1c.d: Likewise. * testsuite/ld-x86-64/load1d.d: Likewise. * testsuite/ld-x86-64/pie3.d: Likewise. * testsuite/ld-x86-64/pr18160.d: Likewise. * testsuite/ld-x86-64/pr19013-x32.d: Likewise. * testsuite/ld-x86-64/pr19013.d: Likewise. * testsuite/ld-x86-64/pr19636-2d.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/pr20253-1b.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1f.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr20253-1j.d: Likewise. * testsuite/ld-x86-64/pr20253-1l.d: Likewise. * testsuite/ld-x86-64/pr21884.d: Likewise. * testsuite/ld-x86-64/pr22393-3a.rd: Likewise. * testsuite/ld-x86-64/pr22393-3b.rd: Likewise. * testsuite/ld-x86-64/tlsgd10.dd: Likewise. * testsuite/ld-x86-64/tlsgd5.dd: Likewise. * testsuite/ld-x86-64/tlsgd8.dd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Likewise. * emulparams/elf32_x86_64_nacl.sh: Removed. * emulparams/elf_i386_nacl.sh: Likewise. * emulparams/elf_x86_64_nacl.sh: Likewise. * testsuite/ld-i386/emit-relocs-nacl.rd: Likewise. * testsuite/ld-i386/load1-nacl.d: Likewise. * testsuite/ld-i386/pie1-nacl.d: Likewise. * testsuite/ld-i386/plt-nacl.pd: Likewise. * testsuite/ld-i386/plt-pic-nacl.pd: Likewise. * testsuite/ld-i386/pr17709-nacl.rd: Likewise. * testsuite/ld-i386/pr19636-1d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2c-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2e-nacl.d: Likewise. * testsuite/ld-i386/pr19827-nacl.rd: Likewise. * testsuite/ld-i386/pr21884-nacl.d: Likewise. * testsuite/ld-i386/pr21884-nacl.t: Likewise. * testsuite/ld-i386/tlsbin-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-i386/tlsnopic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise. * testsuite/ld-x86-64/load1a-nacl.d: Likewise. * testsuite/ld-x86-64/load1b-nacl.d: Likewise. * testsuite/ld-x86-64/load1c-nacl.d: Likewise. * testsuite/ld-x86-64/load1d-nacl.d: Likewise. * testsuite/ld-x86-64/pie3-nacl.d: Likewise. * testsuite/ld-x86-64/plt-nacl.pd: Likewise. * testsuite/ld-x86-64/pr17709-nacl.rd: Likewise. * testsuite/ld-x86-64/pr19013-nacl.d: Likewise. * testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise. * testsuite/ld-x86-64/pr19827-nacl.rd: Likewise. * testsuite/ld-x86-64/pr21884-nacl.d: Likewise. * testsuite/ld-x86-64/pr21884-nacl.t: Likewise. * testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.pd: Likewise. * testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * Makefile.in: Regenerated. * po/BLD-POTFILES.in: Likewise.
2020-04-27x86: Add i386 PE big-object supportTamar Christina1-0/+2
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a couple of years ago. The BIG OBJ format is a slightly different COFF format which extends the size of the number of section field in the header from a uint16_t to a uint32_t and so greatly increases the number of sections allowed. However the 32-bit version of bfd never got support for this. The GHC Haskell compiler generates a great deal of symbols due to it's use of -ffunction-sections and -fdata-sections. This meant that we could not build the 32-bit version of the GHC Compiler for many releases now as binutils didn't have this support. This patch adds the support to the 32-bit port of binutils as well and also does come cleanup in the code. bfd/ChangeLog: * coff-i386.c (COFF_WITH_PE_BIGOBJ): New. * coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New. * config.bfd (targ_selvecs): Rename x86_64_pe_be_vec to x86_64_pe_big_vec as it not a big-endian format. (vec i386_pe_big_vec): New. * configure.ac: Likewise. * targets.c: Likewise. * configure: Regenerate. * pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG, COFF_WITH_PE_BIGOBJ): New. * pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG): New. (x86_64_pe_be_vec): Moved. gas/ChangeLog: * NEWS: Add news entry for big-obj. * config/tc-i386.c (i386_target_format): Support new format. * doc/c-i386.texi: Add i386 support. * testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific. * testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well. ld/ChangeLog: * pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
2020-04-21gas: Extend .symver directiveH.J. Lu1-0/+3
Extend .symver directive to update visibility of the original symbol and assign one original symbol to different versioned symbols: .symver foo, foo@VERS_1, local # Change foo to a local symbol. .symver foo, foo@VERS_2, hidden # Change foo to a hidden symbol. .symver foo, foo@@VERS_3, remove # Remove foo from symbol table. .symver foo, bar@V1 # Assign foo to bar@V1 and baz@V2. .symver foo, baz@V2 PR gas/23840 PR gas/25295 * NEWS: Mention .symver extension. * config/obj-elf.c (obj_elf_find_and_add_versioned_name): New function. (obj_elf_symver): Call obj_elf_find_and_add_versioned_name to add a version name. Add local, hidden and remove visibility support. (elf_frob_symbol): Handle the list of version names. Update the original symbol to local, hidden or remove it from the symbol table. (elf_frob_file_before_adjust): Handle the list of version names. * config/obj-elf.h (elf_visibility): New. (elf_versioned_name_list): Likewise. (elf_obj_sy): Change local to bitfield. Add rename, bad_version and visibility. Change versioned_name pointer to struct elf_versioned_name_list. * doc/as.texi: Update .symver directive. * testsuite/gas/symver/symver.exp: Run all *.d tests. Add more error checking tests. * testsuite/gas/symver/symver6.d: New file. * testsuite/gas/symver/symver7.d: Likewise. * testsuite/gas/symver/symver7.s: Likewise. * testsuite/gas/symver/symver8.d: Likewise. * testsuite/gas/symver/symver8.s: Likewise. * testsuite/gas/symver/symver9.s: Likewise. * testsuite/gas/symver/symver9a.d: Likewise. * testsuite/gas/symver/symver9b.d: Likewise. * testsuite/gas/symver/symver10.s: Likewise. * testsuite/gas/symver/symver10a.d: Likewise. * testsuite/gas/symver/symver10b.d: Likewise. * testsuite/gas/symver/symver11.d: Likewise. * testsuite/gas/symver/symver11.s: Likewise. * testsuite/gas/symver/symver12.d: Likewise. * testsuite/gas/symver/symver12.s: Likewise. * testsuite/gas/symver/symver13.d: Likewise. * testsuite/gas/symver/symver13.s: Likewise. * testsuite/gas/symver/symver14.d: Likewise. * testsuite/gas/symver/symver14.l: Likewise. * testsuite/gas/symver/symver15.d: Likewise. * testsuite/gas/symver/symver15.l: Likewise. * testsuite/gas/symver/symver6.l: Removed. * testsuite/gas/symver/symver6.s: Updated.
2020-04-07gas: Mention support for Intel SERIALIZE and TSXLDTRKH.J. Lu1-0/+2
* NEWS: Mention support for Intel SERIALIZE and TSXLDTRK instructions.
2020-03-11NEWS: Mention x86 assembler options for CVE-2020-0551H.J. Lu1-0/+4
* NEWS: Mention x86 assembler options for CVE-2020-0551.
2020-03-11Add support for generating DWARF-5 format directory and file name tables ↵Nick Clifton1-0/+4
from the assembler. PR 25611 PR 25614 * dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and li_segment_size fields. * dwarf.c (read_debug_line_header): Record the address size and segment selector size values (if present) in the lineinfo structure. (display_formatted_table): Warn if the format count is empty but the table itself is not empty. Display the format count and entry count at the start of the table dump. (display_debug_lines_raw): Display the address size and segement selector size fields, if present. * testsuite/binutils-all/dw5.W: Update expected output. gas * dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1. (DWARF2_FILE_SIZE_NAME): Default to -1. (DWARF2_LINE_VERSION): Default to the current dwarf level or 3, whichever is higher. (DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1. (NUM_MD5_BYTES): Define. (struct file entry): Add md5 field. (get_filenum): Delete and replace with... (get_basename): New function. (get_directory_table_entry): New function. (allocate_filenum): New function. (allocate_filename_to_slot): New function. (dwarf2_where): Use new functions. (dwarf2_directive_filename): Add support for extended .file pseudo-op. (dwarf2_directive_loc): Allow the use of file number zero with DWARF 5 or higher. (out_file_list): Rename to... (out_dir_and_file_list): Add DWARF 5 support. (out_debug_line): Emit extra values into the section header for DWARF 5. (out_debug_str): Allow for file 0 to be used with DWARF 5. * doc/as.texi (.file): Update the description of this pseudo-op. * testsuite/gas/elf-dwarf-5-file0.s: Add more lines. * testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output. * testsuite/gas/lns/lns-diag-1.l: Update expected error message. * NEWS: Mention the new feature.
2020-02-06[2.34] Mention x86 assembler options to align branchesH.J. Lu1-0/+5
* NEWS: Mention x86 assembler options to align branches for binutils 2.34.
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+2
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov1-0/+10
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess1-0/+3
Add a flag to control the version of CIE that is generated. By default gas produces CIE version 1, and this continues to be the default after this patch. However, a user can now provide --gdwarf-cie-version=NUMBER to switch to either version 3 or version 4 of CIE, version 2 was never released, and so causes an error as does any number less than 1 or greater than 4. Producing version 4 CIE requires two new fields to be added to the CIE, an address size field, and an segment selector field. For a flat address space the DWARF specification indicates that the segment selector should be 0, and the address size fields just contains the address size in bytes. For now we support 4 or 8 byte addresses, and the segment selector is always produced as 0. At some future time we might need to allow targets to override this. gas/ChangeLog: * as.c (parse_args): Parse --gdwarf-cie-version option. (flag_dwarf_cie_version): New variable. * as.h (flag_dwarf_cie_version): Declare. * dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to flag_dwarf_cie_version. * doc/as.texi (Overview): Document --gdwarf-cie-version. * NEWS: Likewise. * testsuite/gas/cfi/cfi.exp: Add new tests. * testsuite/gas/cfi/cie-version-0.d: New file. * testsuite/gas/cfi/cie-version-1.d: New file. * testsuite/gas/cfi/cie-version-2.d: New file. * testsuite/gas/cfi/cie-version-3.d: New file. * testsuite/gas/cfi/cie-version-4.d: New file. * testsuite/gas/cfi/cie-version.s: New file. include/ChangeLog: * dwarf2.h (DW_CIE_VERSION): Delete. Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
2019-09-19[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson1-0/+6
These NEWS entries had been missed when the instructions were added. gas/ChangeLog: 2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com> * NEWS: Add SVE2 and TME entries.
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell1-0/+2
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks1-4/+9
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: ↵Dennis Zhang1-0/+6
Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-05-16[PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWSAndre Vieira1-0/+3
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE.
generated by cgit v1.1 at 2025-02-01 00:21:03 +0000