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2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich1-0/+11
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich1-0/+10
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich1-0/+7
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess1-0/+11
2019-11-28gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess1-0/+7
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess1-0/+7
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess1-0/+5
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski1-0/+7
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers1-0/+12
2019-11-25Reverts patches providing octet support in dwarfChristian Eggers1-0/+12
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-0/+12
2019-11-20PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra1-0/+7
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess1-0/+17
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-0/+8
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-0/+10
2019-11-14x86: make AnySize an insn attributeJan Beulich1-0/+4
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich1-0/+6
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich1-0/+12
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson1-0/+4
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu1-0/+15
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu1-0/+6
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu1-0/+8
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-0/+8
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-0/+16
2019-11-12x86: introduce operand type "instance"Jan Beulich1-0/+11
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich1-0/+6
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-0/+9
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-0/+6
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-0/+8
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-0/+6
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-0/+8
2019-11-08x86: introduce operand type "class"Jan Beulich1-0/+14
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson1-0/+5
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-0/+18
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+13
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson1-0/+8
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson1-0/+8
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson1-0/+8
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-0/+44
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+14
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+6
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+15
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich1-0/+19
2019-11-04x86: re-arrange process_operands()Jan Beulich1-0/+5
2019-10-31i386; Add .code16gcc fldenv testsH.J. Lu1-0/+5
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu1-0/+12
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-0/+12
2019-10-30x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich1-0/+7
2019-10-30x86: drop stray WJan Beulich1-0/+5
2019-10-29Re: Optimise away eh_frame advance_loc 0Alan Modra1-0/+6
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