| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2006-05-16 | * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate constant values. | Nick Clifton | 1 | -0/+5 | |
| 2006-05-15 | 2006-05-15 Paul Brook <paul@codesourcery.com> | Paul Brook | 1 | -0/+5 | |
| bfd/ * cpu-arm.c (bfd_is_arm_mapping_symbol_name): Rename ... (bfd_is_arm_special_symbol_name): ... to this. Add type argument. Check symbol name is of specified type. * elf32-arm.c (elf32_arm_is_target_special_symbol, arm_elf_find_function, elf32_arm_output_symbol_hook): Use bfd_is_arm_special_symbol_name. * bfd-in.h (BFD_ARM_SPECIAL_SYM_TYPE_MAP, BFD_ARM_SPECIAL_SYM_TYPE_TAG, BFD_ARM_SPECIAL_SYM_TYPE_OTHER, BFD_ARM_SPECIAL_SYM_TYPE_ANY): Define. (bfd_is_arm_mapping_symbol_name): Remove prototype. (bfd_is_arm_special_symbol_name): Add prototype. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c (arm_adjust_symtab): Use bfd_is_arm_special_symbol_name. ld/testsuite/ * ld-arm/arm-be8.d: New test. * ld-arm/arm-be8.s: New test. * ld-arm/arm-elf.exp: Add arm-be8. | |||||
| 2006-05-15 | bfd: | Bob Wilson | 1 | -0/+7 | |
| * elf32-xtensa.c (check_loop_aligned): Fix reversed check for undefined opcode. Clean up assertions. (narrow_instruction, widen_instruction): Remove "do_it" parameters. Factor most of the code into separate functions.... (can_narrow_instruction, can_widen_instruction): New. (prev_instr_is_a_loop): New. (compute_ebb_proposed_actions): Combine error handling code for decode errors. Replace call to insn_decode_len with inline code. Use can_narrow_instruction and can_widen_instruction. Handle errors from call to xtensa_opcode_is_loop. (relax_section): Adjust calls to narrow_instruction and widen_instruction. gas: * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next, xg_assemble_vliw_tokens, xtensa_mark_narrow_branches, xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed): Handle errors from calls to xtensa_opcode_is_* functions. | |||||
| 2006-05-14 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+6 | |
| * config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests. | |||||
| 2006-05-11 | bfd/doc/ | Carlos O'Donell | 1 | -0/+5 | |
| 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * bfd.texinfo: Rename "Index" to "BFD Index" gas/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * doc/as.texinfo: Rename "Index" to "AS Index", and "ABORT" to "ABORT (COFF)". ld/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * ld.texinfo: Rename "Index" to "LD Index" | |||||
| 2006-05-11 | 2006-05-11 Paul Brook <paul@codesourcery.com> | Paul Brook | 1 | -0/+12 | |
| bfd/ * elf32-arm.c (elf32_arm_reloc_map): Add MOVW and MOVT relocs. (elf32_arm_final_link_relocate): Handle MOVW and MOVT relocs. (elf32_arm_gc_sweep_hook, elf32_arm_check_relocs): Ditto. * reloc.c: Ditto. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate. gas/ * config/tc-arm.c (parse_half): New function. (operand_parse_code): Remove OP_Iffff. Add OP_HALF. (parse_operands): Ditto. (do_mov16): Reject invalid relocations. (do_t_mov16): Ditto. Use Thumb reloc numbers. (insns): Replace Iffff with HALF. (md_apply_fix): Add MOVW and MOVT relocs. (tc_gen_reloc): Ditto. * doc/c-arm.texi: Document relocation operators ld/testsuite/ * ld-arm/arm-elf.exp: Add arm-movwt. * ld-arm/arm-movwt.d: New test. * ld-arm/arm-movwt.s: New test. * ld-arm/arm.ld: Add .far. | |||||
| 2006-05-11 | 2006-05-11 Paul Brook <paul@codesourcery.com> | Paul Brook | 1 | -0/+4 | |
| gas/ * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols. gas/testsuite/ * gas/arm/local_function.d: New test. * gas/arm/local_function.s: New test. | |||||
| 2006-05-11 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+5 | |
| * config/tc-mips.c (append_insn): Don't check the range of j or jal addresses. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Don't check the range of j or jal addresses. | |||||
| 2006-05-11 | Apply fixes to allow arm WinCE toolchain to produce working executables. | Nick Clifton | 1 | -0/+6 | |
| 2006-05-09 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+5 | |
| * config/tc-mips.c (append_insn): Only warn about an out-of-range j or jal address. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Only warn about an out-of-range j or jal address. | |||||
| 2006-05-09 | * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups against | Nick Clifton | 1 | -0/+6 | |
| symbols which are not going to be placed into the symbol table. * coffcode.h (coff_write_relocs): Produce an error message if a an out-of-range symbol index is detected in a reloc. | |||||
| 2006-05-09 | * expr.c (operand): Remove `if (0 && ..)' statement and | Ben Elliston | 1 | -0/+8 | |
| subsequently unused target_op label. Collapse `if (1 || ..)' statement. * app.c (do_scrub_chars): Remove unused case 0, as it is handled separately above the switch. | |||||
| 2006-05-08 | PR gas/2623b | Nick Clifton | 1 | -0/+5 | |
| * config/tc-msp430.c (line_separator_character): Define as |. | |||||
| 2006-05-08 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+18 | |
| * config/tc-mips.c (mips_set_options): Add ase_smartmips flag. (mips_opts): Likewise. (file_ase_smartmips): New variable. (ISA_HAS_ROR): SmartMIPS implements rotate instructions. (macro_build): Handle SmartMIPS instructions. (mips_ip): Likewise. (md_longopts): Add argument handling for smartmips. (md_parse_options, mips_after_parse_args): Likewise. (s_mipsset): Add .set smartmips support. (md_show_usage): Document -msmartmips/-mno-smartmips. * doc/as.texinfo: Document -msmartmips/-mno-smartmips and .set smartmips. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] * gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test. * gas/mips/mips.exp: Run smartmips test. | |||||
| 2006-05-07 | * write.c (relax_segment): Add pass count arg. Don't error on | Alan Modra | 1 | -0/+8 | |
| negative org/space on first two passes. (relax_seg_info): New struct. (relax_seg, write_object_file): Adjust. * write.h (relax_segment): Update prototype. | |||||
| 2006-05-05 | * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds | Julian Brown | 1 | -0/+8 | |
| checking. (do_neon_mov): Enable several VMOV variants for VFP. Add suitable architecture version checks. (insns): Allow overlapping instructions to be used in VFP mode. | |||||
| 2006-05-05 | 2006-05-05 H.J. Lu <hongjiu.lu@intel.com> | H.J. Lu | 1 | -0/+6 | |
| PR gas/2598 * config/obj-elf.c (obj_elf_change_section): Allow user specified SHF_ALPHA_GPREL. | |||||
| 2006-05-05 | * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups for PMEM | Nick Clifton | 1 | -0/+5 | |
| related expressions. * bfd/elf32-avr.c (elf32_avr_relax_delete_bytes): Iterate over all of the bfd's sections for the reloc-addend adjustments. | |||||
| 2006-05-05 | PR gas/2582 | Nick Clifton | 1 | -0/+10 | |
| * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the insertion of a directory separator character into a string at a given offset. Uses heuristics to decide when to use a backslash character rather than a forward-slash character. (dwarf2_directive_loc): Use the macro. (out_debug_info): Likewise. | |||||
| 2006-05-05 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+7 | |
| * config/tc-mips.c (macro_build): Add case 'k' to handle cache instruction. (macro): Add new case M_CACHE_AB. [ opcodes/ChangeLog ] * mips-opc.c: Add macro for cache instruction. [ include/opcode/ChangeLog ] * mips.h (enum): Add macro M_CACHE_AB. | |||||
| 2006-05-04 | gas/ | Kazu Hirata | 1 | -0/+10 | |
| * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated. (opcode_lookup): Issue a warning for opcode with OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated identical to OT_cinfix3. (TxC3w, TC3w, tC3w): New. (insns): Use tC3w and TC3w for comparison instructions with 's' suffix. gas/testsuite * gas/arm/armv1.d (error-output): New. * gas/arm/armv1.l: New. * gas/arm/thumb32.d (error-output): New. * gas/arm/thumb32.l: New. | |||||
| 2006-05-03 | * subsegs.h (struct frchain): Delete frch_seg. | Alan Modra | 1 | -0/+31 | |
| (frchain_root): Delete. (seg_info): Define as macro. * subsegs.c (frchain_root): Delete. (abs_seg_info, und_seg_info, absolute_frchain): Delete. (subsegs_begin, subseg_change): Adjust for above. (subseg_set_rest): Likewise. Add new frchain structs to seginfo rather than to one big list. (subseg_get): Don't special case abs, und sections. (subseg_new, subseg_force_new): Don't set frchainP here. (seg_info): Delete. (subsegs_print_statistics): Adjust frag chain control list traversal. * debug.c (dmp_frags): Likewise. * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag at frchain_root. Make use of known frchain ordering. (last_frag_for_seg): Likewise. (get_frag_fix): Likewise. Add seg param. (process_entries, out_debug_aranges): Adjust get_frag_fix calls. * write.c (chain_frchains_together_1): Adjust for struct frchain. (SUB_SEGMENT_ALIGN): Likewise. (subsegs_finish): Adjust frchain list traversal. * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise. (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise. (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise. (xtensa_fix_b_j_loop_end_frags): Likewise. (xtensa_fix_close_loop_end_frags): Likewise. (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise. (retrieve_segment_info): Delete frch_seg initialisation. | |||||
| 2006-05-03 | bfd/ | Alan Modra | 1 | -0/+7 | |
| * libbfd-in.h (_bfd_generic_new_section_hook): Declare. * section.c (bfd_abs_symbol, bfd_com_symbol): Delete. (bfd_und_symbol, bfd_ind_symbol): Delete. (BFD_FAKE_SECTION): Remove SYM_PTR param, set symbol_ptr_ptr to &SEC.symbol. (STD_SECTION): Adjust. (_bfd_generic_new_section_hook): New function, extracted from.. (bfd_section_init): ..here. (bfd_make_section_old_way): Call new_section_hook for abs, com, und and ind sections. * elf.c (_bfd_elf_large_com_section): Adjust. * aoutx.h (new_section_hook): Call _bfd_generic_new_section_hook. * pdp11.c (new_section_hook): Likewise. * coffcode.h (coff_new_section_hook): Likewise. * ecoff.c (_bfd_ecoff_new_section_hook): Likewise. * elf.c (_bfd_elf_new_section_hook): Likewise. * vms.c (vms_new_section_hook): Likwise. * elf32-arm.c (elf32_arm_new_section_hook): Check used_by_bfd isn't already set. * elf32-sh64.c (sh64_elf_new_section_hook): Likewise. * elf32-xtensa.c (elf_xtensa_new_section_hook): Likewise. * elf64-mmix.c (mmix_elf_new_section_hook): Likewise. * elf64-ppc.c (ppc64_elf_new_section_hook): Likewise. * elfxx-mips.c (_bfd_mips_elf_new_section_hook): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_new_section_hook): Likewise. * ieee.c (ieee_new_section_hook): Likewise. Call _bfd_generic_new_section_hook too. * mmo.c (mmo_new_section_hook): Likewise. * oasys.c (oasys_new_section_hook): Likewise. * som.c (som_new_section_hook): Likewise. * coff-w65.c (reloc_processing): Don't use bfd_abs_symbol. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * subsegs.c (subseg_get): Don't call obj_sec_set_private_data. * config/obj-elf.h (obj_sec_set_private_data): Delete. * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol. * config/tc-mn10300.c (tc_gen_reloc): Likewise. | |||||
| 2006-05-02 | * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4 | Joseph Myers | 1 | -0/+7 | |
| here. (md_apply_fix3): Multiply offset by 4 here for BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. testsuite: * gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh. * gas/arm/iwmmxt.d: Update expected results. * gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh. * gas/arm/iwmmxt-bad2.l: Update expected error messages. | |||||
| 2006-05-02 | 2006-05-02 H.J. Lu <hongjiu.lu@intel.com> | H.J. Lu | 1 | -0/+23 | |
| Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (output_invalid_buf): Change size for unsigned char. * config/tc-tic30.c (output_invalid_buf): Likewise. * config/tc-i386.c (output_invalid): Cast none-ascii char to unsigned char. * config/tc-tic30.c (output_invalid): Likewise. | |||||
| 2006-05-02 | binutils/ | Daniel Jacobowitz | 1 | -0/+8 | |
| * doc/Makefile.am (AM_MAKEINFOFLAGS): New. (TEXI2POD): Use AM_MAKEINFOFLAGS. (config.texi): Don't set top_srcdir. * doc/binutils.texi: Don't use top_srcdir. * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated. gas/ * doc/Makefile.am (AM_MAKEINFOFLAGS): New. (TEXI2POD): Use AM_MAKEINFOFLAGS. (asconfig.texi): Don't set top_srcdir. * doc/as.texinfo: Don't use top_srcdir. * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated. ld/ * Makefile.am (AM_MAKEINFOFLAGS): Add libiberty. (TEXI2POD): Use AM_MAKEINFOFLAGS. (configdoc.texi): Don't set top_srcdir. * ld.texinfo: Don't use top_srcdir. * aclocal.m4, Makefile.in: Regenerated. | |||||
| 2006-05-02 | 2006-05-02 Paul Brook <paul@codesourcery.com> | Paul Brook | 1 | -0/+7 | |
| bfd/ * elf32-arm.c (elf32_arm_final_link_relocate): Set thumb funciton bit for R_ARM_REL32. gas/ * config/tc-arm.c (arm_optimize_expr): New function. * config/tc-arm.h (md_optimize_expr): Define (arm_optimize_expr): Add prototype. (TC_FORCE_RELOCATION_SUB_SAME): Define. ld/testsuite/ * ld-arm/arm-elf.exp: Add thumb-rel32. * ld-arm/thumb-rel32.d: New test. * ld-arm/thumb-rel32.s: New test. | |||||
| 2006-05-02 | * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit | Ben Elliston | 1 | -0/+3 | |
| field unsigned. | |||||
| 2006-05-02 | * sb.h (sb_list_vector): Move to sb.c. | Ben Elliston | 1 | -0/+6 | |
| * sb.c (free_list): Use type of sb_list_vector directly. (sb_build): Fix off-by-one error in assertion about `size'. | |||||
| 2006-05-01 | * listing.c (listing_listing): Remove useless loop. | Ben Elliston | 1 | -0/+10 | |
| * macro.c (macro_expand): Remove is_positional local variable. * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1 and simplify surrounding expressions, where possible. (assign_symbol): Likewise. (s_weakref): Likewise. * symbols.c (colon): Likewise. | |||||
| 2006-05-01 | * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL. | Alan Modra | 1 | -0/+4 | |
| 2006-04-30 | [ gas/ChangeLog ] | Thiemo Seufer | 1 | -0/+8 | |
| 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * config/tc-mips.c (validate_mips_insn): Handling of udi cases. (mips_immed): New table that records various handling of udi instruction patterns. (mips_ip): Adds udi handling. [ include/opcode/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi instructions. [ opcodes/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips-opc.c (mips_builtin_opcodes): Add udi instructions "udi0" to "udi15". * mips-dis.c (print_insn_args): Adds udi argument handling. | |||||
| 2006-04-28 | * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end | Alan Modra | 1 | -0/+5 | |
| of list rather than beginning. | |||||
| 2006-04-26 | * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to... | Julian Brown | 1 | -0/+11 | |
| (is_quarter_float): Rename from above. Simplify slightly. (parse_qfloat_immediate): Parse a "quarter precision" floating-point number. (parse_neon_mov): Parse floating-point constants. (neon_qfloat_bits): Fix encoding. (neon_cmode_for_move_imm): Tweak to use floating-point encoding in preference to integer encoding when using the F32 type. | |||||
| 2006-04-26 | * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so | Julian Brown | 1 | -0/+83 | |
| zero-initialising structures containing it will lead to invalid types). (arm_it): Add vectype to each operand. (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias defined field. (neon_typed_alias): New structure. Extra information for typed register aliases. (reg_entry): Add neon type info field. (arm_reg_parse): Remove RTYPE argument (revert to previous arguments). Break out alternative syntax for coprocessor registers, etc. into... (arm_reg_alt_syntax): New function. Alternate syntax handling broken out from arm_reg_parse. (parse_neon_type): Move. Return SUCCESS/FAIL. (first_error): New function. Call to ensure first error which occurs is reported. (parse_neon_operand_type): Parse exactly one type. (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move. (parse_typed_reg_or_scalar): New function. Handle core of both arm_typed_reg_parse and parse_scalar. (arm_typed_reg_parse): Parse a register with an optional type. (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar result. (parse_scalar): Parse a Neon scalar with optional type. (parse_reg_list): Use first_error. (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse. (neon_alias_types_same): New function. Return true if two (alias) types are the same. (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type of elements. (insert_reg_alias): Return new reg_entry not void. (insert_neon_reg_alias): New function. Insert type/index information as well as register for alias. (create_neon_reg_alias): New function. Parse .dn/.qn directives and make typed register aliases accordingly. (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start of line. (s_unreq): Delete type information if present. (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_shift): Likewise. (parse_shifter_operand): Likewise. (parse_address): Likewise. (parse_tb): Likewise. (tc_arm_regname_to_dw2regnum): Likewise. (md_pseudo_table): Add dn, qn. (parse_neon_mov): Handle typed operands. (parse_operands): Likewise. (neon_type_mask): Add N_SIZ. (N_ALLMODS): New macro. (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error. (el_type_of_type_chk): Add some safeguards. (modify_types_allowed): Fix logic bug. (neon_check_type): Handle operands with types. (neon_three_same): Remove redundant optional arg handling. (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm) (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute) (do_neon_step): Adjust accordingly. (neon_cmode_for_logic_imm): Use first_error. (do_neon_bitfield): Call neon_check_type. (neon_dyadic): Rename to... (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield to allow modification of type of the destination. (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly. (do_neon_compare): Make destination be an untyped bitfield. (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX. (neon_mul_mac): Return early in case of errors. (neon_move_immediate): Use first_error. (neon_mac_reg_scalar_long): Fix type to include scalar. (do_neon_dup): Likewise. (do_neon_mov): Likewise (in several places). (do_neon_tbl_tbx): Fix type. (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane) (do_neon_ld_dup): Exit early in case of errors and/or use first_error. (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL. Handle .dn/.qn directives. (REGDEF): Add zero for reg_entry neon field. | |||||
| 2006-04-26 | * config/tc-arm.c (limits.h): Include. | Julian Brown | 1 | -0/+147 | |
| (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1) (fpu_vfp_v3_or_neon_ext): Declare constants. (neon_el_type): New enumeration of types for Neon vector elements. (neon_type_el): New struct. Define type and size of a vector element. (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per instruction. (neon_type): Define struct. The type of an instruction. (arm_it): Add 'vectype' for the current instruction. (isscalar, immisalign, regisimm, isquad): New predicates for operands. (vfp_sp_reg_pos): Rename to... (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn tags. (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ (Neon D or Q register). (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D register. (GE_OPT_PREFIX_BIG): Define constant, for use in... (my_get_expression): Allow above constant as argument to accept 64-bit constants with optional prefix. (arm_reg_parse): Add extra argument to return the specific type of register in when either a D or Q register (REG_TYPE_NDQ) is requested. Can be NULL. (parse_scalar): New function. Parse Neon scalar (vector reg and index). (parse_reg_list): Update for new arm_reg_parse args. (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists. (parse_neon_el_struct_list): New function. Parse element/structure register lists for VLD<n>/VST<n> instructions. (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args. (s_arm_unwind_save_mmxwr): Likewise. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_big_immediate): New function. Parse an immediate, which may be 64 bits wide. Put results in inst.operands[i]. (parse_shift): Update for new arm_reg_parse args. (parse_address): Likewise. Add parsing of alignment specifiers. (parse_neon_mov): Parse the operands of a VMOV instruction. (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST, OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC, OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64, OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ. (parse_operands): Handle new codes above. (encode_arm_vfp_sp_reg): Rename to... (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if selected VFP version only supports D0-D15. (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z) (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2) (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst) (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new encode_arm_vfp_reg name, and allow 32 D regs. (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm) (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D regs. (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16) (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle constant-load and conversion insns introduced with VFPv3. (neon_tab_entry): New struct. (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and those which are the targets of pseudo-instructions. (neon_opc): Enumerate opcodes, use as indices into... (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB. (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT) (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE) (NEON_ENC_DUP): Define meaningful helper macros to look up values in neon_enc_tab. (neon_shape): Enumerate shapes (permitted register widths, etc.) for Neon instructions. (neon_type_mask): New. Compact type representation for type checking. (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common permitted type combinations. (N_IGNORE_TYPE): New macro. (neon_check_shape): New function. Check an instruction shape for multiple alternatives. Return the specific shape for the current instruction. (neon_modify_type_size): New function. Modify a vector type and size, depending on the bit mask in argument 1. (neon_type_promote): New function. Convert a given "key" type (of an operand) into the correct type for a different operand, based on a bit mask. (type_chk_of_el_type): New function. Convert a type and size into the compact representation used for type checking. (el_type_of_type_ckh): New function. Reverse of above (only when a single bit is set in the bit mask). (modify_types_allowed): New function. Alter a mask of allowed types based on a bit mask of modifications. (neon_check_type): New function. Check the type of the current instruction against the variable argument list. The "key" type of the instruction is returned. (neon_dp_fixup): New function. Fill in and modify instruction bits for a Neon data-processing instruction depending on whether we're in ARM mode or Thumb-2 mode. (neon_logbits): New function. (neon_three_same, neon_two_same, do_neon_dyadic_i_su) (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm) (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes) (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits) (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size) (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su) (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, neon_exchange_operands, neon_compare) (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul) (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul) (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv) (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun) (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn) (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt) (neon_move_immediate, do_neon_mvn, neon_mixed_length) (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long) (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull) (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov) (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp) (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est) (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx) (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave) (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup) (do_neon_ldx_stx): New functions. Neon bit encoding and encoding helpers. (parse_neon_type): New function. Parse Neon type specifier. (opcode_lookup): Allow parsing of Neon type specifiers. (REGNUM2, REGSETH, REGSET2): New macros. (reg_names): Add new VFPv3 and Neon registers. (NUF, nUF, NCE, nCE): New macros for opcode table. (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh, fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd, fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd. Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl, vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif, vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla, vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt, vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli, vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal, vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn, vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup, vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe, vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr, vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd], fto[us][lh][sd]. (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args. (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8. (arm_option_cpu_value): Add vfp3 and neon. (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix VFPv1 attribute. | |||||
| 2006-04-26 | Add missing changelog entry | Andreas Jaeger | 1 | -0/+18 | |
| 2006-04-25 | * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>" | Bob Wilson | 1 | -0/+8 | |
| syntax instead of hardcoded opcodes with ".w18" suffixes. (wide_branch_opcode): New. (build_transition): Use it to check for wide branch opcodes with either ".w18" or ".w15" suffixes. | |||||
| 2006-04-25 | * config/tc-xtensa.c (xtensa_create_literal_symbol, | Bob Wilson | 1 | -0/+6 | |
| xg_assemble_literal, xg_assemble_literal_space): Do not set the frag's is_literal flag. | |||||
| 2006-04-25 | * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default. | Bob Wilson | 1 | -0/+4 | |
| 2006-04-23 | * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c, | Kazu Hirata | 1 | -0/+8 | |
| config/tc-cris.c, config/tc-crx.c, config/tc-i386.c, config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h, config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c, config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos. | |||||
| 2006-04-20 | 2005-04-20 Paul Brook <paul@codesourcery.com> | Paul Brook | 1 | -0/+6 | |
| gas/ * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for all targets. (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets. gas/testsuite/ * gas/arm/arch7.d: Remove skip. * gas/arm/svc.d: Ditto. * gas/arm/thumb2_bcond.d: Ditto. * gas/arm/thumb2_it_bad.d: Ditto. | |||||
| 2006-04-19 | * Makefile.am (CPU_TYPES): Add maxq and mt. Sort. | Alan Modra | 1 | -0/+7 | |
| (CPU_OBJ_VALID): Change sense of COFF test to default to invalid. Make some cpus unsupported on ELF. Run "make dep-am". * Makefile.in: Regenerate. | |||||
| 2006-04-19 | bfd/ | Alan Modra | 1 | -0/+5 | |
| * warning.m4 (--enable-werror, -build-warnings): Format help messages. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure.in (--enable-targets): Indent help message. * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate. | |||||
| 2006-04-18 | gas/ | H.J. Lu | 1 | -0/+6 | |
| 2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * config/tc-i386.c (i386_immediate): Check illegal immediate register operand. gas/testsuite/ 2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * gas/i386/inval.s: Add test for illegal immediate register operand. * gas/i386/inval.l: Updated. | |||||
| 2006-04-18 | * config/tc-i386.c: Formatting. | Alan Modra | 1 | -0/+3 | |
| (output_disp, output_imm): ISO C90 params. | |||||
| 2006-04-18 | * frags.c (frag_offset_fixed_p): Constify args. | Alan Modra | 1 | -0/+3 | |
| * frags.h (frag_offset_fixed_p): Ditto. | |||||
| 2006-04-18 | * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete. | Alan Modra | 1 | -1/+4 | |
| (COFF_MAGIC): Delete. | |||||
| 2006-04-18 | * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete. | Alan Modra | 1 | -1/+5 | |
| 2006-04-16 | Update POTFILES.in. | Daniel Jacobowitz | 1 | -0/+4 | |
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