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2021-06-17Fix an assertion failure in the AArch64 assembler triggered by incorrect inst...Nick Clifton1-0/+7
2021-06-17gas: handle csect in bss section for XCOFFClément Chigot1-0/+7
2021-06-17gas: ensure sections contents is zero for BFD_RELOC_PPC*_TLSM on XCOFF.Clément Chigot1-0/+10
2021-06-16gas: fix hex float parsing from .dcb.? directivesJan Beulich1-0/+6
2021-06-16gas: fix overflow diagnosticsJan Beulich1-0/+10
2021-06-15x86: bring "gas --help" output for --32 etc in sync with realityJan Beulich1-0/+7
2021-06-15x86: simplify .dispNN settingJan Beulich1-0/+7
2021-06-15x86: slightly simplify offset_in_range()Jan Beulich1-0/+5
2021-06-15x86: harmonize disp with imm handlingJan Beulich1-0/+10
2021-06-15x86: make offset_in_range()'s warning contents useful (again)Jan Beulich1-0/+5
2021-06-15x86: off-by-1 in offset_in_range()Jan Beulich1-0/+9
2021-06-15x86: permit parenthesized expressions again as addressing scale factorJan Beulich1-0/+8
2021-06-14gas: fold three as_warn() in emit_expr_with_reloc()Jan Beulich1-0/+4
2021-06-14gas: drop TC_ADDRESS_BYTES conditionalsJan Beulich1-0/+6
2021-06-11x86: Always define TC_PARSE_CONS_EXPRESSIONH.J. Lu1-0/+6
2021-06-11RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.Nelson Chu1-0/+6
2021-06-10arm: avoid "shadowing" of glibc function nameJan Beulich1-0/+8
2021-06-10arm: fix array-out-of-bounds upon register parsing errorJan Beulich1-0/+4
2021-06-10x86: suppress LEA optimization in a specific 16-bit caseJan Beulich1-0/+8
2021-06-08x86: cover a.out in recently added testsJan Beulich1-0/+6
2021-06-08x86: minor improvements to optimize_imm() (part II)Jan Beulich1-0/+5
2021-06-08x86: minor improvements to optimize_disp() (part II)Jan Beulich1-0/+5
2021-06-08x86-64: avoid bogus warnings with 32-bit addressingJan Beulich1-0/+11
2021-06-08x86: minor improvements to optimize_disp() (part I)Jan Beulich1-0/+5
2021-06-07x86: honor quoted figure braces in i386_att_operand()Jan Beulich1-0/+7
2021-06-07x86: better respect quotes in parse_operands()Jan Beulich1-0/+10
2021-06-07x86: allow unary operators to start a memory operandJan Beulich1-0/+8
2021-06-07x86: make symbol quotation check consistent in i386_att_operand()Jan Beulich1-0/+7
2021-06-07x86: correct absolute branch check with segment overrideJan Beulich1-0/+5
2021-06-07x86/Intel: drop unnecessary bracket matching from parse_operands()Jan Beulich1-0/+5
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich1-0/+6
2021-06-07x86: immediate operands don't allow for vector operationsJan Beulich1-0/+4
2021-06-07ix86: wrap constantsJan Beulich1-0/+9
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra1-0/+5
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra1-0/+6
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki1-0/+56
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki1-0/+10
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki1-0/+99
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki1-0/+6
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki1-0/+18
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki1-0/+6
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki1-0/+12
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki1-0/+29
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-0/+6
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki1-0/+5
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki1-0/+10
2021-05-29MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1Maciej W. Rozycki1-0/+5
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu1-0/+9
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner1-0/+5
2021-05-27nds32: __builtin_strncpy bound equals destination sizeAlan Modra1-0/+6
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