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Fixes non-ELF powerpc build failure:
tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used
* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
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bfd/
PR 24144
* pdp11.c (set_section_contents): Revert 2015-02-24 change.
gas/
PR 24144
* config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end
of section to ensure file contents cover aligned section size.
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This adds support for the Neoverse N1 CPU [1] to gas.
This was previously enabled under the Ares codename, which remains as
a valid option for -mcpu for compatibility reasons.
make check-gas passes on arm-none-eabi.
[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure
2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add neoverse-n1.
* doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
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This adds support for the Neoverse E1 CPU [1] to gas.
make check-gas passes on aarch64-none-elf.
[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands
2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
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This adds support for the Neoverse N1 [1] CPU to gas.
This was previously enabled under the Ares codename, which remains as
a valid option for -mcpu for compatibility reasons.
make check-gas passes on aarch64-none-elf.
[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure
2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
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* NEWS: Mention -m[no-]fix-loongson3-llsc.
* configure.ac: Add --enable-mips-fix-loongson3-llsc.
Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):
New variables.
(options): New OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_longopts): Add -m[no-]fix-loongson3-llsc.
(md_begin): Initialize sync insn.
(fix_loongson3_llsc): New.
(append_insn): Call fix_loongson3_llsc.
(md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_show_usage): Display -m[no-]fix-loongson3-llsc.
* doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,
--enable-mips-fix-loongson3-llsc=[yes|no].
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ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed Mar 7 04:18:45 2018 -0800
x86: Rewrite NOP generation for fill and alignment
increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase
of assembler time and memory usage by 5 times for inputs with many
.p2align directives, which is typical for LTO output. This patch passes
max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set
as needed and tracked by backend it so that HANDLE_ALIGN can check the
maximum alignment for each rs_align_code frag. Wall time to assemble
the same cc1plus.s:
before:
423.78user 0.89system 7:05.71elapsed 99%CPU
after:
102.35user 0.27system 1:42.89elapsed 99%CPU
PR gas/24165
* frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
max_bytes.
* config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
aarch64_init_frag.
* /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
arm_init_frag.
* config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
* config/tc-ia64.h (TC_FRAG_INIT): Likewise.
* config/tc-mmix.h (TC_FRAG_INIT): Likewise.
* config/tc-nds32.h (TC_FRAG_INIT): Likewise.
* config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
* config/tc-rl78.h (TC_FRAG_INIT): Likewise.
* config/tc-rx.h (TC_FRAG_INIT): Likewise.
* config/tc-score.h (TC_FRAG_INIT): Likewise.
* config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
* config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
* config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
(alignment ? ((1 << alignment) - 1) : 1)
(i386_tc_frag_data): Add max_bytes.
(TC_FRAG_INIT): Add and track max_bytes.
(HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
fragP->tc_frag_data.max_bytes.
* doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
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The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64. In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment. This requires that HLT also be backported to all earlier
architectures. The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].
The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].
[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e
gas/ChangeLog:
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
opcodes/ChangeLog:
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
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instructions.
This patch just adds a few negative tests for the Armv8.3-a complex instructions.
These already do the right disassembly without needing a verifier, but adding
some tests to make sure that stays that way.
gas/ChangeLog:
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
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The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.
This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.
gas/ChangeLog:
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
opcodes/ChangeLog:
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
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This is done in order to avoid a pipeline hazard on the GR6.
gas/
* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction
on 64-bit boundaries for the GR6.
* testsuite/gas/visium/allinsn_gr6.s: Tweak.
* testsuite/gas/visium/allinsn_gr6.d: Likewise.
* testsuite/gas/visium/bra-1.d: New test.
* testsuite/gas/visium/bra-1.s: Likewise.
* testsuite/gas/visium/visium.exp: Run bra-1 test.
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mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source
operand should be accepted a relocatable expression. This change makes that
possible.
gas/
* config/tc-s12z.c (lex_imm): Add new argument exp_o.
(emit_reloc): New function.
(md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it
can be either 2 bytes or 3 bytes long.
* testsuite/gas/s12z/mov-imm-reloc.d: New file.
* testsuite/gas/s12z/mov-imm-reloc.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
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The limits for PC relative offsets were incorrect. This change fixes
them and adds some tests.
gas/
* config/tc-s12z.c (md_apply_fix): Fix incorrect limits.
* testsuite/gas/s12z/pc-rel-bad.d: New file.
* testsuite/gas/s12z/pc-rel-bad.l: New file.
* testsuite/gas/s12z/pc-rel-bad.s: New file.
* testsuite/gas/s12z/pc-rel-good.d: New file.
* testsuite/gas/s12z/pc-rel-good.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
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It is permissible for the source and destination operands of TFR and EXG to be
the same register. However it is a pointless instruction and anyone writing it
has probably made a mistake. This change emits a warning if such an instruction
is encountered.
gas/
* config/tc-s12z.c (tfr): Emit warning if operands are the same.
* testsuite/gas/s12z/exg.d: New test case.
* testsuite/gas/s12z/exg.l: New file.
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The assembler permitted instructions which attempted to assign to an immediate
operand. Bizarrely there is a valid machine code for such operations (although
the documentation says it's "inappropriate"). This change causes such attempts
to fail with an error message.
gas/
* config/tc-s12z.c (lex_opr): Add a parameter to indicate whether
immediate mode operands should be permitted.
* testsuite/s12z/imm-dest.d: New file.
* testsuite/s12z/imm-dest.l: New file.
* testsuite/s12z/imm-dest.s: New file.
* testsuite/s12z/s12z.exp: Add them.
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opcodes/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch13 as cpu string.
* s390-opc.c: Add new instruction formats and instruction opcode
masks.
* s390-opc.txt: Add new arch13 instructions.
include/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH13.
gas/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
* doc/c-s390.texi: Document arch13 march option.
* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
* testsuite/gas/s390/zarch-arch13.d: New test.
* testsuite/gas/s390/zarch-arch13.s: New test.
* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
also for z13.
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gcc-9 flagged warnings at the places I'm patching here, all real bugs.
* config/tc-alpha.c (md_apply_fix): Correct range checks for
BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.
* config/tc-arm.c (md_apply_fix): Use llabs rather than abs.
* config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
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xtensa gas chokes on 8/16 bit data entries representing constant symbols
because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD
cannot emit relocations. Resolve fixups for constant symbols in
md_apply_fix.
gas/
2019-01-28 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark fixups for constant
symbols as done in md_apply_fix.
* testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
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* configure.ac (ac_checking): Set from bfd/development.sh
development variable.
* configure: Regenerate.
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st2zg
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This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.
STGZM Xt, [<Xn|SP>]
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
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Extension.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
*** opcodes/ChangeLog ***
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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PR gas/23940
* macro.c (getstring): Check array bound before accessing.
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An assertion that can be triggered by user input is wrong, so remove
it. I believe the NUL would have been accepted before the PR20902
patch.
PR 20902
PR 24125
* read.c (stringer): Delete assertion.
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The PE targets don't support mapping symbols and so the disassembler is unable
to correctly output thumb instructions when the input was thumb.
So for testcases that only have thumb output, I have copied them and skipped the
ones for which auto-detection is supposed to work on PE, and added a new one
that will force thumb output. This so that the tests still check the mapping
symbols.
For the tests that switch between thumb and arm in one file I just skip them
entirely on PE targets.
This cleans up the PE GAS testsuite.
gas/
* testsuite/gas/arm/archv6t2-1-pe.d: New test.
* testsuite/gas/arm/archv6t2-1.d: Skip pe.
* testsuite/gas/arm/csdb.d: Skip pe.
* testsuite/gas/arm/sb-thumb1-pe.d: New test.
* testsuite/gas/arm/sb-thumb1.d: Skip pe.
* testsuite/gas/arm/sb-thumb2-pe.d: New test.
* testsuite/gas/arm/sb-thumb2.d: Skip pe.
* testsuite/gas/arm/udf.d: Skip pe.
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2019-01-16 Kito Cheng <kito@andestech.com>
bfd/
* elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even
for OBJ_ATTR_PROC.
gas/
* testsuite/gas/riscv/attribute-empty.d: New.
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2019-01-16 Kito Cheng <kito@andestech.com>
Nelson Chu <nelson@andestech.com>
bfd/
* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Define as
riscv_elf_obj_attrs_arg_type.
* elfxx-riscv.c (riscv_estimate_digit): New.
(riscv_estimate_arch_strlen1): Likewise.
(riscv_estimate_arch_strlen): Likewise.
(riscv_arch_str1): Likewise.
(riscv_arch_str): Likewise.
* elfxx-riscv.h (riscv_arch_str): Declare.
binutils/
* readelf.c (get_riscv_section_type_name): New function.
(get_section_type_name): Add handler for RISC-V.
(riscv_attr_tag_t): Declare.
(riscv_attr_tag): New.
(display_riscv_attribute): New function.
(process_attributes): Add handler for RISC-V.
* testsuite/binutils-all/strip-3.d: Remove .riscv.attribute
section.
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
(riscv_set_options): Add `arch_attr` field.
(riscv_opts): Set default value for arch_attr.
(riscv_write_out_arch_attr): New.
(riscv_set_public_attributes): Likewise.
(riscv_md_end): Likewise.
(riscv_convert_symbolic_attribute): Likewise.
(s_riscv_attribute): Likewise.
(explicit_arch_attr): Likewise.
(riscv_pseudo_table): Add .attribute to the table.
(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
enumeration constants.
(md_longopts): Add `march-attr' and `mno-arch-attr' options.
(md_parse_option): Handle the new options.
(md_show_usage): Document the `march-attr' option.
* config/tc-riscv.h (md_end): Define as riscv_md_end
(riscv_md_end): Declare.
(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
riscv_convert_symbolic_attribute.
(riscv_convert_symbolic_attribute): Declare.
(start_assemble): Declare.
* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
* testsuite/gas/elf/section2.e-riscv: New.
* testsuite/gas/riscv/attribute-01.d: New test
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-04.s: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-06.s: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-07.s: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-08.s: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.s: Likewise.
* testsuite/gas/riscv/empty.l: Likewise.
* doc/c-riscv.texi (.attribute): Add documentation.
* configure.ac (--enable-default-riscv-attribute): New options.
* configure: Re-generate.
* config.in: Re-generate.
include/
* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
(Tag_RISCV_arch): Likewise.
(Tag_RISCV_priv_spec): Likewise.
(Tag_RISCV_priv_spec_minor): Likewise.
(Tag_RISCV_priv_spec_revision): Likewise.
(Tag_RISCV_unaligned_access): Likewise.
(Tag_RISCV_stack_align): Likewise.
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The assembler incorrectly recognised "c" as a register name, and
refused to allow it where it expected a symbol/label.
gas/
* config/tc-s12z.c (lex_reg_name): Compare the length of the strings
before the contents.
* testsuite/gas/s12z/labels.d: New file.
* testsuite/gas/s12z/labels.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
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Other assemblers permit "extending" a register into a register of a
smaller size or the same size. It doesn't make much sense to do this
but would appear to be a valid instruction. So change the error to a
warning.
gas/
* config/tc-s12z.c (tfr): Change as_bad to as_warn.
Also fix message typo and semantics.
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When assembling instructions which involve OPR references, emit
RELOC_S12Z_OPR instead of RELOC_EXT24.
bfd/
* bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc.
* libbfd.h: regen.
* elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero
source field. (md_apply_fix): Apply final fix
to BFD_RELOC_S12Z_OPR.
* reloc.c[BFD_RELOC_S12Z_OPR]: New reloc.
gas/
* config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
BFD_RELOC_24.
* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
of R_S12Z_EXT24.
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both ARM mode and Thumb mode.
* config/tc-arm.c (arm_ext_v6k_v6t2): Define.
(insns) [ARM_VARIANT]: Modified.
(insns) [THUMB_VARIANT]: To implement few ARMv6K instructions
in ARMv6T2 as well.
* testsuite/gas/arm/archv6t2-1.d: New test.
* testsuite/gas/arm/archv6t2-1.s: Likewise.
* testsuite/gas/arm/archv6t2-2.d: Likewise.
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PR 23963
* testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change.
* testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
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PR 23963
binutils* objdump.c (sanitize_string): New function. Removes control
characters from symbol names.
(dump_section_header): Use new function.
(objdump_print_symname): Likewise.
(objdump_print_addr_with_sym): Likewise.
(show_line): Likewise.
(disassemble_bytes): Likewise.
(disassemble_section): Likewise.
(load_specific_debug_section): Likewise.
(read_section_stabs): Likewise.
(print_section_stabs): Likewise.
(dump_section): Likewise.
(dump_reloc_set): Likewise.
(dump_relocs_in_section): Likewise.
(dump_bfd): Likewise.
(display_any_bfd): Likewise.
gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that
control characters are now displayed as escape sequences.
* testsuite/gas/mips/mips16-e.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d:
Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d:
Likewise.
* testsuite/gas/mips/mipsel16-e.d: Likewise.
* testsuite/gas/mips/mipsr6@msa.d: Likewise.
* testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Likewise.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
* testsuite/gas/mips/r6.d: Likewise.
* testsuite/gas/mips/tmips16-e.d: Likewise.
* testsuite/gas/mips/tmipsel16-e.d: Likewise.
* testsuite/gas/mn10300/relax.d: Likewise.
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gas/
* testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
opcodes/
* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
zero.
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Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors
that do not define `__GNUC__`, leaving the string in the output.
bfd/
* warning.m4: Adjust egrep pattern for non-GNU compilers.
* configure: Regenerate.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
gold/
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
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This adds support for the Arm Ares CPU for AArch64.
It implements the Armv8.2-A architecture with the optional features
of statistical profiling, dot product and FP16 on by default.
Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.
* config/tc-aarch64.c (aarch64_cpus): Add ares.
* doc/c-aarch64.texi (-mcpu): Document ares value.
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Some existing tests build .s and .d files for run_dump_test, using an
absolute #source: line in the .d file. This patch changes that scheme
a little to instead use "#source: ./..." in .d files rather than
"#source: $objdir/...", which is more useful in cases where the .d
file is not generated.
This allows RX gas test files to be built in the build directory,
rather than in a source directory (which might be read-only).
binutils/
* testsuite/lib/binutils-common.exp (run_dump_test): Don't prepend
$srcdir/$subdir to source file name if it starts with "./".
gas/
* testsuite/gas/rx/rx.exp: Create generated test source in
current directory.
* testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d,
* testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d,
* testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d,
* testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d,
* testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d,
* testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d,
* testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d,
* testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d,
* testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d,
* testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d,
* testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d,
* testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d,
* testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d,
* testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d,
* testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d,
* testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d,
* testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d,
* testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d,
* testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d,
* testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d,
* testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d,
* testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d,
* testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d,
* testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d,
* testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d,
* testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d,
* testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d,
* testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d,
* testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d,
* testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d,
* testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d,
* testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d,
* testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d,
* testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d,
* testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d,
* testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d,
* testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d,
* testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d,
* testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d,
* testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d,
* testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d,
* testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d,
* testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d,
* testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d,
* testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d,
* testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d,
* testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d,
* testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d,
* testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d,
* testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d,
* testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d,
* testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d,
* testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d,
* testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d,
* testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d,
* testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d,
* testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d,
* testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d,
* testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d,
* testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d,
* testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d,
* testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d,
* testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d,
* testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d,
* testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d,
* testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d,
* testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d,
* testsuite/gas/rx/xor.d: Add #source line.
ld/
* testsuite/ld-elf/sec64k.exp: Use . rather than $objdir in
generated source file names.
* testsuite/ld-m68k/m68k-got.exp: Likewise.
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This adds support for the Arm Ares CPU in the arm port.
It implements the Armv8.2-A architecture with the relevant optional
features
of dot product and FP16 on by default.
Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.
* config/tc-arm.c (arm_cpus): Add ares.
* doc/c-arm.texi (-mcpu): Document ares value.
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Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf
* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
(rx_bfield): Add prototype.
(rx_post): Likewise.
* config/rx-parse.y: Add v3 instructions and Double FPU registers.
(DSIZE): Define.
(POST): Define.
(rx_check_v3): New. check v3 type.
(rx_check_dfpu): New. check have double support.
(double_condition_table): New. dcmp<cond> contiditon.
(check_condition): Multiple condition support.
(rx_lex): RXv3 instructions support.
Add parse dcmp<cond> instruction and Double FPU registers.
(immediate): Disable optimize in dmov #imm case.
(displacement): Add double displacement in dmov instraction.
* config/tc-rx.c (rx_use_conventional_section_names):
Invert default value in rx-*-linux target.
(cpu_type): Add additional ELF flags.
(cpu_type_list): Add RXv3.
(md_parse_option): Refer elf_flags from cpu_type_list.
(md_show_usage): Add rxv3 and rxv3-dfpu.
(rx_bytesT): Add post byte.
(rx_bfield): New. generate bfmov / bfmovz "imm" field.
(rx_post): New. Set instruction post byte.
(md_assemble): Add post byte.
doc/c-rx.texi: Add cpu types.
* testsuite/gas/rx/Xtod.d: New.
* testsuite/gas/rx/Xtod.sm: New.
* testsuite/gas/rx/bfmov.d: New.
* testsuite/gas/rx/bfmov.sm: New.
* testsuite/gas/rx/dabs.d: New.
* testsuite/gas/rx/dabs.sm: New.
* testsuite/gas/rx/dadd.d: New.
* testsuite/gas/rx/dadd.sm: New.
* testsuite/gas/rx/dcmp.d: New.
* testsuite/gas/rx/dcmp.sm: New.
* testsuite/gas/rx/ddiv.d: New.
* testsuite/gas/rx/ddiv.sm: New.
* testsuite/gas/rx/dmov.d: New.
* testsuite/gas/rx/dmov.sm: New.
* testsuite/gas/rx/dmul.d: New.
* testsuite/gas/rx/dmul.sm: New.
* testsuite/gas/rx/dneg.d: New.
* testsuite/gas/rx/dneg.sm: New.
* testsuite/gas/rx/dpopm.d: New.
* testsuite/gas/rx/dpopm.sm: New.
* testsuite/gas/rx/dpushm.d: New.
* testsuite/gas/rx/dpushm.sm: New.
* testsuite/gas/rx/dround.d: New.
* testsuite/gas/rx/dround.sm: New.
* testsuite/gas/rx/dsqrt.d: New.
* testsuite/gas/rx/dsqrt.sm: New.
* testsuite/gas/rx/dsub.d: New.
* testsuite/gas/rx/dsub.sm: New.
* testsuite/gas/rx/dtoX.d: New.
* testsuite/gas/rx/dtoX.sm: New.
* testsuite/gas/rx/macros.inc: Add double FPU registers.
* testsuite/gas/rx/mvfdc.d: New.
* testsuite/gas/rx/mvfdc.sm: New.
* testsuite/gas/rx/mvfdr.d: New.
* testsuite/gas/rx/mvfdr.sm: New.
* testsuite/gas/rx/mvtdc.d: New.
* testsuite/gas/rx/mvtdc.sm: New.
* testsuite/gas/rx/rstr.d: New.
* testsuite/gas/rx/rstr.sm: New.
* testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
* testsuite/gas/rx/save.d: New.
* testsuite/gas/rx/save.sm: New.
* testsuite/gas/rx/xor.d: New.
* testsuite/gas/rx/xor.sm: Add pattern.
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PR 24010
* macro.c (get_any_string): Check for end of input whilst scanning
for separators.
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PR 24009
* read.c (stringer): Fix handling of missing '>' character at end
of <...> sequence.
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For PLT expressions, we should subtract the PLT relocation size only for
jump instructions. Since PLT relocations are PC relative, we only allow
"symbol@PLT" in PLT expression.
gas/
PR gas/23997
* config/tc-i386.c (x86_cons): Check for invalid PLT expression.
(md_apply_fix): Subtract the PLT relocation size only for jump
instructions.
* testsuite/gas/i386/reloc32.s: Add test for invalid PLT
expression.
* testsuite/gas/i386/reloc64.s: Likewise.
* testsuite/gas/i386/ilp32/reloc64.s: Likewise.
* testsuite/gas/i386/reloc32.l: Updated.
* testsuite/gas/i386/reloc64.l: Likewise.
* testsuite/gas/i386/ilp32/reloc64.l: Likewise.
ld/
PR gas/23997
* testsuite/ld-i386/i386.exp: Run PR gas/23997 test.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/pr23997a.s: New file.
* testsuite/ld-x86-64/pr23997b.c: Likewise.
* testsuite/ld-x86-64/pr23997c.c: Likewise.
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