| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -0/+5 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+6 |
| 2018-10-05 | x86: Add Intel ENCLV to assembler and disassembler | H.J. Lu | 1 | -0/+7 |
| 2018-10-05 | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 1 | -0/+12 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 1 | -0/+14 |
| 2018-10-05 | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 1 | -0/+7 |
| 2018-10-05 | or1k: Add OpenRISC gas documentation | Stafford Horne | 1 | -0/+8 |
| 2018-10-05 | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns | Richard Henderson | 1 | -0/+7 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 1 | -0/+20 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 1 | -0/+11 |
| 2018-10-03 | AArch64: Add MOVPRFX tests and update testsuite | Tamar Christina | 1 | -0/+74 |
| 2018-10-03 | AArch64: Constraint disassembler and assembler changes. | Tamar Christina | 1 | -0/+8 |
| 2018-10-03 | AArch64: Close sequences at the end of sections | Tamar Christina | 1 | -0/+6 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -0/+4 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 1 | -0/+11 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+5 |
| 2018-09-26 | Skip broken assembler test on Windows host. | Sandra Loosemore | 1 | -0/+5 |
| 2018-09-21 | Correct ChangeLog entry for commit b8426d169d3f8a | H.J. Lu | 1 | -1/+1 |
| 2018-09-21 | gas: Make bfin-parse.c/rl78-parse.c/rx-parse.c depend on bfd/reloc.c | H.J. Lu | 1 | -0/+8 |
| 2018-09-21 | Fix more fallout from 17f6ade235fc | Alan Modra | 1 | -0/+4 |
| 2018-09-20 | gas: Update expected outputs of "readelf -wL" | H.J. Lu | 1 | -0/+16 |
| 2018-09-20 | S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1 | Maciej W. Rozycki | 1 | -0/+5 |
| 2018-09-20 | PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1 | Maciej W. Rozycki | 1 | -0/+5 |
| 2018-09-20 | ARC: Fix build errors with large constants and C89 | Maciej W. Rozycki | 1 | -0/+5 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 1 | -0/+79 |
| 2018-09-18 | Fix Aarch64 bug in warning filtering. | Tamar Christina | 1 | -0/+5 |
| 2018-09-17 | RISC-V: bge[u] should get higher priority than ble[u]. | Jim Wilson | 1 | -0/+5 |
| 2018-09-17 | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq | H.J. Lu | 1 | -0/+10 |
| 2018-09-17 | x86: Set Vex=1 on VEX.128 only vmovd and vmovq | H.J. Lu | 1 | -0/+16 |
| 2018-09-17 | x86: Add -mvexwig=[0|1] option to assembler | H.J. Lu | 1 | -0/+22 |
| 2018-09-17 | Remove bogus notarget in gas teststuite | Alan Modra | 1 | -0/+17 |
| 2018-09-17 | A few hppa testcase tidies | Alan Modra | 1 | -0/+7 |
| 2018-09-17 | Ensure that binutils test names are unique. | Nick Clifton | 1 | -0/+12 |
| 2018-09-15 | x86: Set Vex=1 on VEX.128 only vmovq | H.J. Lu | 1 | -0/+8 |
| 2018-09-15 | Consolidate run_dump_test | Alan Modra | 1 | -0/+6 |
| 2018-09-15 | run_dump_test replace PROG with DUMPPROG in gas and ld | Alan Modra | 1 | -0/+36 |
| 2018-09-15 | gas testuite fixes: don't match dump.o | Alan Modra | 1 | -0/+248 |
| 2018-09-15 | gas run_dump_test rename stderr and error-output | Alan Modra | 1 | -0/+431 |
| 2018-09-15 | gas run_dump_test rename not-target and not-skip | Alan Modra | 1 | -0/+154 |
| 2018-09-15 | Remove run_dump_test support for objcopy as a dump program | Alan Modra | 1 | -0/+7 |
| 2018-09-14 | x86: Check non-WIG EVEX instruction encoding with -mevexwig=1 | H.J. Lu | 1 | -0/+10 |
| 2018-09-14 | x86: Support VEX/EVEX WIG encoding | H.J. Lu | 1 | -0/+7 |
| 2018-09-14 | x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode | H.J. Lu | 1 | -0/+5 |
| 2018-09-14 | x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode | H.J. Lu | 1 | -0/+7 |
| 2018-09-14 | csky: Support PC relative diff relocation | Lifang Xia | 1 | -0/+9 |
| 2018-09-14 | x86: fold CRC32 templates | Jan Beulich | 1 | -0/+5 |
| 2018-09-13 | x86: Swap destination/source to encode VEX only if possible | H.J. Lu | 1 | -0/+5 |
| 2018-09-13 | x86: also allow D on 3-operand insns | Jan Beulich | 1 | -0/+7 |
| 2018-09-13 | x86: use D attribute also for SIMD templates | Jan Beulich | 1 | -0/+13 |
| 2018-09-13 | x86: fold ILP32 output of "opts" tests | Jan Beulich | 1 | -0/+8 |
