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AgeCommit message (Expand)AuthorFilesLines
2018-10-15BFD_INIT_MAGICAlan Modra1-0/+6
2018-10-11x86: add {,V}MOVQ cases to xmmword testJan Beulich1-0/+5
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-0/+5
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-0/+12
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das1-0/+7
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-0/+11
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+8
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das1-0/+6
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+16
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+8
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-0/+5
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+6
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+7
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das1-0/+12
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das1-0/+14
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das1-0/+7
2018-10-05or1k: Add OpenRISC gas documentationStafford Horne1-0/+8
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson1-0/+7
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+20
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson1-0/+11
2018-10-03AArch64: Add MOVPRFX tests and update testsuiteTamar Christina1-0/+74
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-0/+8
2018-10-03AArch64: Close sequences at the end of sectionsTamar Christina1-0/+6
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-0/+4
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-0/+11
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt1-0/+5
2018-09-26Skip broken assembler test on Windows host.Sandra Loosemore1-0/+5
2018-09-21Correct ChangeLog entry for commit b8426d169d3f8aH.J. Lu1-1/+1
2018-09-21gas: Make bfin-parse.c/rl78-parse.c/rx-parse.c depend on bfd/reloc.cH.J. Lu1-0/+8
2018-09-21Fix more fallout from 17f6ade235fcAlan Modra1-0/+4
2018-09-20gas: Update expected outputs of "readelf -wL"H.J. Lu1-0/+16
2018-09-20S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-0/+5
2018-09-20PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki1-0/+5
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki1-0/+5
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton1-0/+79
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina1-0/+5
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson1-0/+5
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-0/+10
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-0/+16
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-0/+22
2018-09-17Remove bogus notarget in gas teststuiteAlan Modra1-0/+17
2018-09-17A few hppa testcase tidiesAlan Modra1-0/+7
2018-09-17Ensure that binutils test names are unique.Nick Clifton1-0/+12
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-0/+8
2018-09-15Consolidate run_dump_testAlan Modra1-0/+6
2018-09-15run_dump_test replace PROG with DUMPPROG in gas and ldAlan Modra1-0/+36
2018-09-15gas testuite fixes: don't match dump.oAlan Modra1-0/+248
2018-09-15gas run_dump_test rename stderr and error-outputAlan Modra1-0/+431
2018-09-15gas run_dump_test rename not-target and not-skipAlan Modra1-0/+154
2018-09-15Remove run_dump_test support for objcopy as a dump programAlan Modra1-0/+7