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AgeCommit message (Expand)AuthorFilesLines
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu1-0/+9
2016-10-06-Wimplicit-fallthrough dodgy fixesAlan Modra1-0/+5
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune1-0/+10
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+48
2016-10-06-Wimplicit-fallthrough noreturn fixesAlan Modra1-0/+4
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra1-0/+13
2016-10-06bison warning fixesAlan Modra1-0/+5
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang1-0/+7
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-0/+6
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders1-0/+5
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov1-0/+6
2016-09-26PowerPC .gnu.attributesAlan Modra1-0/+5
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme1-0/+5
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-0/+21
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-0/+10
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-0/+17
2016-09-21Fix misplaced ChangeLogRichard Sandiford1-0/+15
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+15
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+18
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford1-0/+16
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford1-0/+25
2016-09-21[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_floatRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford1-0/+11
2016-09-21[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford1-0/+5
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu1-0/+5
2016-09-15gas: run the sparc test dcti-couples-v9 only in ELF targets.Jose E. Marchesi1-0/+6
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner1-0/+8
2016-09-14gas: improve architecture mismatch diagnostics in sparcJose E. Marchesi1-0/+5
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi1-0/+19
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu1-0/+7
2016-09-12S/390: Add alternate processor names.Andreas Krebbel1-0/+7
2016-09-12S/390: Fix facility bit default.Andreas Krebbel1-0/+4
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer1-0/+4
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu1-0/+5
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