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2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+6
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+8
2020-11-09Fix regexp for development.expAndreas Schwab1-0/+5
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu1-0/+32
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-0/+13
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+9
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+90
2020-11-03gas: fix symbol value calculation for versioned symbol aliasesChristian Eggers1-0/+5
2020-10-30x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE markerH.J. Lu1-0/+22
2020-10-26gas: Clear all auto-assigned file slotsH.J. Lu1-0/+11
2020-10-26Update gas/ChangeLog of last commitLifang Xia1-0/+5
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu1-0/+5
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu1-1/+4
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu1-0/+8
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-0/+6
2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni1-0/+9
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert1-0/+4
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+21
2020-10-17gas: Add a -gdwarf-5 debug_line test with .s fileH.J. Lu1-0/+8
2020-10-17gas: Replace dwarf5-line-2.S with dwarf5-line-3.SH.J. Lu1-0/+8
2020-10-17gas: Always use as_where for preprocessed assembly codesH.J. Lu1-0/+16
2020-10-16gas: Reuse the input file entry in the file tableH.J. Lu1-1/+17
2020-10-16Enhancement for avx-vnni patchCui,Lili1-0/+13
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+14
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+11
2020-10-14x86: Support Intel UINTRLili Cui1-0/+10
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-0/+10
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-0/+8
2020-10-09x86: Support GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu1-0/+40
2020-10-06aarch64: Fix bogus type punning in parse_barrier() [PR26699]Alex Coplan1-0/+8
2020-10-06A small set of code improvements for the Z80 assembler.Sergey Belyashav1-0/+12
2020-10-06Fix gas sh-link-zero test for hppa64-hpuxAlan Modra1-0/+5
2020-10-05Add NetBSD AArch64 GAS support.Kamil Rytarowski1-0/+4
2020-10-05Fix spelling mistakesSamanta Navarro1-0/+5
2020-10-05i386: Allow non-absolute segment values for lcall/ljmpT.K. Chia1-0/+13
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-0/+9
2020-10-05x86: Clear modrm if not neededH.J. Lu1-0/+8
2020-10-05GAS: Update the .section directive so that a numeric section index can be pro...Nick Clifton1-0/+14
2020-10-03x86: Update register operand check for AddrPrefixOpRegH.J. Lu1-0/+29
2020-10-02Fix the mve-vcvtne-it assembler test for the arm-*-pe targets.Nick Clifton1-0/+5
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton1-0/+15
2020-09-30x86: Check register operand for AddrPrefixOpRegH.J. Lu1-0/+13
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+6
2020-09-30NEWS: Mention recent Arm CPU supportAlex Coplan1-0/+4
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan1-0/+5
2020-09-30gcc-4.4.7 warning fixesAlan Modra1-0/+6
2020-09-29Add a note about recent changes to the AArch64 assembler: TRBE, ETE and ETMv4...Przemyslaw Wirkus1-0/+4
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus1-0/+6
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus1-7/+21
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus1-0/+5
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