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2020-03-11NEWS: Mention x86 assembler options for CVE-2020-0551H.J. Lu1-0/+4
2020-03-11i386: Add tests for lfence with load/indirect branch/retH.J. Lu1-0/+29
2020-03-11i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]H.J. Lu1-0/+28
2020-03-11Add support for generating DWARF-5 format directory and file name tables from...Nick Clifton1-0/+32
2020-03-10More 1 << 31 signed overflowsAlan Modra1-0/+9
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-0/+6
2020-03-07Re: Add support for a ".file 0" directive if supporting DWARF 5 or higher.Alan Modra1-0/+5
2020-03-06Add support for a ".file 0" directive if supporting DWARF 5 or higher.Nick Clifton1-0/+14
2020-03-06Add support for --dwarf-[3|4|5] to assembler command line.Nick Clifton1-0/+13
2020-03-06Stop the assembler from complaining that the input and output files are the s...Nick Clifton1-0/+6
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-0/+8
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-0/+7
2020-03-06x86: fold (supposed to be) identical codeJan Beulich1-0/+6
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-0/+13
2020-03-06x86: drop Rex64 attributeJan Beulich1-0/+5
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich1-0/+8
2020-03-06x86: add missing IgnoreSizeJan Beulich1-0/+21
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-0/+12
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu1-0/+9
2020-03-04RISC-V: Add description for RISC-V Modifiers to as doc.Nelson Chu1-0/+6
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load instructi...Alexandre Oliva1-0/+13
2020-03-04x86: support VMGEXITJan Beulich1-0/+10
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-0/+6
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov1-0/+10
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu1-0/+13
2020-03-03Fix a potential illegal memory access in the Z80 assembler.Sergey Belyashov1-0/+6
2020-03-03Tidy obj-coff.hAlan Modra1-0/+5
2020-03-02miscellaneous SEC_SMALL_DATAAlan Modra1-0/+11
2020-02-28MIPS/fix_loongson3_llsc: fix when target has multi labelsYunQiang Su1-0/+7
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson1-0/+10
2020-02-26gas gettext warningAlan Modra1-0/+5
2020-02-26gas strncpy warningAlan Modra1-0/+5
2020-02-26Indent labelsAlan Modra1-0/+24
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu1-0/+15
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu1-0/+14
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-0/+28
2020-02-21pdp11 reloc processingAlan Modra1-0/+5
2020-02-21PR25569, PDP11 ld -s clobbers last data byteAlan Modra1-0/+7
2020-02-19RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.Nelson Chu1-0/+5
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson1-0/+5
2020-02-19Various fixes for the Z80 support.Sergey Belyashov1-0/+36
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu1-0/+10
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-0/+6
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-0/+7
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich1-0/+13
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-0/+16
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-0/+6
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu1-0/+5
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-0/+28
2020-02-14x86: adjust segment override prefix emissionJan Beulich1-0/+8
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