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AgeCommit message (Expand)AuthorFilesLines
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich1-0/+5
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich1-0/+12
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson1-0/+4
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich1-0/+5
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-0/+8
2017-11-14x86: string insns don't allow displacementsJan Beulich1-0/+9
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich1-0/+5
2017-11-13gas/ia64: fix testsuite failuresJan Beulich1-0/+6
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-0/+7
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich1-0/+8
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich1-0/+11
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson1-0/+4
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina1-0/+5
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina1-0/+8
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+9
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+5
2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-0/+6
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang1-0/+32
2017-11-08xtensa message pluralizationAlan Modra1-0/+4
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson1-0/+8
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt1-0/+7
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina1-0/+6
2017-11-07bundle_lock message tidyAlan Modra1-0/+6
2017-11-07readelf ngettext fixesAlan Modra1-0/+35
2017-11-07gas and ld pluralization fixesAlan Modra1-0/+20
2017-11-07ngettext supportAlan Modra1-0/+5
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar1-0/+6
2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme1-0/+6
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman1-2/+29
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme1-0/+38
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu1-0/+19
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson1-0/+4
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra1-0/+8
2017-10-25Yet another fill-1 test fixAlan Modra1-9/+14
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman1-0/+10
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman1-0/+7
2017-10-24Fix my previous gas/ChangeLog entryPalmer Dabbelt1-2/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu1-0/+12
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt1-0/+5
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+162
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki1-0/+5
2017-10-22Fix spurious left-over quotes from last edit.Hans-Peter Nilsson1-0/+5
2017-10-20Improve handling of REPT pseudo op with a negative count.Nick Clifton1-0/+18
2017-10-19RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt1-0/+6
2017-10-19Fix the AVR assembler so that it will correctly issue warnings about skipped ...Nick Clifton1-0/+13
2017-10-19Fix fill-1 testcaseAndreas Krebbel1-0/+8
2017-10-18RISC-V: Mark unsupported gas testcasesPalmer Dabbelt1-0/+11
2017-10-18Update Cris assembler tests for checks that now pass where they used to fail.Nick Clifton1-0/+6
2017-10-18Update the Swedish translation in the GAS subdirectory.Nick Clifton1-0/+4
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