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2017-01-18Catch gas exit-via-signalNathan Sidwell1-0/+15
gas/ * as.h (gas_assert): Use abort. (as_assert): Remove. (signal_init): Declare. * as.c (main): Call signal_init. * messages.c: #include <signal.h> (as_assert): Delete. (as_abort): Allow NULL FILE. (signal_crash): New. (signal_init): Register fatal signal handlers. * configure.ac: Check for strsignal. * config.in: Rebuilt. * configure: Rebuilt.
2017-01-18Updated Swedish translation for GAS.Nick Clifton1-1/+1
2017-01-16Updated Swedish translations for GAS and LD subdirectories.Nick Clifton1-0/+4
gas * po/sv.po: Updated Swedish translation. ld * po/sv.po: Updated Swedish translation.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+13
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-12Prevent internal assembler errors if a stabs creation function builds an ↵Nick Clifton1-0/+13
badly formatted input string. * read.c (temp_ilp): New function. Installs a temporary input line pointer. (restore_ilp): New function. Restores the original input line pointer. * read.h (temp_ilp): Prototype. (restore_ilp): Prototype. * stabs.c (dot_func_p): Use bfd_boolean type. (generate_asm_file): Use temp_ilp and restore_ilp. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_endfunc): Likewise.
2017-01-11Add support for x86/64 redox target.Jeremy Soller1-0/+4
bfd * config.bfd: Add entries for i686-redox and x86_64-redox. gas * configure.tgt: Add entry for i386-redox. ld * configure.tgt: Add entries for x86-redox and x86_64-redox.
2017-01-10Fix sleb128-8 regressions.Tristan Gingold1-0/+5
gas/ * testsuite/gas/all/sleb128-8.d: Adjust test. * testsuite/gas/all/gas.exp (test_cond): Likewise.
2017-01-10Updated Swedish translations for GAS and LDNick Clifton1-0/+4
2017-01-10This patch ensure same output for sleb128 with large number.Tristan Gingold1-0/+8
gas/ * read.c (emit_leb128_expr): Extended unsigned big number for sleb128. * testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test. * testsuite/gas/all/sleb128.d: New test. * testsuite/gas/all/sleb128.s: New test source.
2017-01-09RISC-V/GAS: Support more relocs against constant addressesAndrew Waterman1-0/+6
Previously, some pseudoinstructions like "call" only accepted symbolic addresses and rejected constant addresses with an esoteric internal error. This patch enables them by deferring application of constant relocations to md_apply_fix, rather than eagerly applying them during instruction assembly. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (append_insn): Don't eagerly apply relocations against constants. (md_apply_fix): Mark relocations against constants as "done."
2017-01-09RISC-V/GAS: Improve handling of invalid relocsAndrew Waterman1-0/+6
TLS relocs against constants previously segfaulted, and illegal symbol subtractions were silently ignored. The previous behavior was to segfault. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (md_apply_fix): Report TLS relocations against constants. Report disallowed symbol subtractions.
2017-01-09Remove some custom sections from RISC-V's default linker scriptsPalmer Dabbelt1-0/+7
This was added so compressed loads could have smaller offsets for accessing the data section, but the result was that writable sections ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is to just remove this micro-optimization. Thanks to Alan Morda for finding the problem! ld/ChangeLog 2017-01-09 Palmer Dabbelt <palmer@dabbelt.com> Kito Cheng <kito.cheng@gmail.com> * emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS): Removed. (SDATA_START_SYMBOLS): Likewise.
2017-01-09Add Swedish translation for GAS.Nick Clifton1-0/+6
* po/sv.po: New Swedish translation. * configure.ac (ALL_LINGUAS): Add sv. * configure: Regenerate.
2017-01-09RISC-V/GAS: Correct branch relaxation for weak symbols.Andrew Waterman1-0/+5
* config/tc-riscv.c (relaxed_branch_length): Use the long sequence when the target is a weak symbol.
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+10
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04When configuring GAS treat as sparcv9 target the same way as a sparc64 target.Norm Jacobs1-0/+5
PR gas/20992 * configure.tgt: Treat sparcv9 as sparc64.
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+7
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03Fix PRU GAS for 32-bit hostsDimitar Dimitrov1-0/+6
The PRU GAS port I originally submitted does not build on 32bit hosts. This patch fixes it by aligning md_number_to_chars's definition with the global declaration in tc.h. Here is the original bug report I got: https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175 * config/tc-pru.c (md_number_to_chars): Fix parameter to be valueT, as declared in tc.h. (md_apply_fix): Fix to work on 32-bit hosts. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-6012/+2
2016-12-31PRU GAS PortDimitar Dimitrov1-0/+38
* NEWS: Mention new PRU target. * Makefile.am: Add PRU target. * config/obj-elf.c: Ditto. * configure.tgt: Ditto. * config/tc-pru.c: New file. * config/tc-pru.h: New file. * doc/Makefile.am: Add documentation for PRU GAS port. * doc/all.texi, Ditto. * doc/as.texinfo: Ditto. * doc/c-pru.texi: Document PRU GAS options. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/pru/alu.d: New file for PRU GAS testsuite. * testsuite/gas/pru/alu.s: Ditto. * testsuite/gas/pru/branch.d: Ditto. * testsuite/gas/pru/branch.s: Ditto. * testsuite/gas/pru/illegal.l: Ditto. * testsuite/gas/pru/illegal.s: Ditto. * testsuite/gas/pru/ldi.d: Ditto. * testsuite/gas/pru/ldi.s: Ditto. * testsuite/gas/pru/ldst.d: Ditto. * testsuite/gas/pru/ldst.s: Ditto. * testsuite/gas/pru/loop.d: Ditto. * testsuite/gas/pru/loop.s: Ditto. * testsuite/gas/pru/misc.d: Ditto. * testsuite/gas/pru/misc.s: Ditto. * testsuite/gas/pru/pru.exp: Ditto. * testsuite/gas/pru/pseudo.d: Ditto. * testsuite/gas/pru/pseudo.s: Ditto. * testsuite/gas/pru/warn_reglabel.l: Ditto. * testsuite/gas/pru/warn_reglabel.s: Ditto. * testsuite/gas/pru/xfr.d: Ditto. * testsuite/gas/pru/xfr.s: Ditto. * testsuite/gas/lns/lns.exp: Mark lns-common-1-alt variant for PRU. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-0/+8
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki1-0/+5
Simplify extended operand handling and only specially process immediates which require bit shuffling, using the generic operand insertion and extraction handlers for the '<' (5-bit shift amount) operand code in particular. Require the least significant bit of all extended operand forms to be (artificially) set to 0 for their special processing to trigger. gas/ * config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend' use to operands whose LSB position is zero. opcodes/ * mips-dis.c (print_mips16_insn_arg): Simplify processing of extended operands. * mips16-opc.c (decode_mips16_operand): Switch the extended form of the `<' operand type to LSB position 22.
2016-12-23MIPS16/GAS: Clean up invalid unextended operand handlingMaciej W. Rozycki1-0/+18
Bail out right away when an unextended instruction encoding is required either with the use of a `.t' suffix or by means of `.set noautoextend', however an operand supplied requires the extended instruction form to be used. This is to avoid messing up with the internal state of the assembler, even though no actual failures are known to happen as a result. Add test cases for the situation concerned. gas/ * config/tc-mips.c (match_mips16_insn): Don't update `forced_insn_length' or the instruction opcode if an operand requires an extended instruction form, but an unextended one has been requested. * testsuite/gas/mips/mips16-relax-unextended-1.d: New test. * testsuite/gas/mips/mips16-relax-unextended-2.d: New test. * testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr output. * testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr output. * testsuite/gas/mips/mips16-relax-unextended-1.s: New test source. * testsuite/gas/mips/mips16-relax-unextended-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-0/+6
Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise.
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+37
Identify non-extensible instructions in the MIPS16 opcode table and disallow their use with the `.e' instruction size suffix in assembly and do not interpret any EXTEND prefix present as a part of the instruction in disassembly. According to all versions of the MIPS16 ASE specifications the following instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R, I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [3][5]. Therefore in the presence of an EXTEND prefix none of these instructions are supposed to be handled as extended instructions and supporting these forms in disassembly causes confusion, and in the case of the RRR major opcode it also clashes with the ASMACRO encoding. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39 [4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49 [5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41 [6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51 include/ * opcode/mips.h (INSN2_SHORT_ONLY): New macro. gas/ * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix instruction size override for INSN2_SHORT_ONLY opcode table entries. * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-insn-e.s: New test source. * testsuite/gas/mips/mips16-insn-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix matching for INSN2_SHORT_ONLY opcode table entries. * mips16-opc.c (SH): New macro. (mips16_opcodes): Set SH in `pinfo2' for non-extensible instruction entries: "nop", "addu", "and", "break", "cmp", "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", "seh", "sew", "zeb", "zeh", "zew" and "extend". binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-extend-insn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki1-0/+5
Remove special casing for the `6' operand code used for the embedded trap code of the BREAK and the SDBBP instructions to support supposedly extended forms of these instructions. According to all versions of the MIPS16 ASE specifications these instructions are not extensible [1][2][3][4][5][7][8][10][11], and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [5][6][9][10]. Therefore supposedly extended BREAK and SDBBP instructions do not serve their purpose anymore as they do not cause a Bp and a Debug exception respectively and supporting these forms in disassembly only causes confusion. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] same, Table 18. "Extendable MIPS16 Instructions", p. 24 [4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38 [5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41 [6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41 [7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49 [8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39 [9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42 [10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43 [11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50 gas/ * config/tc-mips.c (match_mips16_insn): Remove the `6' operand code special case and its associated comment. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended encoding support.
2016-12-23MIPS16/GAS: Fix forced size suffixes with argumentless instructionsMaciej W. Rozycki1-0/+9
Correct the handling of `.e' and `.t' instruction size suffixes with instruction mnemonics which are not followed by any text on the same line, such as arguments or white space, e.g.: $ cat test.s .set mips16 foo: entry.t # comment entry.t exit.t # comment exit.t nop.t # comment nop.t $ as -32 -o test.o test.s test.s: Assembler messages: test.s:4: Error: unrecognized opcode `entry.t' test.s:6: Error: unrecognized opcode `exit.t' test.s:8: Error: unrecognized opcode `nop.t' $ gas/ * config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction suffixes followed by a null character rather than a space too. * testsuite/gas/mips/mips16-insn-length-noargs.d: New test. * testsuite/gas/mips/mips16-insn-length-noargs.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki1-0/+6
Do not allow any explicitly coded EXTEND instruction to be automatically scheduled into a jump delay slot, as an EXTEND prefix is coupled with the next regular MIPS16 instruction and therefore swapping it with a jump would change program's semantics; EXTEND is not architecturally allowed to be present in a jump delay slot anyway. opcodes/ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for "extend". gas/ * testsuite/gas/mips/mips16-extend-swap.d: New test. * testsuite/gas/mips/mips16-extend-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-23[msp430] Sync tc-msp430.c with devices.csvJoe Seymour1-0/+5
This patch syncs the generated data structure in tc-msp430.c with the latest version of devices.csv released by TI. My understanding is that the devices being removed were "invalid spins", so can't be being used by anyone, and never will be. Current web searches related to these devices return no relevant results. Built and tested (no regressions) as follows: Configured with: --target=msp430-elf --disable-gdb Test variations: msp430-sim/-mcpu=msp430 msp430-sim/-mcpu=msp430x msp430-sim/-mcpu=msp430x/-mlarge/-mdata-region=either/-mcode-region=either msp430-sim/-mhwmult=none msp430-sim/-mhwmult=f5series gas/ * config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's devices.csv file as of September 2016.
2016-12-23Bump version to 2.28.51Tristan Gingold1-0/+4
bfd/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.28.51 * configure: Regenerate. binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2016-12-23Add marker in NEWS filesTristan Gingold1-0/+4
binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28.
2016-12-23Regenerate pot files.Tristan Gingold1-0/+4
2016-12-22ChangeLog formatting fixesAlan Modra1-2/+2
2016-12-22Support aligning text section from odd addressesAndrew Waterman1-0/+5
Previously, the alignment directives were not correctly supported in the text section when current alignment was only 1 byte (i.e., when the address was odd). Since there are no 1-byte instructions in RISC-V, this patch resolves the bug by writing a zero byte to obtain 2-byte alignment, at which point a 2-byte NOP can be used to obtain 4-byte alignment. Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205 * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs. (riscv_frag_align_code): Correct frag_align_code arg.
2016-12-22Fix a const-safety issue on GCC-4.9 and aboveTim Newsome1-0/+5
* config/tc-riscv.c (riscv_pre_output_hook): Remove const from loc4_frag.
2016-12-21Remove high bit set charactersAlan Modra1-0/+5
gas/ * doc/c-lm32.texi: Fix chars with high bit set. * testsuite/gas/bfin/vector2.s: Likewise. gold/ * arm.cc: Fix comment chars with high bit set. include/ * coff/pe.h: Fix comment chars with high bit set. * opcode/xgate.h: Likewise. ld/ * testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
2016-12-21Document character escape sequencesAlan Modra1-0/+5
PR gas/10946 * doc/as.texinfo (Chars): Document escape sequences.
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki1-0/+17
Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20MIPS/GAS/testsuite: Add RESTORE instruction to `mips16e' testMaciej W. Rozycki1-0/+5
Add a RESTORE instruction smoke test to the `mips16e' GAS test. gas/ * testsuite/gas/mips/mips16e.s: Add a RESTORE instruction. * testsuite/gas/mips/mips16e.d: Adjust accordingly.
2016-12-20MIPS/GAS/testsuite: Extend MIPS16 testing over multiple ISAsMaciej W. Rozycki1-0/+42
Run the `mips16', `mips16-64', `mips16e-64', `mips16-macro', `mips16-macro-e' and `mips16-macro-t' GAS tests over multiple MIPS16 ISAs. gas/ * testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-macro.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation. * testsuite/gas/mips/mips16e-64.l: Rename to... * testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this. * testsuite/gas/mips/mips16-64@mips16.d: New test. * testsuite/gas/mips/mips16-64@mips16-64.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-64@mips16-macro.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64', `mips16-macro', `mips16-macro-t', `mips16-macro-e' and `mips16e-64' testing across multiple MIPS16 ISAs. Fold `mips16-macro' and `mips16e-64' list test invocations into corresponding dump tests.
2016-12-20MIPS/GAS/testsuite: Implement individual MIPS16 ISA testingMaciej W. Rozycki1-0/+14
Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit variants of the base MIPS16 and the MIPS16e ISA each. gas/ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add `mips16e' and `mips16' prefixes. (run_list_test_arch): Likewise. Rename `mips16' architecture to `mips16-32'. Add `mips16-64', `mips16e-32' and `mips16e-64' architectures. Update `rol64', `mips16e', `elf${el}-rel2' and `elf-rel4' test invocations accordingly. * testsuite/gas/mips/mips16e@branch-swap-3.d: New test. * testsuite/gas/mips/mips16e@branch-swap-4.d: New test. * testsuite/gas/mips/mips16e@loc-swap-dis.d: New test. * testsuite/gas/mips/mips16e@loc-swap.d: New test.
2016-12-20MIPS/GAS/testsuite: Fix trailing padding in `loc-swap.s'Maciej W. Rozycki1-0/+8
Pad alignment with zeros rather than NOP instructions, for sensible multi-ISA MIPS16 testing. gas/ * testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for trailing alignment padding. * testsuite/gas/mips/loc-swap.d: Adjust accordingly. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+33
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki1-0/+5
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki1-0/+7
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS/GAS/testsuite: Correct NewABI test selectionMaciej W. Rozycki1-0/+5
Make sure all tests that require NewABI support are only run with `has_newabi' targets, removing numerous `mips-sgi-irix5' failures. gas/ * testsuite/gas/mips/mips.exp: Limit remaining tests that require NewABI support to `has_newabi' targets.
2016-12-20Don't define RISC-V .p2alignAndrew Waterman1-0/+14
* config/tc-riscv.c (riscv_pseudo_table): Remove "align", "p2align", and "balign". (s_align): Remove. (riscv_handle_align): New function. (riscv_frag_align_code): Likewise. (riscv_make_nops): Likewise. * config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7. (HANDLE_ALIGN): Define. (md_do_align): Define. (riscv_handle_align): Declare. (riscv_frag_align_code): Likewise.
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-0/+19
We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-20Rework RISC-V relocationsAndrew Waterman1-0/+19
Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4.
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