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2006-07-06PR binutils/2877Nick Clifton1-0/+10
* doc/as.texi: Fix spelling typo: branchs => branches. * doc/c-m68hc11.texi: Likewise. * config/tc-m68hc11.c: Likewise. Support old spelling of command line switch for backwards compatibility.
2006-07-04 * config/tc-mips.c (s_is_linkonce): New function.Thiemo Seufer1-0/+8
(mips16_mark_labels): Don't adjust mips16 symbol addresses for weak, external, and linkonce symbols. (pic_need_relax): Use s_is_linkonce.
2006-06-242006-06-24 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+5
* doc/as.texinfo (Org): Remove space. (P2align): Add "@var{abs-expr},".
2006-06-23gas/H.J. Lu1-0/+14
2006-06-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch_tune_set): New. (cpu_arch_isa): Likewise. (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize nops with short or long nop sequences based on -march=/.arch and -mtune=. (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0, set cpu_arch_tune and cpu_arch_tune_flags. (md_parse_option): For -march=, set cpu_arch_isa and set cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is 0. Set cpu_arch_tune_set to 1 for -mtune=. (i386_target_format): Don't set cpu_arch_tune. gas/testsuite/ 2006-06-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686, nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1, x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom. * gas/i386/nops-1.s: New file. * gas/i386/nops-2.s: Likewise. * gas/i386/nops-1-i386.d: Likewise. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-1-merom.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d: Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/x86-64-nops-1.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-1-merom.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte nop.
2006-06-23 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sectionsThiemo Seufer1-0/+5
generated .sbss.* and .gnu.linkonce.sb.*.
2006-06-23 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segmentThiemo Seufer1-0/+11
label_list. * config/tc-mips.c (label_list): Define per-segment label_list. (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels, append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword, mips_from_file_after_relocs, mips_define_label): Use per-segment label_list.
2006-06-22 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.Thiemo Seufer1-0/+10
(append_insn): Use it. (md_apply_fix): Whitespace formatting. (md_begin, append_insn, macro, macro2, mips16_immed, mips_align, mips16_extended_frag): Remove register specifier. (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric constants.
2006-06-21Corrected typo in date.Mark Shinwell1-1/+1
2006-06-21gas/Mark Shinwell1-0/+11
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse a directive saving VFP registers for ARMv6 or later. (s_arm_unwind_save): Add parameter arch_v6 and call s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as appropriate. (md_pseudo_table): Add entry for new "vsave" directive. * doc/c-arm.texi: Correct error in example for "save" directive (fstmdf -> fstmdx). Also document "vsave" directive.
2006-06-19 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169pDenis Chertykov1-0/+8
and atmega644p devices. Rename atmega164/atmega324 devices to atmega164p/atmega324p. * doc/c-avr.texi: Document new mcu and arch options.
2006-06-17(enum parse_operand_result): Move outside of #ifdef OBJ_ELF so that non-ELFNick Clifton1-0/+5
targeted ARM ports can build.
2006-06-162006-06-16 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+23
* config/tc-i386.h (processor_type): New. (arch_entry): Add type. * config/tc-i386.c (cpu_arch_tune): New. (cpu_arch_tune_flags): Likewise. (cpu_arch_isa_flags): Likewise. (cpu_arch): Updated. (set_cpu_arch): Also update cpu_arch_isa_flags. (md_assemble): Update cpu_arch_isa_flags. (OPTION_MARCH): New. (OPTION_MTUNE): Likewise. (md_longopts): Add -march= and -mtune=. (md_parse_option): Support -march= and -mtune=. (md_show_usage): Add -march=CPU/-mtune=CPU. (i386_target_format): Also update cpu_arch_isa_flags, cpu_arch_tune and cpu_arch_tune_flags. * doc/as.texinfo: Add -march=CPU/-mtune=CPU. * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
2006-06-15 * include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}Mark Shinwell1-0/+25
to R_ARM_LDC_SB_G{0,1,2} respectively. bfd/ * bfd-in2.h: Regenerate. * elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0, R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2, R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0, R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1, R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1, R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1, R_ARM_LDC_SB_G2): New relocation types. (R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1 and friends. (elf32_arm_howto_table_3): Delete; contents merged into elf32_arm_howto_table_2. (elf32_arm_howto_from_type): Adjust correspondingly. (elf32_arm_reloc_map): Extend with the above relocations. (calculate_group_reloc_mask): New function. (identify_add_or_sub): New function. (elf32_arm_final_link_relocate): Support for the above relocations. * reloc.c: Add enumeration entries for BFD_RELOC_ARM_... codes to correspond to the above relocations. gas/ * config/tc-arm.c (enum parse_operand_result): New. (struct group_reloc_table_entry): New. (enum group_reloc_type): New. (group_reloc_table): New array. (find_group_reloc_table_entry): New function. (parse_shifter_operand_group_reloc): New function. (parse_address_main): New function, incorporating code from the old parse_address function. To be used via... (parse_address): wrapper for parse_address_main; and (parse_address_group_reloc): new function, likewise. (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR, OP_ADDRGLDRS, OP_ADDRGLDC. (parse_operands): Support for these new operand codes. New macro po_misc_or_fail_no_backtrack. (encode_arm_cp_address): Preserve group relocations. (insns): Modify to use the above operand codes where group relocations are permitted. (md_apply_fix): Handle the group relocations ALU_PC_G0_NC through LDC_SB_G2. (tc_gen_reloc): Likewise. (arm_force_relocation): Leave group relocations for the linker. (arm_fix_adjustable): Likewise. gas/testsuite/ * gas/arm/group-reloc-alu.d: New test. * gas/arm/group-reloc-alu-encoding-bad.d: New test. * gas/arm/group-reloc-alu-encoding-bad.l: New test. * gas/arm/group-reloc-alu-encoding-bad.s: New test. * gas/arm/group-reloc-alu-parsing-bad.d: New test. * gas/arm/group-reloc-alu-parsing-bad.l: New test. * gas/arm/group-reloc-alu-parsing-bad.s: New test. * gas/arm/group-reloc-alu.s: New test. * gas/arm/group-reloc-ldc.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.l: New test. * gas/arm/group-reloc-ldc-encoding-bad.s: New test. * gas/arm/group-reloc-ldc-parsing-bad.d: New test. * gas/arm/group-reloc-ldc-parsing-bad.l: New test. * gas/arm/group-reloc-ldc-parsing-bad.s: New test. * gas/arm/group-reloc-ldc.s: New test. * gas/arm/group-reloc-ldr.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.l: New test. * gas/arm/group-reloc-ldr-encoding-bad.s: New test. * gas/arm/group-reloc-ldr-parsing-bad.d: New test. * gas/arm/group-reloc-ldr-parsing-bad.l: New test. * gas/arm/group-reloc-ldr-parsing-bad.s: New test. * gas/arm/group-reloc-ldr.s: New test. * gas/arm/group-reloc-ldrs.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.l: New test. * gas/arm/group-reloc-ldrs-encoding-bad.s: New test. * gas/arm/group-reloc-ldrs-parsing-bad.d: New test. * gas/arm/group-reloc-ldrs-parsing-bad.l: New test. * gas/arm/group-reloc-ldrs-parsing-bad.s: New test. * gas/arm/group-reloc-ldrs.s: New test. ld/testsuite/ * ld-arm/group-relocs-alu-bad.d: New test. * ld-arm/group-relocs-alu-bad.s: New test. * ld-arm/group-relocs.d: New test. * ld-arm/group-relocs-ldc-bad.d: New test. * ld-arm/group-relocs-ldc-bad.s: New test. * ld-arm/group-relocs-ldr-bad.d: New test. * ld-arm/group-relocs-ldr-bad.s: New test. * ld-arm/group-relocs-ldrs-bad.d: New test. * ld-arm/group-relocs-ldrs-bad.s: New test. * ld-arm/group-relocs.s: New test. * ld-arm/arm-elf.exp: Wire in new tests.
2006-06-15 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...Julian Brown1-0/+6
(do_neon_ldr_str): Always defer to VFP encoding routines, which handle relocs properly.
2006-06-12gas/H.J. Lu1-0/+5
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-09 [ gas/ChangeLog ]Thiemo Seufer1-0/+4
* config/tc-mips.c (mips_ip): Maintain argument count. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-sf32.s, gas/mips/mips32-sf32.d: New test for odd single precision FPRs on MIPS32. * gas/mips/mips.exp: Run them.
2006-06-09 * config/tc-iq2000.c: Include sb.h.Alan Modra1-0/+4
2006-06-08 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"Thiemo Seufer1-0/+5
aliases for better compatibility with SGI tools.
2006-06-08 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.Alan Modra1-0/+14
* Makefile.am (GASLIBS): Expand @BFDLIB@. (BFDVER_H): Delete. (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants. (obj-aout.o): Depend on $(DEP_@target_get_type@_aout) (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly. Run "make dep-am". * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate.
2006-06-07bfd/doc:Joseph Myers1-0/+4
* bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
2006-06-07 * config/tc-arm.c (stdarg.h): include.Julian Brown1-0/+87
(arm_it): Add uncond_value field. Add isvec and issingle to operand array. (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and REG_TYPE_NSDQ (single, double or quad vector reg). (reg_expected_msgs): Update. (BAD_FPU): Add macro for unsupported FPU instruction error. (parse_neon_type): Support 'd' as an alias for .f64. (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ sets of registers. (parse_vfp_reg_list): Don't update first arg on error. (parse_neon_mov): Support extra syntax for VFP moves. (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO, OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ. (parse_operands): Support isvec, issingle operands fields, new parse codes above. (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs, msr variants. (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above. (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez. (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros. (NEON_SHAPE_DEF): New macro. Define table of possible instruction shapes. (neon_shape): Redefine in terms of above. (neon_shape_class): New enumeration, table of shape classes. (neon_shape_el): New enumeration. One element of a shape. (neon_shape_el_size): Register widths of above, where appropriate. (neon_shape_info): New struct. Info for shape table. (neon_shape_tab): New array. (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL. (neon_check_shape): Rewrite as... (neon_select_shape): New function to classify instruction shapes, driven by new table neon_shape_tab array. (neon_quad): New function. Return 1 if shape should set Q flag in instructions (or equivalent), 0 otherwise. (type_chk_of_el_type): Support F64. (el_type_of_type_chk): Likewise. (neon_check_type): Add support for VFP type checking (VFP data elements fill their containing registers). (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE in thumb mode for VFP instructions. (do_vfp_nsyn_opcode): New function. Look up the opcode in argument, and encode the current instruction as if it were that opcode. (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS arguments, call function in PFN. (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul) (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str) (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul) (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push) (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions. Redirect Neon-syntax VFP instructions to VFP instruction handlers. (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm) (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield) (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh) (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext) (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn) (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long) (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt) (do_neon_swp): Use neon_select_shape not neon_check_shape. Use neon_quad. (vfp_or_neon_is_neon): New function. Call if a mnemonic shared between VFP and Neon turns out to belong to Neon. Perform architecture check and fill in condition field if appropriate. (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg) (do_neon_cvt): Add support for VFP variants of instructions. (neon_cvt_flavour): Extend to cover VFP conversions. (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP vmov variants. (do_neon_ldr_str): Handle single-precision VFP load/store. (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use NS_NULL not NS_IGNORE. (opcode_tag): Add OT_csuffixF for operands which either take a conditional suffix, or have 0xF in the condition field. (md_assemble): Add support for OT_csuffixF. (NCE): Replace macro with... (NCE_tag, NCE, NCEF): New macros. (nCE): Replace macro with... (nCE_tag, nCE, nCEF): New macros. (insns): Add support for VFP insns or VFP versions of insns msr, mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop, vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia, vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared VFP/Neon insns together.
2006-06-07remove some duplicate #include's.Alan Modra1-0/+73
2006-06-07include/opcode/Alan Modra1-0/+8
* ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
2006-06-06 [ gas/ChangeLog ]Thiemo Seufer1-0/+12
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
2006-06-05 [ gas/ChangeLog ]Thiemo Seufer1-0/+11
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew appropriate. (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. (mips_ip): Make overflowed/underflowed constant arguments in DSP and MT instructions a fatal error. Use INSERT_OPERAND where appropriate. Improve warnings for break and wait code overflows. Use symbolic constant of OP_MASK_COPZ. (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d, gas/mips/mips32-mt.s: Remove instructions with invalid arguments. * gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file. [ include/opcode/ChangeLog ] * mips.h: Improve description of MT flags.
2006-06-05bfd/, binutils/, gas/, gprof/, ld/, opcodes/Daniel Jacobowitz1-0/+4
* po/Make-in (top_builddir): Define.
2006-06-02binutils:Joseph Myers1-0/+6
* doc/Makefile.am (TEXI2DVI): Define. * doc/Makefile.in: Regenerate. gas: * doc/Makefile.am (TEXI2DVI): Define. * doc/Makefile.in: Regenerate. * doc/c-arc.texi: Fix typo. ld: * Makefile.am (TEXI2DVI): Add -I $(top_srcdir)/../libiberty. * Makefile.in: Regenerate.
2006-06-01 * config/obj-ieee.c: Delete.Alan Modra1-0/+15
* config/obj-ieee.h: Delete. * Makefile.am (OBJ_FORMATS): Remove ieee. (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly. (obj-ieee.o): Remove rule. * Makefile.in: Regenerate. * configure.in (atof): Remove tahoe. (OBJ_MAYBE_IEEE): Don't define. * configure: Regenerate. * config.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2006-05-31Configury changes: update src repository (binutils, gdb, and rda) to useDaniel Jacobowitz1-0/+11
config/gettext-sister.m4 instead of the old gettext.m4. Regenerate all affected autotools files. Include intl in gdb releases again.
2006-05-30Update Spanish translationNick Clifton1-0/+4
2006-05-29 * doc/c-avr.texi: New file.Denis Chertykov1-0/+7
* doc/Makefile.am (CPU_DOCS): Add c-avr.texi * doc/all.texi: Set AVR * doc/as.texinfo: Include c-avr.texi
2006-05-28 * config/bfin-parse.y (check_macfunc): Loose the condition ofJie Zhang1-0/+5
calling check_multiply_halfregs ().
2006-05-26Remove ">>>>>>> 1.2917".H.J. Lu1-1/+0
2006-05-25 * config/bfin-parse.y (asm_1): Better check and deal withJie Zhang1-0/+6
vector and scalar Multiply 16-Bit Operands instructions.
2006-05-24Add TLS support for hppa-linuxNick Clifton1-0/+16
2006-05-24Add support for AVR6 familyNick Clifton1-0/+4
2006-05-23 [ gas/ChangeLog ]Thiemo Seufer1-0/+30
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, ISA_HAS_MXHC1): New macros. (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. (mips_cpu_info): Change to use combined ASE/IS_ISA flag. (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. (mips_after_parse_args): Change default handling of float register size to account for 32bit code with 64bit FP. Better sanity checking of ISA/ASE/ABI option combinations. (s_mipsset): Support switching of GPR and FPR sizes via .set {g,f}p={32,64,default}. Better sanity checking for .set ASE options. (mips_elf_final_processing): We should record the use of 64bit FP registers in 32bit code but we don't, because ELF header flags are a scarce ressource. (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document missing -march options. Document .set arch=CPU. Move .set smartmips to ASE page. Use @code for .set FOO examples. [ gas/testsuite/Changelog ] * gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d, gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler output. * gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files, catch assembler warnings.
2006-05-23 * config/tc-bfin.c (bfin_start_line_hook): Bump line countersJie Zhang1-0/+5
if needed.
2006-05-23 * config/bfin-defs.h (bfin_equals): Remove declaration.Jie Zhang1-0/+9
* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr". * config/tc-bfin.c (bfin_name_is_register): Remove. (bfin_equals): Remove. * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1. (bfin_name_is_register): Remove declaration.
2006-05-22Remove ChangeLog entries, since the template files were already up to date.Nick Clifton1-4/+0
2006-05-22Update translation templatesNick Clifton1-0/+4
2006-05-19 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.Thiemo Seufer1-0/+7
(mips_oddfpreg_ok): New function. (mips_ip): Use it. -------------------------------------------------------------------
2006-05-19 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.Thiemo Seufer1-0/+23
* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Reformat. (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC, RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK, RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES, FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES, N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES, SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES, MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names, reg_names_o32, reg_names_n32n64): Define register classes. (reg_lookup): New function, use register classes. (md_begin): Reserve register names in the symbol table. Simplify OBJ_ELF defines. (mips_ip): Fix comment formatting. Handle symbolic COP0 registers. Use reg_lookup. (mips16_ip): Use reg_lookup. (tc_get_register): Likewise. (tc_mips_regname_to_dw2regnum): New function. -------------------------------------------------------------------
2006-05-19 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):Thiemo Seufer1-0/+17
Un-constify string argument. * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum): Likewise. * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum): Likewise. * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum): Likewise. * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum): Likewise. * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum): Likewise. * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum): Likewise. -------------------------------------------------------------------
2006-05-19 * gas/config/tc-m68k.c (m68k_init_arch): Move checking ofNathan Sidwell1-0/+5
cfloat/m68881 to correct architecture before using it.
2006-05-16* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate constant values.Nick Clifton1-0/+5
2006-05-152006-05-15 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+5
bfd/ * cpu-arm.c (bfd_is_arm_mapping_symbol_name): Rename ... (bfd_is_arm_special_symbol_name): ... to this. Add type argument. Check symbol name is of specified type. * elf32-arm.c (elf32_arm_is_target_special_symbol, arm_elf_find_function, elf32_arm_output_symbol_hook): Use bfd_is_arm_special_symbol_name. * bfd-in.h (BFD_ARM_SPECIAL_SYM_TYPE_MAP, BFD_ARM_SPECIAL_SYM_TYPE_TAG, BFD_ARM_SPECIAL_SYM_TYPE_OTHER, BFD_ARM_SPECIAL_SYM_TYPE_ANY): Define. (bfd_is_arm_mapping_symbol_name): Remove prototype. (bfd_is_arm_special_symbol_name): Add prototype. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c (arm_adjust_symtab): Use bfd_is_arm_special_symbol_name. ld/testsuite/ * ld-arm/arm-be8.d: New test. * ld-arm/arm-be8.s: New test. * ld-arm/arm-elf.exp: Add arm-be8.
2006-05-15bfd:Bob Wilson1-0/+7
* elf32-xtensa.c (check_loop_aligned): Fix reversed check for undefined opcode. Clean up assertions. (narrow_instruction, widen_instruction): Remove "do_it" parameters. Factor most of the code into separate functions.... (can_narrow_instruction, can_widen_instruction): New. (prev_instr_is_a_loop): New. (compute_ebb_proposed_actions): Combine error handling code for decode errors. Replace call to insn_decode_len with inline code. Use can_narrow_instruction and can_widen_instruction. Handle errors from call to xtensa_opcode_is_loop. (relax_section): Adjust calls to narrow_instruction and widen_instruction. gas: * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next, xg_assemble_vliw_tokens, xtensa_mark_narrow_branches, xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed): Handle errors from calls to xtensa_opcode_is_* functions.
2006-05-14 [ gas/ChangeLog ]Thiemo Seufer1-0/+6
* config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
2006-05-11bfd/doc/Carlos O'Donell1-0/+5
2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * bfd.texinfo: Rename "Index" to "BFD Index" gas/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * doc/as.texinfo: Rename "Index" to "AS Index", and "ABORT" to "ABORT (COFF)". ld/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * ld.texinfo: Rename "Index" to "LD Index"
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