| Age | Commit message (Collapse) | Author | Files | Lines |
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call. Delete out of date comment.
(dwarf2_consume_line_info): Always clear dwarf2_loc_directive_seen.
(dwarf2_emit_label): Don't emit unless there has been a previous
.file or we are outputting assembler generated debug.
dwarf2_consume_line_info after emitting line info, not before.
(out_debug_info): Simplify files_in_use test.
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2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (parse_real_register): Return AVX register
only if AVX is enabled.
gas/testsuite/
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/att-regs.s: Add AVX register test.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Updated.
* gas/i386/intel-regs.d: Likewise.
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* config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
* gas/sh/sh64/eh-1.d: New.
* gas/sh/sh64/eh-1.d: Likewise.
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Bob Wilson <bob.wilson@acm.org>
* config/tc-xtensa.c (xg_apply_fix_value): Check return code from
call to decode_reloc.
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2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add attiny167.
* doc/c-avr.texi: Likewise.
/include:
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
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2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add atmega32u4.
* doc/c-avr.texi: Likewise.
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2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add atmega32c1.
* doc/c-avr.texi: Likewise.
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gas/
* config/tc-arm.c (parse_neon_mov): Parse register before immediate
to avoid spurious symbols.
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as_bad_where.
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* doc/c-avr.texi: Likewise.
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start of block.
(do_neon_ext): Fix sign of comparison.
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* config/tc-bfin.c (bfin_start_line_hook): Localize the labels
generated for LOOP_BEGIN and LOOP_END instructions.
(bfin_gen_loop): Likewise.
gas/testsuite/:
* gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
and LOOP_END instruction are local now.
* gas/bfin/flow2.d: Likewise.
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* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
data register in each rule that moves to the data
register.
gas/testsuite/
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
Add check for mismatch of accumulator and data register.
opcodes/
* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
multiply and multiply-accumulate to data register instruction.
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* config/bfin-parse.y (check_macfunc_option): New.
(check_macfuncs): Check option by calling check_macfunc_option.
Fix comparison always true warnings. Both scalar instructions
of vector instruction must share the same mode option. Only allow
option mode at the end of the second instruction of the vector.
(asm_1): Check option by calling check_macfunc_option.
gas/testsuite/:
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
tests for bad options of "multiply and multipy-accumulate to
accumulator" instructions. Add new vector instruction option
mode tests.
* gas/bfin/vector2.s: Add new vector instruction option mode test.
* gas/bfin/vector2.d: Adjust accordingly.
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
instructions.
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From Jie Zhang <jie.zhang@analog.com>
* config/bfin-parse.y (asm_1): Check AREGS in comparison
instructions. And call yyerror () when comparing PREG with
DREG.
gas/testsuite/:
* gas/bfin/expected_comparison_errors.l: New test.
* gas/bfin/expected_comparison_errors.s: New test.
* gas/bfin/bfin.exp: Add expected_comparison_errors.
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* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
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* configure: Regenerate.
config/
* proginstall.m4: New file, with fixed AC_PROG_INSTALL.
bfd/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
bfd/doc/
* Makefile.in: Regenerate.
intl/
* aclocal.m4: Regenerate.
* configure: Likewise.
gas/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
* doc/Makefile.in: Likewise.
ld/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
opcodes/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
binutils/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
* doc/Makefile.in: Likewise.
gprof/
* aclocal.m4: Regenerate.
* configure: Likewise.
* Makefile.in: Likewise.
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* config/tc-hppa.c (is_same_frag): Delete.
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* config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
RELAX_LOOP_END_ADD_NOP.
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* read.c (s_mexit): Warn if attempting to exit a macro when not
inside a macro definition.
* gas/macros/exit.s: New test case.
* gas/macros/macros.exp: Run the new test, expect it to produce an
error result.
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* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
bfd/doc/
* Makefile.in: Regenerate.
binutils/
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
* configure: Regenerate.
gas/
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* configure: Regenerate.
opcodes/
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
* configure: Regenerate.
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gas/
* config/tc-arm.c (arm_cpu_option_table): Add cortex-a9.
* doc/c-arm.texi: Add cortex-a9.
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bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
Tag_VFP_arch values.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
gas/
* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
* doc/c-arm.texi: Document new ARM FPU variants.
gas/testsuite/
* gas/arm/vfpv3-d16-bad.d: New test.
* gas/arm/vfpv3-d16-bad.l: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
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bfd/
* elf32-arm.c (elf32_arm_howto_table_1): Fix bitmasks for MOVW and
MOVT relocations.
(elf32_arm_final_link_relocate): Fix off by one MOVW/MOVT sign
extension.
(elf32_arm_relocate_section): Handle MOVW and MOVT
relocations. Improve safety check for other weird relocations.
(elf32_arm_check_relocs): Only set h->needs_plt for branch/call
relocations.
gas/
* config/tc-arm.c (md_apply_fix): Use correct offset range.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw.
* ld-arm/arm-app-movw.s: New test.
* ld-arm/arm-app.r: Update expected output.
* ld-arm/movw-merge.d: New test.
* ld-arm/movw-merge.s: New test.
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for strict ordering of powerpc_opcodes, but disable for now.
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gas/
* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
(arm_ext_v7m): Rename...
(arm_ext_m): ... to this. Include v6-M.
(do_t_add_sub): Allow narrow low-reg non flag setting adds.
(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
(md_assemble): Allow wide msr instructions.
(insns): Add classifications for v6-m instructions.
(arm_cpu_option_table): Add cortex-m1.
(arm_arch_option_table): Add armv6-m.
(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
gas/testsuite/
* gas/arm/archv6m.d: New test.
* gas/arm/archv6m.s: New test.
* gas/arm/t16-bad.s: Test low register non flag setting add.
* gas/arm/t16-bad.l: Update expected output.
include/opcode/
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
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* xtensa-isa.c (xtensa_isa_num_pipe_stages): Make max_stage static and
only compute its value once.
gas/
* config/tc-xtensa.c (xtensa_num_pipe_stages): New.
(md_begin): Initialize it.
(resources_conflict): Use it.
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* config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
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2008-03-03 Denys Vlasenko <vda.linux@googlemail.com>
H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* read.c (pseudo_set): Don't allow global register symbol.
* symbols.c (S_SET_EXTERNAL): Don't allow register symbol
global.
2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* write.c (write_object_file): Don't allow symbols which were
equated to register. Stop if there is an error.
gas/testsuite/
2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2.
* gas/i386/inval-equ-1.l: New.
* gas/i386/inval-equ-1.s: Likewise.
* gas/i386/inval-equ-2.l: Likewise.
* gas/i386/inval-equ-2.s: Likewise.
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(ppc_cpu): Declare.
(TC_FIX_TYPE, TC_INIT_FIX_DATA): Define.
* config/tc-ppc.c (ppu_cpu): Make global.
(ppc_insert_operand): Add ppu_cpu parameter.
(md_assemble): Adjust for above change.
(md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
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targeted ARM ports, otherwise just skip generating the reloc.
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targeted ARM ports.
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* doc/c-i386.texi: Update -march= and .arch.
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Do not regard weak symbols as having a known location.
(md_estimate_size_before_relax): Use new function.
(md_pcrel_from): Do not compute a pcrel against a weak symbol.
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2008-02-18 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (match_template): Disallow 'l' suffix when
currently selected CPU has no 32-bit support.
(parse_real_register): Do not return registers not available on
currently selected CPU.
gas/testsuite/
2008-02-18 Jan Beulich <jbeulich@novell.com>
* gas/i386/att-regs.s, gas/i386/att-regs.d,
gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
* gas/i386/i386.exp: Run new tests.
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* config/tc-i386.c (process_immext): Fix format.
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2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (inoutportreg): New.
(process_immext): New.
(md_assemble): Use it.
(update_imm): Use imm16 and imm32s.
(i386_att_operand): Use inoutportreg.
opcodes/
2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
* i386-init.h: Regenerated.
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* config/tc-i386.c (operand_type_all_zero): New.
(operand_type_set): Likewise.
(operand_type_equal): Likewise.
(cpu_flags_all_zero): Likewise.
(cpu_flags_set): Likewise.
(cpu_flags_equal): Likewise.
(UINTS_ALL_ZERO): Removed.
(UINTS_SET): Likewise.
(UINTS_CLEAR): Likewise.
(UINTS_EQUAL): Likewise.
(cpu_flags_match): Updated.
(smallest_imm_type): Likewise.
(set_cpu_arch): Likewise.
(md_assemble): Likewise.
(optimize_imm): Likewise.
(match_template): Likewise.
(process_suffix): Likewise.
(update_imm): Likewise.
(process_drex): Likewise.
(process_operands): Likewise.
(build_modrm_byte): Likewise.
(i386_immediate): Likewise.
(i386_displacement): Likewise.
(i386_att_operand): Likewise.
(parse_real_register): Likewise.
(md_parse_option): Likewise.
(i386_target_format): Likewise.
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* config/tc-arm.c (s_arm_unwind_save): Advance the input line
pointer past the comma after parsing a floating point register
name.
* gas/arm/fp-save.s: New test.
* gas/arm/fp-save.d: Expected disassembly.
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* avr.h (AVR_ISA_2xxe): Define.
* config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
to AVR_ISA_2xxe.
(avr_operand): Disallow post-increment addressing in the lpm
instruction for the attiny26.
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2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (parse_real_register): Don't return 'FLAT'
if not in Intel mode.
(i386_intel_operand): Ignore segment overrides in immediate and
offset operands.
(intel_e11): Range-check i.mem_operands before use as array
index. Filter out FLAT for uses other than as segment override.
(intel_get_token): Remove broken promotion of "FLAT:" to mean
"offset FLAT:".
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.s: Replace invalid offset expression with
valid ones.
* gas/i386/x86_64.s: Likewise.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-opc.h (RegFlat): New.
* i386-reg.tbl (flat): Add.
* i386-tbl.h: Re-generate.
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2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Also special-case 'bound'.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
* gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
gas/i386/opcode-intel.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (a_mode): New.
(cond_jump_mode): Adjust.
(Ma): Change to a_mode.
(intel_operand_size): Handle a_mode.
* i386-opc.tbl: Allow Dword and Qword for bound.
* i386-tbl.h: Re-generate.
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2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (allow_pseudo_reg): New.
(parse_real_register): Check for NULL just once. Allow all
register table entries when allow_pseudo_reg is non-zero.
Don't allow any registers without type when allow_pseudo_reg
is zero.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
(tc_x86_frame_initial_instructions): Adjust for above change.
* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
(tc_parse_to_dw2regnum): New.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
error handling.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/cfi/cfi-i386.s: Add code testing use of all registers.
Fix a few comments.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-gen.c (process_i386_registers): Process new fields.
* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
unsigned char. Add dw2_regnum and Dw2Inval.
* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
register names.
* i386-tbl.h: Re-generate.
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argument.
(tic4x_insn_add): Likewise.
(md_begin): Drop cast that was discarding a const qualifier.
* config/tc-d30v.c (get_reloc): Add const qualifier to op
argument.
(build_insn): Drop cast that was discarding a const qualifier.
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2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .xsave.
(md_show_usage): Add .xsave.
* doc/c-i386.texi: Add xsave to -march=.
gas/testsuite/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add xgetbv.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-10.d: Likewise.
opcodes/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
* i386-init.h: Updated.
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* config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
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* config/tc-xtensa.c (relax_frag_immed): Change internal consistency
checks into assertions. When relaxation produces an operation that
does not fit in the current FLIX instruction, make sure that the
operation is relaxed as needed to account for being placed following
the current instruction.
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2008-02-04 Kai Tietz <kai.tietz@onevision.com>
H.J. Lu <hongjiu.lu@intel.com>
PR 5715
* warning.m4: Enable -Wno-format by default when using gcc on
mingw.
* configure: Regenerated.
binutils/
2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
PR 5715
* configure: Regenerated.
gas/
2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
PR 5715
* configure: Regenerated.
ld/
2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
PR 5715
* configure: Regenerated.
opcodes/
2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
PR 5715
* configure: Regenerated.
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