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AgeCommit message (Expand)AuthorFilesLines
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+9
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-0/+8
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-0/+11
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+11
2016-11-15Fix SPARC relocations generated for the .eh_frame section.Nick Clifton1-0/+6
2016-11-13add missing ChangeLog entryAnthony Green1-0/+4
2016-11-11Accept L and LL suffixes to integer constants.Nick Clifton1-0/+9
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-0/+5
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+7
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-0/+5
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy1-0/+7
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-0/+6
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+5
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy1-0/+9
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-0/+12
2016-11-09X86: Update opcode-suffix.dH.J. Lu1-0/+5
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-0/+7
2016-11-04Fix gas crash with unreasonably long linesNathan Sidwell1-0/+11
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess1-0/+7
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+7
2016-11-04Add support for ARM Cortex-M23 processorThomas Preud'homme1-0/+7
2016-11-04Update RISC-V documentation and make sure that it is included in the gas info...Palmer Dabbelt1-0/+11
2016-11-03[ARC] Fix ldbit test on 32-bit systemsGraham Markall1-0/+6
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+5
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-0/+14
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-0/+5
2016-11-03gas/arc: Replace short_insn flag with insn length fieldGraham Markall1-0/+9
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar1-0/+7
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu1-0/+7
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang1-0/+16
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+19
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+28
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+21
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess1-0/+30
2016-10-26Revert "bison warning fixes"Alan Modra1-0/+6
2016-10-21X86: Remove pcommit instructionH.J. Lu1-0/+12
2016-10-20Check invalid mask registersH.J. Lu1-0/+7
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing instr...Renlin Li1-0/+8
2016-10-17Fixed matching in newly added test.Cupertino Miranda1-0/+4
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda1-0/+5
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-0/+7
2016-10-11Enhance objdump so that it will use .got, .plt and .plt.got section symbols w...Nick Clifton1-0/+4
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-0/+5
2016-10-10MIPS64: Adjust cfi* testcases.Andreas Krebbel1-0/+12
2016-10-08Auto-generated dependencies for rx-parse.o and rl78-parse.oAlan Modra1-0/+8
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang1-0/+7
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu1-0/+9
2016-10-06-Wimplicit-fallthrough dodgy fixesAlan Modra1-0/+5
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune1-0/+10
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+48
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