aboutsummaryrefslogtreecommitdiff
path: root/gas/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2020-12-03IBM Z: Add support for HLASM extended mnemonicsAndreas Krebbel1-0/+9
2020-12-01RISC-V: Support to add implicit extensions for G.Nelson Chu1-0/+7
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu1-0/+15
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu1-0/+30
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu1-0/+10
2020-12-01RISC-V: Don't allow any uppercase letter in the arch string.Nelson Chu1-0/+6
2020-12-01RISC-V: Minor cleanup and testcases improvement for arch string parser.Nelson Chu1-0/+67
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-0/+9
2020-11-27ELF: Support .noinit and .persistent sectionsJozef Lawrynowicz1-0/+8
2020-11-25gas output_file_close error messageAlan Modra1-0/+6
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+6
2020-11-19gas/testsuite: Fix SHF_GNU_RETAIN tests for FreeBSD OSABIsJozef Lawrynowicz1-0/+7
2020-11-18Re: Stop Gas from generating line info or address rangesAlan Modra1-0/+12
2020-11-18Support SHF_GNU_RETAIN ELF section flagJozef Lawrynowicz1-0/+23
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus1-0/+8
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+8
2020-11-16arm: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+6
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-0/+38
2020-11-12MSP430: gas: Ignore -md option required for GCC backward compatibilityJozef Lawrynowicz1-0/+9
2020-11-12Fix up changelog entry of previous deltaNick Clifton1-2/+4
2020-11-12Stop Gas from generating line info or address ranges for sections that do not...Nick Clifton1-0/+9
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus1-0/+4
2020-11-09gas: improve reproducibility for stabs debugging data formatDenys Zagorui1-0/+5
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson1-0/+6
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+6
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+8
2020-11-09Fix regexp for development.expAndreas Schwab1-0/+5
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu1-0/+32
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-0/+13
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+9
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+90
2020-11-03gas: fix symbol value calculation for versioned symbol aliasesChristian Eggers1-0/+5
2020-10-30x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE markerH.J. Lu1-0/+22
2020-10-26gas: Clear all auto-assigned file slotsH.J. Lu1-0/+11
2020-10-26Update gas/ChangeLog of last commitLifang Xia1-0/+5
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu1-0/+5
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu1-1/+4
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu1-0/+8
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-0/+6
2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni1-0/+9
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert1-0/+4
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+21
2020-10-17gas: Add a -gdwarf-5 debug_line test with .s fileH.J. Lu1-0/+8
2020-10-17gas: Replace dwarf5-line-2.S with dwarf5-line-3.SH.J. Lu1-0/+8
2020-10-17gas: Always use as_where for preprocessed assembly codesH.J. Lu1-0/+16
2020-10-16gas: Reuse the input file entry in the file tableH.J. Lu1-1/+17
2020-10-16Enhancement for avx-vnni patchCui,Lili1-0/+13
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+14
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+11
2020-10-14x86: Support Intel UINTRLili Cui1-0/+10
generated by cgit v1.1 at 2024-12-16 20:10:55 +0000