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2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2019-01-01ChangeLog rotationAlan Modra1-53/+2
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-0/+4
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-0/+4
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs464e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS464E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs464e to bfd_mach_mips_gs464 extension. binutils/ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support. * readelf.c (get_machine_flags): Handle gs464e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs464e and gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-0/+5
bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-0/+4
bfd/ * elfxx-mips.c (infer_mips_abiflags): Use ases instead of isa_ext for infer ABI flags. (print_mips_ases): Add Loongson EXT extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT extension. elfcpp/ * mips.h (AFL_ASE_LOONGSON_EXT): New enum. gas/ * NEWS: Mention Loongson EXTensions (EXT) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and OPTION_NO_LOONGSON_EXT. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to AFL_ASE_LOONGSON_EXT. (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a. (md_show_usage): Add help for -mloongson-ext and -mno-loongson-ext. * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext. * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext, .set loongson-ext and .set noloongson-ext. * testsuite/gas/mips/loongson-mmi.d: Add ASE flag. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT. * opcode/mips.h (ASE_LOONGSON_EXT): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (IL3A): Delete. * mips-opc.c (LEXT): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT instructions.
2018-07-06[GOLD] PowerPC .gnu.attributes supportAlan Modra1-0/+5
elfcpp/ * powerpc.h (Tag_GNU_Power_ABI_FP): Define. (Tag_GNU_Power_ABI_Vector, Tag_GNU_Power_ABI_Struct_Return): Define. gold/ * powerpc.cc: Include attributes.h. (Powerpc_relobj::attributes_section_data_): New variable, with accessor and associated constructor and destructor support. (Powerpc_dynobj::attributes_section_data_): Likewise. (Powerpc_relobj::do_read_symbols): Stash SHT_GNU_ATTRIBUTES section contents in attributes_section_data_. (Powerpc_dynobj::do_read_symbols): Likewise. (Target_powerpc): Add attributes_section_data_, last_fp_, last_ld_, last_vec_, and last_struct_ vars. (Target_powerpc::merge_object_attributes): New function. (Target_powerpc::do_finalize_sections): Iterate over input objects merging attributes. Create output attributes section.
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+4
2018-06-22Add support for .note.gnu.property sections.Cary Coutant1-0/+8
elfcpp/ PR gold/22914 * elfcpp.h (NT_GNU_PROPERTY_TYPE_0): New note type. (GNU_PROPERTY_*): New Gnu property types. * x86_64.h (GNU_PROPERTY_X86_FEATURE_1_IBT) (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New x86 feature bits. gold/ PR gold/22914 * layout.cc (Layout::Layout): Initialize gnu_properties_. (read_sized_value, write_sized_value): New functions. (Layout::layout_gnu_property): New method. (Layout::create_notes): Call create_gnu_properties_note. (Layout::create_gnu_properties_note): New method. * layout.h (Layout::layout_gnu_property): New method. (Layout::create_gnu_properties_note): New method. (Layout::Gnu_property, Layout::Gnu_properties): New types. (Layout::gnu_properties_): New data member. * object.cc (Sized_relobj_file::layout_gnu_property_section): New method. (Sized_relobj_file::do_layout): Handle .note.gnu.property sections. * object.h (Sized_relobj_file::layout_gnu_property_section): New method. * target.h (Target::merge_gnu_property): New method. (Target::do_merge_gnu_property): New virtual method. * x86_64.cc (Target_x86_64::do_merge_gnu_property): New method. * testsuite/Makefile.am (gnu_property_test): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/gnu_property_a.S: New source file. * testsuite/gnu_property_b.S: New source file. * testsuite/gnu_property_c.S: New source file. * testsuite/gnu_property_main.c: New source file. * testsuite/gnu_property_test.sh: New test script.
2018-04-09PowerPC inline PLT call supportAlan Modra1-0/+4
In addition to the existing relocs we need two more to mark all instructions in the call sequence, PLTCALL on the call itself (plus the toc restore insn for ppc64), and PLTSEQ on others. All relocations in a particular sequence have the same symbol. Example ppc64 ELFv2 assembly: .reloc .,R_PPC64_PLTSEQ,puts std 2,24(1) addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts .reloc .,R_PPC64_PLTSEQ,puts mtctr 12 .reloc .,R_PPC64_PLTCALL,puts bctrl ld 2,24(1) Example ppc32 -fPIC assembly: addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000 lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000 .reloc .,R_PPC_PLTSEQ,puts+32768 mtctr 12 .reloc .,R_PPC_PLTCALL,puts+32768 bctrl Marking sequences like this allows the linker to convert them to nops and a direct call if the target symbol turns out to be local. When the call is __tls_get_addr, each relocation shown above is paired with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the sequence for possible TLS optimization. The TLSLD or TLSGD relocs are emitted first. include/ * elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define. * elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos. (is_plt_seq_reloc): New function. (ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs. (ppc_elf_tls_optimize): Handle inline plt call sequence. (ppc_elf_relax_section): Handle PLTCALL reloc. (ppc_elf_relocate_section): Nop out inline plt call sequence when resolving locally. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE. (has_tls_get_addr_call): Correct comment. (is_branch_reloc): Add PLTCALL. (is_plt_seq_reloc): New function. (ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt entry for R_PPC64_PLTCALL. (ppc64_elf_tls_optimize): Handle inline plt call sequence. (ppc_type_of_stub): Handle PLTCALL reloc. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL reloc insn. Nop out inline plt call sequence when resolving locally. Handle __tls_get_addr inline plt call optimization. elfcpp/ * powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define. gold/ * powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call): Handle inline plt sequence relocs. (Stub_table::Plt_stub_key::Plt_stub_key): Likewise. (Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise. (Target_powerpc::Relocate::relocate): Likewise.
2018-03-28Add support for R_AARCH64_TLSLE_LDST8_TPREL_LO12, etc.Cary Coutant1-0/+5
elfcpp/ PR gold/22969 * aarch64.h: Fix spelling of R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC. gold/ PR gold/22969 * aarch64-reloc.def: Add TLSLE_LDST* relocations. * aarch64.cc (Target_aarch64::optimize_tls_reloc): Likewise. (Target_aarch64::Scan::local): Likewise. (Target_aarch64::Scan::global): Likewise. (Target_aarch64::Relocate::relocate): Likewise. (Target_aarch64::Relocate::relocate_tls): Likewise.
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2018-01-03ChangeLog rotationAlan Modra1-37/+2
2017-09-21oops - changelog entry omitted from previous deltaNick Clifton1-0/+4
2017-08-29[GOLD] PowerPC tls_get_addr_optimizeAlan Modra1-0/+5
This implements the special __tls_get_addr_opt call stub for powerpc gold that returns __thread variable addresses without actually making a call to __tls_get_addr in most cases. Shared libraries that are loaded at program load time (ie. dlopen is not used) have a known layout for their __thread variables, and thus DTPMOD64/DPTREL64 pairs describing those variables can be set up by ld.so for the __tls_get_addr_opt call stub fast exit. Ref https://sourceware.org/ml/libc-alpha/2015-03/msg00626.html I really, really wish I'd used a differently versioned __tls_get_addr symbol than the base symbol to indicate glibc support for the optimized call, rather than having glibc export __tls_get_addr_opt. A lot of the messing around here, flipping symbols from __tls_get_addr to __tls_get_addr_opt, is caused by that decision. About the only benefit is that a user can see at a glance that their disassembled code is calling __tls_get_addr via the fancy call stub.. Anyway, we need references to __tls_get_addr to seem like they were to __tls_get_addr_opt, and in cases like the tsan interceptor, a definition of __tls_get_addr to seem like one of __tls_get_addr_opt as well. That's the reason for Symbol::clear_in_reg and Symbol_table::clone, and why symbols are substituted in Scan::global and other places dealing with dynamic linking. elfcpp/ * elfcpp.h (DT_PPC_OPT): Define. * powerpc.h (PPC_OPT_TLS): Define. gold/ * options.h (tls_get_addr_optimize): New option. * symtab.h (Symbol::clear_in_reg, clone): New functions. (Sized_symbol::clone): New function. (Symbol_table::clone): New function. * resolve.cc (Symbol::clone, Sized_symbol::clone): New functions. * powerpc.cc (Target_powerpc::has_tls_get_addr_opt_, tls_get_addr_, tls_get_addr_opt_): New vars. (Target_powerpc::tls_get_addr_opt, tls_get_addr, is_tls_get_addr_opt, replace_tls_get_addr, set_has_tls_get_addr_opt, stk_linker): New functions. (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call): Add target param. Update callers. Compare symbols rather than names. (Target_powerpc::do_define_standard_symbols): Init tls_get_addr_ and tls_get_addr_opt_. (Target_powerpc::Branch_info::mark_pltcall): Translate tls_get_addr sym to tls_get_addr_opt. (Target_powerpc::Branch_info::make_stub): Likewise. (Stub_table::define_stub_syms): Likewise. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. (add_3_12_2, add_3_12_13, bctrl, beqlr, cmpdi_11_0, cmpwi_11_0, ld_11_1, ld_11_3, ld_12_3, lwz_11_3, lwz_12_3, mr_0_3, mr_3_0, mtlr_11, std_11_1): New constants. (Stub_table::eh_frame_added_): Delete. (Stub_table::tls_get_addr_opt_bctrl_, plt_fde_len_, plt_fde_): New vars. (Stub_table::init_plt_fde): New functions. (Stub_table::add_eh_frame, replace_eh_frame): Move definition out of line. Init and use plt_fde_. (Stub_table::plt_call_size): Return size for tls_get_addr stub. Extract alignment code to.. (Stub_table::plt_call_align): ..this new function. Adjust all callers. (Stub_table::add_plt_call_entry): Set has_tls_get_addr_opt and tls_get_addr_opt_bctrl, and align after that. (Stub_table::do_write): Write out tls_get_addr stub. (Target_powerpc::do_finalize_sections): Emit DT_PPC_OPT PPC_OPT_TLS/PPC64_OPT_TLS bit. (Target_powerpc::Relocate::relocate): Don't check for or modify nop following bl for tls_get_addr stub.
2017-07-28gold: Add put_ch_reserved to 64-bit Chdr_writeH.J. Lu1-0/+7
The 64-bit ELF compression header has a reserved field. It should be cleared to avoid random bits in it. elfcpp/ PR gold/21857 * elfcpp.h (Chdr_write): Add put_ch_reserved. (Chdr_write<64, true>::put_ch_reserved): New. (Chdr_write<64, false>::put_ch_reserved): Likewise. gold/ PR gold/21857 * compressed_output.cc (Output_compressed_section::set_final_data_size): Call put_ch_reserved to clear the reserved field for 64-bit ELF.
2017-07-03[GOLD] undef after using DW_IDX and friendsAlan Modra1-1/+2
* dwarf.h (DW_FIRST_IDX, DW_IDX, DW_IDX_DUP, DW_END_IDX): Undef after using.
2017-07-03Repair include/dwarf2.def breakageAlan Modra1-0/+4
* dwarf.h (DW_FIRST_IDX, DW_IDX, DW_IDX_DUP, DW_END_IDX): Define.
2017-06-26Add pgste marker changelogAndreas Krebbel1-0/+4
2017-06-23[GOLD] PowerPC64 localentry:0 plt call optimizationAlan Modra1-0/+6
elfcpp/ * elfcpp.h (DT_PPC64_OPT): Define. * powerpc.h (PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC, PPC64_OPT_LOCALENTRY): Define. gold/ * options.h (General_options): Add plt_localentry. * powerpc.cc (Target_powerpc::st_other): New function. (Target_powerpc::plt_localentry0_, plt_localentry0_init_, has_localentry0_): New vars. (Target_powerpc::plt_localentry0, set_has_localentry0, is_elfv2_localentry0): New functions. (Target_powerpc::Branch_info::mark_pltcall): Don't set tocsave or return true for localentry:0 calls. (Stub_table::Plt_stub_ent::localentry0_): New var. (Stub_table::add_plt_call_entry): Set localentry0_ and has_localentry0_. Don't set r2save_ for localentry:0 calls. (Output_data_glink::do_write): Save r2 in __glink_PLTresolve for elfv2. (Target_powerpc::scan_relocs): Default plt_localentry0_. (Target_powerpc::do_finalize_sections): Set DT_PPC64_OPT. (Target_powerpc::Relocate::relocate): Don't require nop following calls for localentry:0 plt calls, and don't change nop.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-63/+2
2016-12-31Add PRU ELF ID to elfcppDimitar Dimitrov1-0/+4
* elfcpp.h (enum EM): Add EM_TI_PRU. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-06-20Add support for MIPS .rld_map section.Vladimir Radosavljevic1-0/+4
Includes DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags and __RLD_MAP symbol. 2016-06-20 Vladimir Radosavljevic <Vladimir.Radosavljevic@imgtec.com> elfcpp/ * elfcpp.h (DT_MIPS_RLD_MAP_REL): New enum constant. gold/ * mips.cc (Target_mips::Target_mips): Initialize rld_map_. (Target_mips::rld_map_): New data member. (Target_mips::do_finalize_sections): Add support for DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags, .rld_map section, and __RLD_MAP symbol. (Target_mips::do_dynamic_tag_custom_value): Add support for DT_MIPS_RLD_MAP_REL dynamic tag. * output.cc (Output_data_dynamic::get_entry_offset): New method definition. * output.h (Output_data_dynamic::get_entry_offset): New method declaration.
2016-06-20Add support for Mips32r6 and Mips64r6.Vladimir Radosavljevic1-0/+7
elfcpp/ * mips.h (R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16, R_MIPS_PCLO16): New enums for Mips32r6 and Mips64r6 relocations. (r6_isa): New function. gold/ * mips.cc (relocation_needs_la25_stub): Add support for relocs: R_MIPS_PC21_S2 and R_MIPS_PC26_S2. (hi16_reloc): Add support for R_MIPS_PCHI16 relocation. (is_matching_lo16_reloc): Likewise. (lo16_reloc): Add support for R_MIPS_PCLO16 relocation. (Mips_output_data_plt::plt_entry_r6): New static data member for R6 PLT entry. (Target_mips::is_output_r6): New method. (Target_mips::Mips_mach): Add new enum constants. (Mips_relocate_functions::Status): Likewise. (Mips_relocate_functions::pchi16_relocs): New static data member. (Mips_relocate_functions::relpc21): New method. (Mips_relocate_functions::relpc26): Likewise. (Mips_relocate_functions::relpc18): Likewise. (Mips_relocate_functions::relpc19): Likewise. (Mips_relocate_functions::relpchi16): Likewise. (Mips_relocate_functions::do_relpchi16): Likewise. (Mips_relocate_functions::relpclo16): Likewise. (Mips_output_data_plt::do_write): Add support for Mips r6 plt entry. (Target_mips::mips_32bit_flags): Add E_MIPS_ARCH_32R6 support. (Target_mips::elf_mips_mach): Add E_MIPS_ARCH_32R6 and E_MIPS_ARCH_64R6 support. (Target_mips::update_abiflags_isa): Likewise. (mips_get_size_for_reloc): Add support for relocs: R_MIPS_PCHI16, R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3 and R_MIPS_PC19_S2. (Target_mips::Scan::local): Add support for relocs: R_MIPS_PCHI16 and R_MIPS_PCLO16. (Target_mips::Scan::global): Add support for relocs: R_MIPS_PC21_S2 and R_MIPS_PC26_S2. (Target_mips::Relocate::relocate): Call functions for resolving Mips32r6 and Mips64r6 relocations, and print error message for STATUS_PCREL_UNALIGNED. (Target_mips::Scan::get_reference_flags): Add support for relocs: R_MIPS_PCHI16, R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3 and R_MIPS_PC19_S2. (Target_mips::elf_mips_mach_name): Add E_MIPS_ARCH_32R6 and E_MIPS_ARCH_64R6 support.
2016-06-11Add support for .MIPS.abiflags and .gnu.attributes sections.Vladimir Radosavljevic1-0/+27
elfcpp/ * elfcpp.h (SHT_MIPS_ABIFLAGS): New enum constant. * mips.h (EF_MIPS_FP64, EF_MIPS_NAN2008): New enum constants for processor-specific flags. (E_MIPS_MACH_5900): New enum constant for machine variant. (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): New enum constants. (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU, AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS, AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16, AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP, AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900, AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900, AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120, AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E, AFL_EXT_LOONGSON_2F, AFL_EXT_OCTEON3): Likewise. (Tag_GNU_MIPS_ABI_FP, Tag_GNU_MIPS_ABI_MSA): Likewise. (Val_GNU_MIPS_ABI_FP_ANY, Val_GNU_MIPS_ABI_FP_DOUBLE, Val_GNU_MIPS_ABI_FP_SINGLE, Val_GNU_MIPS_ABI_FP_SOFT, Val_GNU_MIPS_ABI_FP_OLD_64,Val_GNU_MIPS_ABI_FP_XX, Val_GNU_MIPS_ABI_FP_64, Val_GNU_MIPS_ABI_FP_64A, Val_GNU_MIPS_ABI_FP_NAN2008, Val_GNU_MIPS_ABI_MSA_ANY, Val_GNU_MIPS_ABI_MSA_128): Likewise. (AFL_FLAGS1_ODDSPREG): New enum constant. gold/ * mips.cc (struct Mips_abiflags): New struct. (Mips_relobj::Mips_relobj): Initialize attributes_section_data_ and abiflags_. (Mips_relobj::~Mips_relobj): Delete object pointed by attributes_section_data_. (Mips_relobj::abiflags): New method. (Mips_relobj::attributes_section_data): Likewise. (Mips_relobj::attributes_section_data_): New data member. (Mips_relobj::abiflags_): Likewise. (class Mips_output_section_abiflags): New class. (Target_mips::Target_mips): Initialize attributes_section_data_, abiflags_ and has_abiflags_section_. (Target_mips::do_should_include_section): Don't emit input .MIPS.abiflags sections to output .MIPS.abiflags. (Target_mips::Mips_mach): Add new enum constants. (Target_mips::mips_isa_ext_mach): New method. (Target_mips::mips_isa_ext): Likewise. (Target_mips::update_abiflags_isa): Likewise. (Target_mips::infer_abiflags): Likewise. (Target_mips::create_abiflags): Likewise. (Target_mips::fp_abi_string): Likewise. (Target_mips::select_fp_abi): Likewise. (Target_mips::merge_obj_attributes): Likewise. (Target_mips::merge_obj_abiflags): Likewise. (Target_mips::level_rev): Likewise. (Target_mips::merge_obj_e_flags): Rename from merge_processor_specific_flags. Remove dyn_obj argument, call update_abiflags_isa when needed, compare NaN encodings and compare FP64 state. (Target_mips::add_machine_extensions): Add two machine extensions and fix one. (Target_mips::attributes_section_data_): New data member. (Target_mips::abiflags_): Likewise. (Target_mips::has_abiflags_section_): Likewise. (Mips_relobj::do_read_symbols): Read .gnu.attributes and .MIPS.abiflags sections if they exists. (Target_mips::elf_mips_mach): Add E_MIPS_MACH_5900 and E_MIPS_MACH_OCTEON3 support. (Target_mips::do_adjust_elf_header): Setup EI_ABIVERSION flag. (Target_mips::do_finalize_sections): Merge .gnu.attributes and .MIPS.abiflags sections from input. Create these sections if needed. (Target_mips::elf_mips_mach_name): Add E_MIPS_MACH_5900 and E_MIPS_MACH_OCTEON3 support, and change strings for E_MIPS_MACH_LS2E, E_MIPS_MACH_LS2F and E_MIPS_MACH_LS3A just to match bfd.
2016-03-18Remove is_n64_ data member from Mips_relobj class.Vladimir Radosavljevic1-0/+4
elfcpp/ * mips.h (abi_64): Remove. gold/ * mips.cc (Mips_relobj::is_n64_): Remove. (Target_mips::ei_class_): Likewise. (Mips_relobj::is_newabi): Call methods. (Mips_relobj::is_n64): Change checking for N64 ABI. (Target_mips::is_output_n64): Likewise. (Target_mips::merge_processor_specific_flags): Remove ei_class argument, and remove comparing ei_class. (Target_mips::do_adjust_elf_header): Remove setting EI_CLASS field of the ELF header. (Target_mips::do_finalize_sections): Don't pass ei_class argument to merge_processor_specific_flags. (Target_mips::elf_mips_abi_name): Remove ei_class argument, and change checking for N64 ABI.
2016-01-12Fix compile error with use of 'typename' outside of template.H.J. Lu1-0/+5
elfcpp/ * elfcpp_internal.h (Mips64_rel_data, Mips64_rela_data): Remove 'typename'.
2016-01-11Refactor gold to enable support for MIPS-64 relocation format.Cary Coutant1-0/+6
For MIPS-64, the r_info field in the relocation format is replaced by several individual fields, including r_sym and r_type. To enable support for this format, I've refactored target-independent code to remove almost all uses of the r_info field. (I've left alone a couple of routines used only for incremental linking, which I can update if/when the MIPS target adds support for incremental linking.) For routines that are already templated on a Classify_reloc class (namely, gc_process_relocs, relocate_section, and relocate_relocs), I've extended the Classify_reloc interface to include sh_type (which no longer needs to be a separate template parameter) as well as get_r_sym() and get_r_type() methods for extracting the r_sym and r_type fields. For scan_relocatable_relocs, I've extended the Default_scan_relocatable_relocs class by converting it to a class template with Classify_reloc as a template parameter. For the remaining routines that need to access r_sym, I've added a virtual Target::get_r_sym() method with an override for the MIPS target. In elfcpp, I've added Mips64_rel, etc., accessor classes and corresponding internal data structures. The MIPS target uses these new classes within its own Mips_classify_reloc class. The Mips64_ accessor classes also expose the r_ssym, r_type2, and r_type3 fields from the relocation. These changes should be functionally the same for all but the MIPS target. elfcpp/ * elfcpp.h (Mips64_rel, Mips64_rel_write): New classes. (Mips64_rela, Mips64_rela_write): New classes. * elfcpp_internal.h (Mips64_rel_data, Mips64_rela_data): New structs. gold/ * gc.h (get_embedded_addend_size): Remove sh_type parameter. (gc_process_relocs): Remove sh_type template parameter. Use Classify_reloc to access r_sym, r_type, and r_addend fields. * object.h (Sized_relobj_file::split_stack_adjust): Add target parameter. (Sized_relobj_file::split_stack_adjust_reltype): Likewise. * reloc-types.h (Reloc_types::copy_reloc_addend): (SHT_REL and SHT_RELA specializations) Remove. * reloc.cc (Emit_relocs_strategy): Rename and move to target-reloc.h. (Sized_relobj_file::emit_relocs_scan): Call Target::emit_relocs_scan(). (Sized_relobj_file::emit_relocs_scan_reltype): Remove. (Sized_relobj_file::split_stack_adjust): Add target parameter. Adjust all callers. (Sized_relobj_file::split_stack_adjust_reltype): Likewise. Call Target::get_r_sym() to get r_sym field from relocations. (Track_relocs::next_symndx): Call Target::get_r_sym(). * target-reloc.h (scan_relocs): Remove sh_type template parameter; add Classify_reloc template parameter. Use for accessing r_sym and r_type. (relocate_section): Likewise. (Default_classify_reloc): New class (renamed and moved from reloc.cc). (Default_scan_relocatable_relocs): Remove sh_type template parameter. (Default_scan_relocatable_relocs::Reltype): New typedef. (Default_scan_relocatable_relocs::reloc_size): New const. (Default_scan_relocatable_relocs::sh_type): New const. (Default_scan_relocatable_relocs::get_r_sym): New method. (Default_scan_relocatable_relocs::get_r_type): New method. (Default_emit_relocs_strategy): New class. (scan_relocatable_relocs): Replace sh_type template parameter with Scan_relocatable_relocs class. Use it to access r_sym and r_type fields. (relocate_relocs): Replace sh_type template parameter with Classify_reloc class. Use it to access r_sym and r_type fields. * target.h (Target::is_call_to_non_split): Replace r_type parameter with pointer to relocation. Adjust all callers. (Target::do_is_call_to_non_split): Likewise. (Target::emit_relocs_scan): New virtual method. (Sized_target::get_r_sym): New virtual method. * target.cc (Target::do_is_call_to_non_split): Replace r_type parameter with pointer to relocation. * aarch64.cc (Target_aarch64::emit_relocs_scan): New method. (Target_aarch64::Relocatable_size_for_reloc): Remove. (Target_aarch64::gc_process_relocs): Use Default_classify_reloc. (Target_aarch64::scan_relocs): Likewise. (Target_aarch64::relocate_section): Likewise. (Target_aarch64::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_aarch64::scan_relocatable_relocs): Use Default_classify_reloc. (Target_aarch64::relocate_relocs): Use Default_classify_reloc. * arm.cc (Target_arm::Arm_scan_relocatable_relocs): Remove sh_type template parameter. (Target_arm::emit_relocs_scan): New method. (Target_arm::Relocatable_size_for_reloc): Replace with... (Target_arm::Classify_reloc): ...this. (Target_arm::gc_process_relocs): Use Classify_reloc. (Target_arm::scan_relocs): Likewise. (Target_arm::relocate_section): Likewise. (Target_arm::scan_relocatable_relocs): Likewise. (Target_arm::relocate_relocs): Likewise. * i386.cc (Target_i386::emit_relocs_scan): New method. (Target_i386::Relocatable_size_for_reloc): Replace with... (Target_i386::Classify_reloc): ...this. (Target_i386::gc_process_relocs): Use Classify_reloc. (Target_i386::scan_relocs): Likewise. (Target_i386::relocate_section): Likewise. (Target_i386::scan_relocatable_relocs): Likewise. (Target_i386::relocate_relocs): Likewise. * mips.cc (Mips_scan_relocatable_relocs): Remove sh_type template parameter. (Mips_reloc_types): New class template. (Mips_classify_reloc): New class template. (Target_mips::Reltype): New typedef. (Target_mips::Relatype): New typedef. (Target_mips::emit_relocs_scan): New method. (Target_mips::get_r_sym): New method. (Target_mips::Relocatable_size_for_reloc): Replace with Mips_classify_reloc. (Target_mips::copy_reloc): Use Mips_classify_reloc. (Target_mips::gc_process_relocs): Likewise. (Target_mips::scan_relocs): Likewise. (Target_mips::relocate_section): Likewise. (Target_mips::scan_relocatable_relocs): Likewise. (Target_mips::relocate_relocs): Likewise. (mips_get_size_for_reloc): New function, factored out from Relocatable_size_for_reloc::get_size_for_reloc. (Target_mips::Scan::local): Use Mips_classify_reloc. (Target_mips::Scan::global): Likewise. (Target_mips::Relocate::relocate): Likewise. * powerpc.cc (Target_powerpc::emit_relocs_scan): New method. (Target_powerpc::Relocatable_size_for_reloc): Remove. (Target_powerpc::gc_process_relocs): Use Default_classify_reloc. (Target_powerpc::scan_relocs): Likewise. (Target_powerpc::relocate_section): Likewise. (Powerpc_scan_relocatable_reloc): Convert to class template. (Powerpc_scan_relocatable_reloc::Reltype): New typedef. (Powerpc_scan_relocatable_reloc::reloc_size): New const. (Powerpc_scan_relocatable_reloc::sh_type): New const. (Powerpc_scan_relocatable_reloc::get_r_sym): New method. (Powerpc_scan_relocatable_reloc::get_r_type): New method. (Target_powerpc::scan_relocatable_relocs): Use Powerpc_scan_relocatable_reloc. (Target_powerpc::relocate_relocs): Use Default_classify_reloc. * s390.cc (Target_s390::emit_relocs_scan): New method. (Target_s390::Relocatable_size_for_reloc): Remove. (Target_s390::gc_process_relocs): Use Default_classify_reloc. (Target_s390::scan_relocs): Likewise. (Target_s390::relocate_section): Likewise. (Target_s390::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_s390::scan_relocatable_relocs): Use Default_classify_reloc. (Target_s390::relocate_relocs): Use Default_classify_reloc. * sparc.cc (Target_sparc::emit_relocs_scan): New method. (Target_sparc::Relocatable_size_for_reloc): Remove. (Target_sparc::gc_process_relocs): Use Default_classify_reloc. (Target_sparc::scan_relocs): Likewise. (Target_sparc::relocate_section): Likewise. (Target_sparc::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_sparc::scan_relocatable_relocs): Use Default_classify_reloc. (Target_sparc::relocate_relocs): Use Default_classify_reloc. * tilegx.cc (Target_tilegx::emit_relocs_scan): New method. (Target_tilegx::Relocatable_size_for_reloc): Remove. (Target_tilegx::gc_process_relocs): Use Default_classify_reloc. (Target_tilegx::scan_relocs): Likewise. (Target_tilegx::relocate_section): Likewise. (Target_tilegx::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_tilegx::scan_relocatable_relocs): Use Default_classify_reloc. (Target_tilegx::relocate_relocs): Use Default_classify_reloc. * x86_64.cc (Target_x86_64::emit_relocs_scan): New method. (Target_x86_64::Relocatable_size_for_reloc): Remove. (Target_x86_64::gc_process_relocs): Use Default_classify_reloc. (Target_x86_64::scan_relocs): Likewise. (Target_x86_64::relocate_section): Likewise. (Target_x86_64::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_x86_64::scan_relocatable_relocs): Use Default_classify_reloc. (Target_x86_64::relocate_relocs): Use Default_classify_reloc. * testsuite/testfile.cc (Target_test::emit_relocs_scan): New method.
2016-01-01Copyright update for binutilsAlan Modra1-0/+4
2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+14
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01binutils ChangeLog rotationAlan Modra1-467/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra1-2/+2
2015-12-07[GOLD] R_PPC64_ENTRY supportAlan Modra1-0/+4
elfcpp/ * powerpc.h (R_PPC64_ENTRY): Define. gold/ * powerpc.cc (add_2_2_12, ld_2_12, lis_2): Define. (Target_powerpc::Scan::local, global): Handle R_PPC64_ENTRY. (Target_powerpc::Relocate::relocate): Edit code at R_PPC64_ENTRY.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-0/+5
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-10-28Add s390 backend.Marcin Kościelnicki1-0/+4
elfcpp/ * s390.h: New file. gold/ * s390.cc: New file. * Makefile.am (TARGETSOURCES): Add s390.cc. (ALL_TARGETOBJS): Add s390.o. * Makefile.in: Regenerate. * configure.ac: Add s390 support. * configure: Regenerate. * configure.tgt: Add s390-*-* and s390x-*-*. * testsuite/icf_safe_test.sh (arch_specific_safe_fold): Add s390 support.
2015-10-22Gold: Don't fail on R_X86_64_[REX_]GOTPCRELX relocationsH.J. Lu1-0/+5
This patch updates gold to treat the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 the same as R_X86_64_GOTPCREL. FIXME: Gold should perform the transformations as suggested. elfcpp/ * x86_64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. gold/ * x86_64.cc (Target_x86_64<size>::Scan::get_reference_flags): Treat R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX the same as R_X86_64_GOTPCREL. (Target_x86_64<size>::Scan::local): Likewise. (Target_x86_64<size>::Scan::possible_function_pointer_reloc): Likewise. (Target_x86_64<size>::Scan::global): Likewise. (Target_x86_64<size>::Relocate::relocate): Likewise. (Target_x86_64<size>::Relocatable_size_for_reloc::get_size_for_reloc): Likewise.
2015-10-22Gold: Don't fail on R_386_GOT32X relocationH.J. Lu1-0/+4
This patch updates gold to treat the R_386_GOT32X relocation proposed in https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I the same as R_386_GOT32. FIXME: Gold should perform the transformations as suggested. elfcpp/ * i386.h (R_386_GOT32X): New. gold/ * i386.cc (Target_i386::Scan::get_reference_flags(): Treat R_386_GOT32X the same as R_386_GOT32. (Target_i386::Scan::local): Likewise. (Target_i386::Scan::possible_function_pointer_reloc): Likewise. (Target_i386::Scan::global): Likewise. (Target_i386::Relocate::relocate): Likewise. (Target_i386::Relocatable_size_for_reloc::get_size_for_reloc): Likewise.
2015-10-13Add EM_IAMCU support to goldH.J. Lu1-0/+5
elfcpp/ PR gold/19118 * elfcpp.h (EM): Add EM_IAMCU. gold/ PR gold/19118 * i386.cc (Target_iamcu): New class. (Target_selector_iamcu): Likewise. (Target_iamcu::iamcu_info): New variable. (target_selector_iamcu): Likewise.
2015-10-04Change ch_type to Elf_Word in struct Chdr_data<64>H.J. Lu1-0/+7
The ch_type field in struct Chdr_data<64> is 4 bytes, followed by a 4-byte padding. This change doesn't introduce any functional change since only the lower 32 bits of the ch_type field are used. PR gold/19060 * elfcpp.h (Chdr::get_ch_type): Change return type to Elf_Word. * elfcpp_internal.h (Chdr_data<64>): Change ch_type to 4 bytes and add ch_reserved.
2015-04-08Add chdr_size, Chdr, Chdr_write and Chdr_dataH.J. Lu1-0/+7
* elfcpp.h (Elf_sizes): Add chdr_size. (Chdr): New. (Chdr_write): Likewise. * elfcpp_internal.h (Chdr_data): Likewise.
2015-04-08Add SHF_COMPRESSED and ELFCOMPRESS_XXX to elfcpp.hH.J. Lu1-0/+9
* elfcpp.h (SHF): Add SHF_COMPRESSED. (ELFCOMPRESS_ZLIB): New. (ELFCOMPRESS_LOOS): Likewise. (ELFCOMPRESS_HIOS): Likewise. (ELFCOMPRESS_LOPROC): Likewise. (ELFCOMPRESS_HIPROC): Likewise.
2015-04-07Add AArch32 support for arm gold linker.Han Shen1-0/+4
2015-02-17[gold] Recognize DWARF5/GCC5 DW_LANG_Fortran03 and DW_LANG_Fortran08.Mark Wielaard1-0/+6
DWARFv5 defines and GCC5 may output two new DW_LANG constants for the Fortran 2003 and Fortran 2008 standards. Recognize both in gold gdb-index as unsupported. For consistency also add the other new DWARF5/GCC5 language constants in the elfcpp::DW_LANG enum to match include/dwarf2.h. elfcpp/ChangeLog: * dwarf.h (enum DW_LANG): Add DW_LANG_C_plus_plus_11, DW_LANG_C11, DW_LANG_C_plus_plus_14, DW_LANG_Fortran03 and DW_LANG_Fortran08 from ../include/dwarf2.h. gold/ChangeLog: * gdb-index.cc (Gdb_index_info_reader::visit_top_die): Recognize DW_LANG_Fortran03 and DW_LANG_Fortran08.
2015-01-29This patch adds IFUNC support for arm gold backend.Han Shen1-0/+4
This is a feature required in chromeos arm development work. Tested: 1) Built passed all-gold on x86_64 machine 2) Tested with basic gold aarch64 ifunc unittests - a) global ifunc, statically/non-statically linked b) local ifunc, statically/non-statically linked c) global/local, other shared library routine mixed, statically/non-statically linked d) arm/thumb mode ifunc e) linking chrome browser passed
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+5
2014-12-25ARM: Add support for value 3 of Tag_ABI_VFP_args attributeAlan Modra1-0/+4
Missing from 5c294fee elfcpp/ * arm.h: Add enums for Tag_ABI_FP_number_model and Tag_ABI_VFP_args. gold/ * arm.cc (Target_arm::do_adjust_elf_header): Provide namespace on new enums. (Target_arm::merge_object_attributes, ): Likewise.
2014-09-17Add tls support to gold aarch64 backend.Jing Yu1-0/+5
elfcpp/ChangeLog: 2014-09-17 Han Shen <shenhan@google.com> * aarch64.h (R_AARCH64_TLS_DTPREL64): Switch enum value with ... (R_AARCH64_TLS_DTPMOD64): ... enum value. gold/ChangeLog: 2014-09-17 Han Shen <shenhan@google.com> Jing Yu <jingyu@google.com> * aarch64-reloc.def: Add TLSGD_ADR_PAGE21, TLSGD_ADD_LO12_NC, TLSDESC_ADR_PAGE21, TLSDESC_LD64_LO12, TLSDESC_ADD_LO12, TLSDESC_CALL. * aarch64.cc (Target_aarch64): Add data members got_irelative_, got_tlsdesc_, rela_irelative_, got_mod_index_offset_, tlsdesc_reloc_info_, tls_base_symbol_defined_. Initialize them in constructor. (Target_aarch64::do_reloc_symbol_index): New method. (Target_aarch64::do_reloc_addend): New method. (Target_aarch64::add_tlsdesc_info): New method. (Target_aarch64::do_dynsym_value): New method. (Target_aarch64::do_make_data_plt): Add new parameters: got, got_irelative. Pass them to Output_data_plt_aarch64_standard. (Target_aarch64::make_data_plt): Add new parameters: got, got_irelative. Pass them to do_make_data_plt. (Target_aarch64::Relocate): Add skip_call_tls_get_addr_ variable. (Target_aarch64::Relocate:tls_gd_to_le): New method. (Target_aarch64::Relocate:tls_ie_to_le): New method. (Target_aarch64::Relocate:tls_desc_gd_to_le): New method. (Target_aarch64::Relocate:tls_desc_gd_to_ie): New method. (Target_aarch64::got_tlsdesc_section): New method. (Target_aarch64::make_local_ifunc_plt_entry): New method. (Target_aarch64::define_tls_base_symbol): New method. (Target_aarch64::reserve_tlsdesc_entries): New method. (Target_aarch64::got_mod_index_entry): New method. (Target_aarch64::rela_tlsdesc_section): New method. (Target_aarch64::rela_irelative_section): New method. (Target_aarch64::Tlsdesc_info): New struct. (Target_aarch64::got_section): Create .got.plt space for IRELATIVE relocations and tlsdesc relocations. (Target_aarch64::optimize_tls_reloc): Implement method. (Output_data_plt_aarch64): Add member variables: tlsdesc_rel_, got_, got_irelative_, irelative_count_, tlsdesc_got_offset_. Initialize them in constructor. (Output_data_plt_aarch64::reserve_tlsdesc_entry): New method. (Output_data_plt_aarch64::has_tlsdesc_entry): New method. (Output_data_plt_aarch64::get_tlsdesc_got_offset): New method. (Output_data_plt_aarch64::get_tlsdesc_plt_offset): New method. (Output_data_plt_aarch64::rela_tlsdesc): New method. (Output_data_plt_aarch64::rela_irelative): New method. (Output_data_plt_aarch64::entry_count): Count IRELATIVE relocations. (Output_data_plt_aarch64::first_plt_entry_offset): Add const attribute. (Output_data_plt_aarch64::get_plt_tlsdesc_entry_size): New method. (Output_data_plt_aarch64::fill_tlsdesc_entry): New method. (Output_data_plt_aarch64::do_get_plt_tlsdesc_entry_size): New method. (Output_data_plt_aarch64::do_fill_tlsdesc_entry): New method. (Output_data_plt_aarch64_standard): New member variables: plt_tlsdesc_entry_size, tlsdesc_plt_entry. (Output_data_plt_aarch64_standard::Output_data_plt_aarch64_standard): New parameter: got, got_irelative. (Output_data_plt_aarch64_standard::do_get_plt_entry_size): New method. (Output_data_plt_aarch64_standard::do_fill_tlsdesc_entry): New method. (Output_data_plt_aarch64::do_write): Replace got_address with gotplt_address. Add irelative_count_ to count. Write tlsdesc entry. (AArch64_relocate_functions::update_movnz): New method. (AArch64_relocate_functions): Correct format. (AArch64_relocate_functions::movnz): New method. (Target_aarch64::Scan::local): Correct format. Move r_sym, got to before the switch. Add new cases to switch. Check ie_to_le relaxation on tlsie relocations. Add code handling tlsgd tlsdesc cases. (Target_aarch64::Scan::global): Move arp to front. Do copy_reloc when needed. Add new cases to switch. Insert dynamic RELATIVE relocation when needed. Add code handling tlsgd, tlsie, tlsdesc cases. Call reloc_name_in_error_message to print unsupported reloc. (Target_aarch64::make_plt_section): Pass got_ and got_irelative_ to make_data_plt. (Target_aarch64::do_finalize_sections): Emit relocs to save COPY relocs. Fill in some more dynamic tags. (Target_aarch64::Relocate::relocate): Handle tlsgd, tlsdesc relocs. Skip call tls_get_addr when tlsgd is relaxed. (Target_aarch64::Relocate::relocate_tls): Correct format. Add code handling tlsgd, tlsdesc relocs, and tls gd->le, ie->le, tlsdesc->le, tlsdesc->ie relaxation.
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