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2014-07-20or1k: add missing l.msync, l.psync and l.psync instructions.Stefan Kristiansson2-0/+28
Even though the opcodes were defined for these instructions, the actual instruction definitions were lacking. cpu/ * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions. opcodes/ * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
2014-06-12Whitespace fixes for cpu/or1k.opcAlan Modra2-87/+91
* or1k.opc: Whitespace fixes.
2014-05-08or1k: add support for l.swa/l.lwa atomic instructionsStefan Kristiansson2-3/+56
This adds support for the load-link/store-conditional l.lwa/l.swa atomic instructions. The support is added in such way, that the cpu description not only describes the mnemonics, but also the functionality. A couple of fixes to typos in nearby/related code are also snuck into this. cpu/ * or1korbis.cpu (h-atomic-reserve): New hardware. (h-atomic-address): Likewise. (insn-opcode): Add opcodes for LWA and SWA. (atomic-reserve): New operand. (atomic-address): Likewise. (l-lwa, l-swa): New instructions. (l-lbs): Fix typo in comment. (store-insn): Clear atomic reserve on store to atomic-address. Fix register names in fmt field. opcodes/ * or1k-desc.c: Regenerated. * or1k-desc.h: Likewise. * or1k-opc.c: Likewise. * or1k-opc.h: Likewise. * or1k-opinst.c: Likewise.
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson8-938/+2224
with support for the new or1k configuration.
2013-12-07strip off +x bits on non-executable/script filesMike Frysinger2-0/+4
These files are source files and have no business being +x. We couldn't easily fix it in CVS (you need login+write access to the raw rcs files), but we can fix this w/git. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-03-08 PR binutils/15241Nick Clifton2-1/+9
* lm32.cpu (Control and status registers): Add CFG2, PSW, TLBVADDR, TLBPADDR and TLBBADVADDR. * lm32-desc.c: Regenerate.
2012-12-10Add copyright noticesNick Clifton1-0/+6
2012-11-302012-11-30 Oleg Raikhman <oleg@adapteva.com>Joern Rennecke2-28/+47
Joern Rennecke <joern.rennecke@embecosm.com> cpu: * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12. (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l. (testset-insn): Add NO_DIS attribute to t.l. (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l. (move-insns): Add NO-DIS attribute to cmov.l. (op-mmr-movts): Add NO-DIS attribute to movts.l. (op-mmr-movfs): Add NO-DIS attribute to movfs.l. (op-rrr): Add NO-DIS attribute to .l. (shift-rrr): Add NO-DIS attribute to .l. (op-shift-rri): Add NO-DIS attribute to i32.l. (bitrl, movtl): Add NO-DIS attribute. (op-iextrrr): Add NO-DIS attribute to .l (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l. (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise. opcodes: * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
2012-02-27cpu/Alan Modra2-2/+6
* mt.opc (print_dollarhex): Trim values to 32 bits. opcodes/ * mt-dis.c: Regenerate.
2011-12-15 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bitNick Clifton2-5/+10
hosts. * cgen-asm.c (cgen_parse_signed_integer): Add code to handle the sign extension of negative values on a 64-bit host. * frv-asm.c: Regenerate. * gas/frv/immediates.s: New test file - checks assembly of constant values. * gas/frv/immediates.d: Expected disassmbly. * gas/frv/allinsn.exp: Run the new test.
2011-10-27bfd:Joern Rennecke2-2/+2
* cpu-epiphany.c: Reinstate full list of Copyright years. * elf32-epiphany.c: Likewise. cpu: * epiphany.cpu, epiphany.opc: Likewise. gas: * config/tc-epiphany.c, config/tc-epiphany.h: Likewise. * doc/c-epiphany.texi: Likewise. include: * elf/epiphany.h: Likewise.
2011-10-26cpu:Joern Rennecke2-4/+10
* epiphany.opc (parse_branch_addr): Fix type of valuep. Cast value before printing it as a long. (parse_postindex): Fix type of valuep. opcodes: * epiphany-asm.c, epiphany-opc.h: Regenerate.
2011-10-25bfd:Nick Clifton3-0/+3356
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
2011-08-22Move cpu files from cgen/cpu to top level cpu directory.Nick Clifton22-0/+26465
2010-10-08Fix build with -DDEBUG=7Alan Modra2-0/+7
2010-07-03* m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.DJ Delorie2-2/+6
* m32c-ibld.c: Regenerate.
2010-02-12 * m32r.cpu (HASH-PREFIX): Delete.Doug Evans5-44/+150
(duhpo, dshpo): New pmacros. (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo. (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX attribute, define with dshpo. (uimm24): Delete HASH-PREFIX attribute. * m32r.opc (CGEN_PRINT_NORMAL): Delete. (print_signed_with_hash_prefix): New function. (print_unsigned_with_hash_prefix): New function. * xc16x.cpu (dowh): New pmacro. (upof16): Define with dowh, specify print handler. (qbit, qlobit, qhibit): Ditto. (upag16): Ditto. * xc16x.opc (CGEN_PRINT_NORMAL): Delete. (print_with_dot_prefix): New functions. (print_with_pof_prefix, print_with_pag_prefix): New functions.
2010-01-25 * desc-cpu.scm (cgen-desc.h): Don't print virtual enums.Doug Evans2-11/+22
* sid-cpu.scm (cgen-desc.h): Ditto. * enum.scm (enum-builtin!): New function. * read.scm (reader-install-builtin!): Call it. * rtl-c.scm (s-convop): Delete, replaced with ... (s-int-convop, s-float-convop): ... new fns. (ext, zext, trunc): Update. (fext, ftrunc, float, ufloat, fix, ufix): Update. * rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter `how'. * cpu/mep-fmax.cpu (fcvtsw): Update. * cpu/sh.cpu (h-fsd, h-fmov): Update. * doc/rtl.texi (float-convop): Update. * frv.cpu (floating-point-conversion): Update call to fp conv op. (floating-point-dual-conversion, ne-floating-point-dual-conversion, conditional-floating-point-conversion, ne-floating-point-conversion, float-parallel-mul-add-double-semantics): Ditto.
2010-01-06 cpu/Doug Evans2-12/+18
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. (f-dsp-40-u20, f-dsp-40-u24): Ditto. opcodes/ * cgen-ibld.in: #include "cgen/basic-modes.h". * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2010-01-02 * m32c.opc (parse_signed16): Fix typo.Doug Evans2-2/+6
2009-12-11Add -Wshadow to the gcc command line options used when compiling the binutils.Nick Clifton3-43/+43
Fix up all warnings generated by the addition of this switch.
2009-11-14 Must use VOID expression in VOID context.Doug Evans2-93/+114
* xc16x.cpu (mov4): Fix mode of `sequence'. (mov9, mov10): Ditto. (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'. (callr, callseg, calls, trap, rets, reti): Ditto. (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'. (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'. (exts, exts1, extsr, extsr1, prior): Ditto.
2009-10-24 cpu/Doug Evans2-2/+7
* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h. cgen-ops.h -> cgen/basic-ops.h. include/opcode/ * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. * cgen.h: Update. Improve multi-inclusion macro name. include/cgen/ * basic-modes.h: New file. Moved here from opcodes/cgen-types.h. * basic-ops.h: New file. Moved here from opcodes/cgen-ops.h. * bitset.h: New file. Moved here from ../opcode/cgen-bitset.h. Update license to GPL v3. opcodes/ * cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h. * cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h. * cgen-bitset.c: Update. * fr30-desc.h: Regenerate. * frv-desc.h: Regenerate. * ip2k-desc.h: Regenerate. * iq2000-desc.h: Regenerate. * lm32-desc.h: Regenerate. * m32c-desc.h: Regenerate. * m32c-opc.h: Regenerate. * m32r-desc.h: Regenerate. * mep-desc.h: Regenerate. * mt-desc.h: Regenerate. * openrisc-desc.h: Regenerate. * xc16x-desc.h: Regenerate. * xstormy16-desc.h: Regenerate.
2009-09-25 * m32r.cpu (stb-plus): Typo fix.Alan Modra2-1/+5
2009-09-23 * m32r.cpu (sth-plus): Fix address mode and calculation.Doug Evans3-101/+117
(stb-plus): Ditto. (clrpsw): Fix mask calculation. (bset, bclr, btst): Make mode in bit calculation match expression. * xc16x.cpu (rtl-version): Set to 0.8. (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix, make uppercase. Remove unnecessary name-prefix spec. (grb-names, conditioncode-names, extconditioncode-names): Ditto. (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto. (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto. (h-cr): New hardware. (muls): Comment out parts that won't compile, add fixme. (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto. (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto. (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
2009-09-02update copyright datesAlan Modra20-20/+22
2009-07-16 * cpu/simplify.inc (*): One line doc strings don't need \n.Doug Evans2-36/+45
(df): Invoke define-full-ifield instead of claiming it's an alias. (dno): Define. (dnop): Mark as deprecated.
2009-06-22cpu/Alan Modra2-1/+5
* m32c.opc (parse_lab_5_3): Use correct enum. opcodes/ * m32c-asm.c: Regenerate.
2009-01-07 * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.Hans-Peter Nilsson2-4/+21
(DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros. (media-arith-sat-semantics): Explicitly sign- or zero-extend arguments of "operation" to DI using "mode" and the new pmacros.
2009-01-03 * cris.cpu (cris-implemented-writable-specregs-v32): Correct sizeHans-Peter Nilsson2-1/+6
of number 2, PID.
2008-12-23Add LM32 port.Nick Clifton3-0/+1172
2008-01-29 * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c changeAlan Modra2-2/+7
to source.
2007-10-22 * cris.cpu (movs, movu): Use result of extension operation whenHans-Peter Nilsson2-6/+13
updating flags.
2007-07-05Change source files over to GPLv3.Nick Clifton21-62/+98
2007-04-30Support new FR-V SPRsMark Salter2-4/+17
2007-04-20Changelog entry for previous deltaNick Clifton1-0/+5
2007-04-20Restore from version 1.1Nick Clifton1-245/+3129
2007-03-29* m32c.cpu (Imm-8-s4n): Fix print hook.DJ Delorie2-7/+14
(Lab-24-8, Lab-32-8, Lab-40-8): Fix. (arith-jnz-imm4-dst-defn): Make relaxable. (arith-jnz16-imm4-dst-defn): Fix encodings. * m32c-desc.c: Regenerate. * m32c-dis.c: Regenerate. * m32c-opc.c: Regenerate. * config/tc-m32c.c (rl_for, relaxable): Protect argument. (md_relax_table): Add entries for ADJNZ macros. (M32C_Macros): Add ADJNZ macros. (subtype_mappings): Add entries for ADJNZ macros. (insn_to_subtype): Check for adjnz and sbjnz insns. (md_estimate_size_before_relax): Pass insn to insn_to_subtype. (md_convert_frag): Convert adjnz and sbjnz.
2007-03-21* m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,DJ Delorie2-11/+112
mem20): New. (src16-16-20-An-relative-*): New. (dst16-*-20-An-relative-*): New. (dst16-16-16sa-*): New (dst16-16-16ar-*): New (dst32-16-16sa-Unprefixed-*): New (jsri): Fix operands. (setzx): Fix encoding. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.h: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
2007-03-08 * m32r.opc: Formatting.Alan Modra2-10/+14
2006-05-22* iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.Nick Clifton2-5/+6
2006-04-10* m32c.opc (parse_unsigned_bitbase): Take a new parameter whichDJ Delorie2-10/+55
decides if this function accepts symbolic constants or not. (parse_signed_bitbase): Likewise. (parse_unsigned_bitbase8): Pass the new parameter. (parse_unsigned_bitbase11): Likewise. (parse_unsigned_bitbase16): Likewise. (parse_unsigned_bitbase19): Likewise. (parse_unsigned_bitbase27): Likewise. (parse_signed_bitbase8): Likewise. (parse_signed_bitbase11): Likewise. (parse_signed_bitbase19): Likewise. * m32c-asm.c: Regenerate.
2006-03-14* m32c.cpu (Bit3-S): New.DJ Delorie3-1/+30
(btst:s): New. * m32c.opc (parse_bit3_S): New.
2006-03-14* m32c.cpu (decimal-subtraction16-insn): Add second operand.DJ Delorie2-5/+22
(btst): Add optional :G suffix for MACH32. (or.b:S): New. (pop.w:G): Add optional :G suffix for MACH16. (push.b.imm): Fix syntax.
2006-03-11* m32c.cpu (mul.l): New.DJ Delorie2-0/+16
(mulu.l): New. * m32c-desc.c: Regenerate with mul.l, mulu.l. * m32c-opc.c: Likewise. * m32c-opc.h: Likewise.
2006-03-03Fix parseing functions to return an error message if the parse failedNick Clifton3-3153/+296
2006-02-24[include/elf]DJ Delorie2-26/+51
* m32c.h: Add relax relocs. [cpu] * m32c.cpu (RL_TYPE): New attribute, with macros. (Lab-8-24): Add RELAX. (unary-insn-defn-g, binary-arith-imm-dst-defn, binary-arith-imm4-dst-defn): Add 1ADDR attribute. (binary-arith-src-dst-defn): Add 2ADDR attribute. (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP attribute. (jsri16, jsri32): Add 1ADDR attribute. (jsr32.w, jsr32.a): Add JUMP attribute. [opcodes] * m32c-desc.c: Regenerate with linker relaxation attributes. * m32c-desc.h: Likewise. * m32c-dis.c: Likewise. * m32c-opc.c: Likewise. [gas] * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix. (tc_gen_reloc): Don't define. * config/tc-m32c.c (rl_for, relaxable): New convenience macros. (OPTION_LINKRELAX): New. (md_longopts): Add it. (m32c_relax): New. (md_parse_options): Set it. (md_assemble): Emit relaxation relocs as needed. (md_convert_frag): Emit relaxation relocs as needed. (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16. (m32c_apply_fix): New. (tc_gen_reloc): New. (m32c_force_relocation): Force out jump relocs when relaxing. (m32c_fix_adjustable): Return false if relaxing. [bfd] * elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs. (m32c_elf_relocate_section): Don't relocate them. (compare_reloc): New. (relax_reloc): Remove. (m32c_offset_for_reloc): New. (m16c_addr_encodings): New. (m16c_jmpaddr_encodings): New. (m32c_addr_encodings): New. (m32c_elf_relax_section): Relax jumps and address displacements. (m32c_elf_relax_delete_bytes): Adjust for internal syms. Fix up short jumps. * reloc.c: Add m32c relax relocs. * libbfd.h: Regenerate.
2006-02-17Add support for the Infineon XC16X.Nick Clifton3-0/+3362
2006-02-10Fix %hi() operator for 64-bit hosts.Nick Clifton2-0/+6
2006-01-06* m32c.cpu (mov.w:q): Fix mode.DJ Delorie2-2/+7
(push32.b.imm): Likewise, for the comment.
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