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2019-12-11Remove more shifts for sign/zero extensionAlan Modra4-9/+23
cpu/ * epiphany.cpu (f-sdisp11): Don't sign extend with shifts. * lm32.cpu (f-branch, f-vall): Likewise. * m32.cpu (f-lab-8-16): Likewise. opcodes/ * arc-dis.c (BITS): Don't truncate high bits with shifts. * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts. * tic54x-dis.c (print_instruction): Likewise. * tilegx-opc.c (parse_insn_tilegx): Likewise. * tilepro-opc.c (parse_insn_tilepro): Likewise. * visium-dis.c (disassem_class0): Likewise. * pdp11-dis.c (sign_extend): Likewise. (SIGN_BITS): Delete. * epiphany-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate.
2019-12-11ubsan: epiphany: left shift of negative valueAlan Modra2-2/+7
Two places in epiphany_cgen_extract_operand, "value" is a long. value = ((((value) << (1))) + (pc)); cpu/ * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than shift left to avoid UB on left shift of negative values. opcodes/ * epiphany-ibld.c: Regenerate.
2019-11-20cpu: fix comment in bpf.cpuJose E. Marchesi2-1/+5
2019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu: Fix comment describing the 128-bit instruction format.
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell1-0/+4
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi2-2/+7
This patch changes the eBPF CPU description to prefer the register names %r0 and %r6 instead of %a and %ctx when disassembling. This matches better with the current practice, vs. cBPF. It also updates the GAS tests in order to reflect this change. Tested in a x86_64 host. cpu/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of %a and %ctx. opcodes/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerated. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise.
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi2-25/+43
This patch fixes the eBPF CPU description in order to reflect the right explicit arguments passed to the ldabs{b,h,w,dw} instructions, updates the corresponding GAS tests, and updates the BPF section of the GAS manual. cpu/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlabs): New pmacro. (dlind): Likewise. opcodes/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. gas/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src' register as an argument. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct explicit arguments to ldabs and ldind instructions.
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi2-2/+7
The eBPF non-generic load instructions ldind{b,h,w,dw} and ldabs{b,h,w,dw} do not take an explicit destination register as an argument. Instead, they put the loaded value in %r0, implicitly. This patch fixes the CPU BPF description to not expect a 'dst' argument in these arguments, regenerates the corresponding files in opcodes, and updates the impacted GAS tests. Tested in a x86-64 host. cpu/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlsi): ldabs and ldind instructions do not take an explicit 'dst' argument. opcodes/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. gas/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Do not use explicit arguments for ldabs and ldind instructions. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise.
2019-06-13cpu/or1k: Update fpu compare symbols to imply set flagStafford Horne2-3/+7
The fpu compare symbols where not including 'sf' in the mnemonic. So instead of `lf-sfeq` (implying set flag if operands are equal) we were having `lf-eq`. This patch adds the 'sf'. This helps with making the generated CGEN documentation consistent and ordered correctly. cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
2019-06-13cpu/or1k: Document no branch delay slot architectures and l.adrpStafford Horne3-4/+9
The 'nd' architectures did not mention what the 'nd' stands for. Document that these mean 'no brach delay slot'. cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a (l-adrp): Improve comment.
2019-06-13cpu/or1k: Define unordered comparisonsStafford Horne2-4/+55
Add support for new floating point unordered comparisons. These have been defined in OpenRISC architecture proposal 7[0] and are now included in the architecture specification 1.3. These new instructions provide the ability for floating point comparisons to detect NaNs. [0] https://openrisc.io/proposals/lfsf cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S, SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D, SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes. (float-setflag-insn-base): New pmacro based on float-setflag-insn. (float-setflag-symantics, float-setflag-unordered-cmp-symantics, float-setflag-unordered-symantics): New pmacro for instruction symantics. (float-setflag-insn): Update to use float-setflag-insn-base. (float-setflag-unordered-insn): New pmacro for generating instructions.
2019-06-13cpu/or1k: Add support for orfp64a32 specStafford Horne6-46/+375
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by using register pairs. The functionality has been added to OpenRISC architecture specification version 1.3 as per architecture proposal 14[0]. For supporting assembly of both 64-bit and 32-bit precision instructions we have defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit architecture assembly parsing on 64-bit toolchains and 32-bit architecture assembly parsing on 32-bit toolchains. Without this the assembler has issues parsing register pairs. This patch also contains a few fixes to the symantics for existing OpenRISC single and double precision FPU operations. [0] https://openrisc.io/proposals/orfpx64a32 cpu/ChangeLog: yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org> Stafford Horne <shorne@gmail.com> * or1k.cpu (ORFPX64A32-MACHS): New pmacro. (ORFPX-MACHS): Removed pmacro. * or1k.opc (or1k_cgen_insn_supported): New function. (CGEN_VALIDATE_INSN_SUPPORTED): Define macro. (parse_regpair, print_regpair): New functions. * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder and add comments. (h-fdr): Update comment to indicate or64. (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs. (h-fd32r): New hardware for 64-bit fpu registers. (h-i64r): New hardware for 64-bit int registers. * or1korbis.cpu (f-resv-8-1): New field. * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS. (rDDF, rADF, rBDF): Update operand comment to indicate or64. (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields. (h-roff1): New hardware. (double-field-and-ops mnemonic): New pmacro to generate operations rDD32F, rAD32F, rBD32F, rDDI and rADI. (float-regreg-insn): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (float-setflag-insn): Update single precision generator to MACH ORFPX32-MACHS. Fix double instructions from single to double precision. Add generator for or32 64-bit instructions. (float-cust-insn cust-num): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to ORFPX32-MACHS. (lf-rem-d): Fix operation from mod to rem. (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction. (lf-itof-d): Fix operands from single to double. (lf-ftoi-d): Update operand mode from DI to WI.
2019-05-23cpu: add eBPF cpu descriptionJose E. Marchesi3-0/+843
This patch adds a CPU description for the Linux kernel eBPF virtual machine, plus supporting code for disassembler and assembler. cpu/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu: New file. * bpf.opc: Likewise.
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson2-93/+181
Also fix the incorrect definitions of multiply and divide carry and overflow float. Changes to the instructions are made in the .cpu file, then we regenerate the binutils and sim files. The changes also required a few fixups for tests and additional sim helpers. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU. (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU. (l-mul): Fix overflow support and indentation. (l-mulu): Fix overflow support and indentation. (l-muld, l-muldu, l-msbu, l-macu): New instructions. (l-div); Remove incorrect carry behavior. (l-divu): Fix carry and overflow behavior. (l-mac): Add overflow support. (l-msb, l-msbu): Add carry and overflow support. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. sim/common/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * cgen-ops.h (ADDCFDI): New function, add carry flag DI variant. (ADDOFDI): New function, add overflow flag DI variant. (SUBCFDI): New function, subtract carry flag DI variant. (SUBOFDI): New function, subtract overflow flag DI variant. sim/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1k/cpu.h: Regenerate. * or1k/decode.c: Regenerate. * or1k/decode.h: Regenerate. * or1k/model.c: Regenerate. * or1k/sem-switch.c: Regenerate. * or1k/sem.c: Regenerate: sim/testsuite/sim/or1k/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * div.S: Fix tests to match correct overflow/carry semantics. * mul.S: Likewise. gas/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * testsuite/gas/or1k/allinsn.s: Add instruction tests for l.muld, l.muldu, l.macu, l.msb, l.msbu. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions.
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne3-62/+213
This patch adds the new instruction and relocation as per proposal: https://openrisc.io/proposals/ladrp This is to be added to the spec in an upcoming revision. The new instruction l.adrp loads the page offset of the current instruction offset by a 21-bit immediate shifted left 13-bits. This is meant to be used with a 13-bit lower bit page offset. This allows us to free up the got register r16. l.adrp r3, foo l.ori r4, r3, po(foo) l.lbz r5, po(foo)(r3) l.sb po(foo)(r3), r6 The relocations we add are: - BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry asm: plta() implemented using l.ardp, meaning no need for r16 (the GOT reg) - BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address asm: got() - BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General asm: tlsgd() Dynamic calculation - BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local asm: tlsldm() dynamic calculation - BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial asm: gottp() Executable calculation - BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp instructions) - BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation asm: po() i.e. mem loads, addi etc - BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation asm: po() i.e. mem stores, with split immediate - BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs asm: gotpo() - BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs asm: tlsgdpo() - BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs asm: tlsldmpo() - BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs asm: gottppo() bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * bfd-in2.h: Regenerated. * elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. (or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26. (elf_or1k_link_hash_table): Add field saw_plta. (or1k_final_link_relocate): Add value calculations for new relocations. (or1k_elf_relocate_section): Add section relocations for new relocations. (or1k_write_plt_entry): New function. (or1k_elf_finish_dynamic_sections): Add support for PLTA relocations using new l.adrp instruction. Cleanup PLT relocation code generation. * libbfd.h: Regenerated. * reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc (parse_disp26): Add support for plta() relocations. (parse_disp21): New function. (or1k_rclass): New enum. (or1k_rtype): New enum. (or1k_imm16_relocs): Define new PO and SPO relocation mappings. (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. (parse_imm16): Add support for the new 21bit and 13bit relocations. * or1korbis.cpu (f-disp26): Don't assume SI. (f-disp21): New pc-relative 21-bit 13 shifted to right. (insn-opcode): Add ADRP. (l-adrp): New instruction. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. * testsuite/gas/or1k/allinsn.s: Add test for l.adrp. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. * testsuite/gas/or1k/reloc-1.s: Add tests to generate R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13 relocations. * testsuite/gas/or1k/reloc-1.d: Add relocation results for tests. * testsuite/gas/or1k/reloc-2.s: Add negative tests for store to gotpo(). * testsuite/gas/or1k/reloc-2.l: Add expected error test results. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/or1k.exp: Add test cases for plt generation. * testsuite/ld-or1k/plt1.dd: New file. * testsuite/ld-or1k/plt1.s: New file. * testsuite/ld-or1k/plt1.x.dd: New file. * testsuite/ld-or1k/plta1.dd: New file. * testsuite/ld-or1k/plta1.s: New file. * testsuite/ld-or1k/pltlib.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson3-292/+203
This patch adds the following target relocations: - BFD_RELOC_HI16_S High 16-bit relocation, for used with signed asm: ha() lower. - BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local asm: gotoffha() symbols, for use with signed lower. - BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial asm: gottpoffha() executable calculation, for use with signed lower. - BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable asm: tpoffha() variables, for use with signed lower. - BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with asm: lo() OpenRISC store instructions. - BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for asm: gotofflo() local symbols, used with OpenRISC store instructions. - BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local asm: tpofflo() executable variables, used with OpenRISC store instructions. bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * bfd-in2.h: Regenerated. * elf32-or1k.c (N_ONES): New macro. (or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow. Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF, R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. (or1k_reloc_map): Add entries for BFD_RELOC_HI16_S, BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_LE_SLO16. (or1k_reloc_type_lookup): Change search loop to start ad index 0 and also check results before returning. (or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index limit. (or1k_final_link_relocate): New function. (or1k_elf_relocate_section): Add support for new AHI and SLO relocations. Use or1k_final_link_relocate instead of generic _bfd_final_link_relocate. (or1k_elf_check_relocs): Add support for new AHI and SLO relocations. * reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16 and BFD_RELOC_OR1K_GOTOFF_LO16. * libbfd.h: Regenerated. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc: Add RTYPE_ enum. (INVALID_STORE_RELOC): New string. (or1k_imm16_relocs): New array array. (parse_reloc): New static function that just does the parsing. (parse_imm16): New static function for generic parsing. (parse_simm16): Change to just call parse_imm16. (parse_simm16_split): New function. (parse_uimm16): Change to call parse_imm16. (parse_uimm16_split): New function. * or1korbis.cpu (simm16-split): Change to use new simm16_split. (uimm16-split): Change to use new uimm16_split. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation. * testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations. * testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp. * testsuite/gas/or1k/or1k.exp: Add reloc-2 list test. * testsuite/gas/or1k/reloc-1.d: New file. * testsuite/gas/or1k/reloc-1.s: New file. * testsuite/gas/or1k/reloc-2.l: New file. * testsuite/gas/or1k/reloc-2.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/offsets1.d: New file. * testsuite/ld-or1k/offsets1.s: New file. * testsuite/ld-or1k/or1k.exp: New file. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerate.
2018-07-24PR23430, Indices misspelledAlan Modra2-1/+6
PR 23430 include/ * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo. bfd/ * dwarf2.c (dwarf_debug_section_enum): Fix comment typo. * elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise. binutils/ * elfcomm.h (struct archive_info): Rename uses_64bit_indicies to uses_64bit_indices. * elfcomm.c (setup_archive): Update uses of above. * readelf.c (process_archive): Likewise. (get_section_type_name): Rename indicies to indices. (get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise. (process_section_groups): Likewise. cpu/ * or1kcommon.cpu (spr-reg-indices): Fix description typo. opcodes/ * or1k-desc.h: Regenerate.
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra2-1/+5
PR 22069 binutils/ * od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming. cpu/ChangeLog * or1kcommon.cpu (spr-reg-info): Typo fix. include/ChangeLog * mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS): Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS. (MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS. opcodes/ChangeLog * cr16-opc.c (cr16_instruction): Comment typo fix. * hppa-dis.c (print_insn_hppa): Likewise. sim/ppc/ChangeLog * e500_registers.h: Comment typo fix. * ppc-instructions (ppc_insn_mfcr): Likewise.
2018-03-03opcodes error messagesAlan Modra2-8/+16
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2017-03-20Update the openrisc previous program counter (ppc) when running code in the ↵Stafford Horne2-0/+9
cgen based simulator. * or1kcommon.cpu: Add pc set semantics to also update ppc.
2016-10-06Add fall through comment to source in cpu/Alan Modra2-0/+5
I edited opcodes/mep-asm.c in 1a0670f3 without noticing it was a generated file. * mep.opc (expand_string): Add fall through comment.
2016-03-03Correct fr30 commentAlan Modra2-3/+10
* fr30.cpu (f.m4): Replace bogus comment with a better guess at what is really going on.
2016-03-02Fix shift left warning at sourceAlan Modra2-1/+5
cpu/ * fr30.cpu (f-m4): Replace -1 << 4 with -16. opcodes/ * fr30-ibld.c: Regenerate.
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess2-2/+8
Always set the bytes_per_line field (of struct disassemble_info) to the same constant value, this is inline with the advice contained within include/dis-asm.h. Setting this field to a constant value will cause the disassembler output to be better aligned. cpu/ChangeLog: * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to a constant to better align disassembler output. opcodes/ChangeLog: * epiphany-dis.c: Regenerated from latest cpu files. gas/ChangeLog: * testsuite/gas/epiphany/sample.d: Update expected output.
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-7/+7
2014-07-20or1k: add missing l.msync, l.psync and l.psync instructions.Stefan Kristiansson2-0/+28
Even though the opcodes were defined for these instructions, the actual instruction definitions were lacking. cpu/ * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions. opcodes/ * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
2014-06-12Whitespace fixes for cpu/or1k.opcAlan Modra2-87/+91
* or1k.opc: Whitespace fixes.
2014-05-08or1k: add support for l.swa/l.lwa atomic instructionsStefan Kristiansson2-3/+56
This adds support for the load-link/store-conditional l.lwa/l.swa atomic instructions. The support is added in such way, that the cpu description not only describes the mnemonics, but also the functionality. A couple of fixes to typos in nearby/related code are also snuck into this. cpu/ * or1korbis.cpu (h-atomic-reserve): New hardware. (h-atomic-address): Likewise. (insn-opcode): Add opcodes for LWA and SWA. (atomic-reserve): New operand. (atomic-address): Likewise. (l-lwa, l-swa): New instructions. (l-lbs): Fix typo in comment. (store-insn): Clear atomic reserve on store to atomic-address. Fix register names in fmt field. opcodes/ * or1k-desc.c: Regenerated. * or1k-desc.h: Likewise. * or1k-opc.c: Likewise. * or1k-opc.h: Likewise. * or1k-opinst.c: Likewise.
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson8-938/+2224
with support for the new or1k configuration.
2013-12-07strip off +x bits on non-executable/script filesMike Frysinger2-0/+4
These files are source files and have no business being +x. We couldn't easily fix it in CVS (you need login+write access to the raw rcs files), but we can fix this w/git. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-03-08 PR binutils/15241Nick Clifton2-1/+9
* lm32.cpu (Control and status registers): Add CFG2, PSW, TLBVADDR, TLBPADDR and TLBBADVADDR. * lm32-desc.c: Regenerate.
2012-12-10Add copyright noticesNick Clifton1-0/+6
2012-11-302012-11-30 Oleg Raikhman <oleg@adapteva.com>Joern Rennecke2-28/+47
Joern Rennecke <joern.rennecke@embecosm.com> cpu: * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12. (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l. (testset-insn): Add NO_DIS attribute to t.l. (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l. (move-insns): Add NO-DIS attribute to cmov.l. (op-mmr-movts): Add NO-DIS attribute to movts.l. (op-mmr-movfs): Add NO-DIS attribute to movfs.l. (op-rrr): Add NO-DIS attribute to .l. (shift-rrr): Add NO-DIS attribute to .l. (op-shift-rri): Add NO-DIS attribute to i32.l. (bitrl, movtl): Add NO-DIS attribute. (op-iextrrr): Add NO-DIS attribute to .l (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l. (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise. opcodes: * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
2012-02-27cpu/Alan Modra2-2/+6
* mt.opc (print_dollarhex): Trim values to 32 bits. opcodes/ * mt-dis.c: Regenerate.
2011-12-15 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bitNick Clifton2-5/+10
hosts. * cgen-asm.c (cgen_parse_signed_integer): Add code to handle the sign extension of negative values on a 64-bit host. * frv-asm.c: Regenerate. * gas/frv/immediates.s: New test file - checks assembly of constant values. * gas/frv/immediates.d: Expected disassmbly. * gas/frv/allinsn.exp: Run the new test.
2011-10-27bfd:Joern Rennecke2-2/+2
* cpu-epiphany.c: Reinstate full list of Copyright years. * elf32-epiphany.c: Likewise. cpu: * epiphany.cpu, epiphany.opc: Likewise. gas: * config/tc-epiphany.c, config/tc-epiphany.h: Likewise. * doc/c-epiphany.texi: Likewise. include: * elf/epiphany.h: Likewise.
2011-10-26cpu:Joern Rennecke2-4/+10
* epiphany.opc (parse_branch_addr): Fix type of valuep. Cast value before printing it as a long. (parse_postindex): Fix type of valuep. opcodes: * epiphany-asm.c, epiphany-opc.h: Regenerate.
2011-10-25bfd:Nick Clifton3-0/+3356
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
2011-08-22Move cpu files from cgen/cpu to top level cpu directory.Nick Clifton22-0/+26465
2010-10-08Fix build with -DDEBUG=7Alan Modra2-0/+7
2010-07-03* m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.DJ Delorie2-2/+6
* m32c-ibld.c: Regenerate.
2010-02-12 * m32r.cpu (HASH-PREFIX): Delete.Doug Evans5-44/+150
(duhpo, dshpo): New pmacros. (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo. (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX attribute, define with dshpo. (uimm24): Delete HASH-PREFIX attribute. * m32r.opc (CGEN_PRINT_NORMAL): Delete. (print_signed_with_hash_prefix): New function. (print_unsigned_with_hash_prefix): New function. * xc16x.cpu (dowh): New pmacro. (upof16): Define with dowh, specify print handler. (qbit, qlobit, qhibit): Ditto. (upag16): Ditto. * xc16x.opc (CGEN_PRINT_NORMAL): Delete. (print_with_dot_prefix): New functions. (print_with_pof_prefix, print_with_pag_prefix): New functions.
2010-01-25 * desc-cpu.scm (cgen-desc.h): Don't print virtual enums.Doug Evans2-11/+22
* sid-cpu.scm (cgen-desc.h): Ditto. * enum.scm (enum-builtin!): New function. * read.scm (reader-install-builtin!): Call it. * rtl-c.scm (s-convop): Delete, replaced with ... (s-int-convop, s-float-convop): ... new fns. (ext, zext, trunc): Update. (fext, ftrunc, float, ufloat, fix, ufix): Update. * rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter `how'. * cpu/mep-fmax.cpu (fcvtsw): Update. * cpu/sh.cpu (h-fsd, h-fmov): Update. * doc/rtl.texi (float-convop): Update. * frv.cpu (floating-point-conversion): Update call to fp conv op. (floating-point-dual-conversion, ne-floating-point-dual-conversion, conditional-floating-point-conversion, ne-floating-point-conversion, float-parallel-mul-add-double-semantics): Ditto.
2010-01-06 cpu/Doug Evans2-12/+18
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. (f-dsp-40-u20, f-dsp-40-u24): Ditto. opcodes/ * cgen-ibld.in: #include "cgen/basic-modes.h". * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2010-01-02 * m32c.opc (parse_signed16): Fix typo.Doug Evans2-2/+6
2009-12-11Add -Wshadow to the gcc command line options used when compiling the binutils.Nick Clifton3-43/+43
Fix up all warnings generated by the addition of this switch.
2009-11-14 Must use VOID expression in VOID context.Doug Evans2-93/+114
* xc16x.cpu (mov4): Fix mode of `sequence'. (mov9, mov10): Ditto. (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'. (callr, callseg, calls, trap, rets, reti): Ditto. (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'. (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'. (exts, exts1, extsr, extsr1, prior): Ditto.
2009-10-24 cpu/Doug Evans2-2/+7
* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h. cgen-ops.h -> cgen/basic-ops.h. include/opcode/ * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. * cgen.h: Update. Improve multi-inclusion macro name. include/cgen/ * basic-modes.h: New file. Moved here from opcodes/cgen-types.h. * basic-ops.h: New file. Moved here from opcodes/cgen-ops.h. * bitset.h: New file. Moved here from ../opcode/cgen-bitset.h. Update license to GPL v3. opcodes/ * cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h. * cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h. * cgen-bitset.c: Update. * fr30-desc.h: Regenerate. * frv-desc.h: Regenerate. * ip2k-desc.h: Regenerate. * iq2000-desc.h: Regenerate. * lm32-desc.h: Regenerate. * m32c-desc.h: Regenerate. * m32c-opc.h: Regenerate. * m32r-desc.h: Regenerate. * mep-desc.h: Regenerate. * mt-desc.h: Regenerate. * openrisc-desc.h: Regenerate. * xc16x-desc.h: Regenerate. * xstormy16-desc.h: Regenerate.
2009-09-25 * m32r.cpu (stb-plus): Typo fix.Alan Modra2-1/+5
generated by cgit v1.1 at 2024-11-26 00:36:44 +0000