Age | Commit message (Collapse) | Author | Files | Lines |
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cgen based simulator.
* or1kcommon.cpu: Add pc set semantics to also update ppc.
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I edited opcodes/mep-asm.c in 1a0670f3 without noticing it was a
generated file.
* mep.opc (expand_string): Add fall through comment.
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* fr30.cpu (f.m4): Replace bogus comment with a better guess
at what is really going on.
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cpu/
* fr30.cpu (f-m4): Replace -1 << 4 with -16.
opcodes/
* fr30-ibld.c: Regenerate.
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Always set the bytes_per_line field (of struct disassemble_info) to the
same constant value, this is inline with the advice contained within
include/dis-asm.h.
Setting this field to a constant value will cause the disassembler
output to be better aligned.
cpu/ChangeLog:
* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
a constant to better align disassembler output.
opcodes/ChangeLog:
* epiphany-dis.c: Regenerated from latest cpu files.
gas/ChangeLog:
* testsuite/gas/epiphany/sample.d: Update expected output.
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Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.
cpu/
* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
opcodes/
* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
* or1k-opinst.c: Regenerate.
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* or1k.opc: Whitespace fixes.
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This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.
A couple of fixes to typos in nearby/related code are also snuck
into this.
cpu/
* or1korbis.cpu (h-atomic-reserve): New hardware.
(h-atomic-address): Likewise.
(insn-opcode): Add opcodes for LWA and SWA.
(atomic-reserve): New operand.
(atomic-address): Likewise.
(l-lwa, l-swa): New instructions.
(l-lbs): Fix typo in comment.
(store-insn): Clear atomic reserve on store to atomic-address.
Fix register names in fmt field.
opcodes/
* or1k-desc.c: Regenerated.
* or1k-desc.h: Likewise.
* or1k-opc.c: Likewise.
* or1k-opc.h: Likewise.
* or1k-opinst.c: Likewise.
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with support for the new or1k configuration.
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These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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* lm32.cpu (Control and status registers): Add CFG2, PSW,
TLBVADDR, TLBPADDR and TLBBADVADDR.
* lm32-desc.c: Regenerate.
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Joern Rennecke <joern.rennecke@embecosm.com>
cpu:
* epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
(load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
(testset-insn): Add NO_DIS attribute to t.l.
(store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
(move-insns): Add NO-DIS attribute to cmov.l.
(op-mmr-movts): Add NO-DIS attribute to movts.l.
(op-mmr-movfs): Add NO-DIS attribute to movfs.l.
(op-rrr): Add NO-DIS attribute to .l.
(shift-rrr): Add NO-DIS attribute to .l.
(op-shift-rri): Add NO-DIS attribute to i32.l.
(bitrl, movtl): Add NO-DIS attribute.
(op-iextrrr): Add NO-DIS attribute to .l
(op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
(op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
opcodes:
* epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
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* mt.opc (print_dollarhex): Trim values to 32 bits.
opcodes/
* mt-dis.c: Regenerate.
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hosts.
* cgen-asm.c (cgen_parse_signed_integer): Add code to handle the
sign extension of negative values on a 64-bit host.
* frv-asm.c: Regenerate.
* gas/frv/immediates.s: New test file - checks assembly of
constant values.
* gas/frv/immediates.d: Expected disassmbly.
* gas/frv/allinsn.exp: Run the new test.
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* cpu-epiphany.c: Reinstate full list of Copyright years.
* elf32-epiphany.c: Likewise.
cpu:
* epiphany.cpu, epiphany.opc: Likewise.
gas:
* config/tc-epiphany.c, config/tc-epiphany.h: Likewise.
* doc/c-epiphany.texi: Likewise.
include:
* elf/epiphany.h: Likewise.
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* epiphany.opc (parse_branch_addr): Fix type of valuep.
Cast value before printing it as a long.
(parse_postindex): Fix type of valuep.
opcodes:
* epiphany-asm.c, epiphany-opc.h: Regenerate.
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* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
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* m32c-ibld.c: Regenerate.
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(duhpo, dshpo): New pmacros.
(simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
(uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
attribute, define with dshpo.
(uimm24): Delete HASH-PREFIX attribute.
* m32r.opc (CGEN_PRINT_NORMAL): Delete.
(print_signed_with_hash_prefix): New function.
(print_unsigned_with_hash_prefix): New function.
* xc16x.cpu (dowh): New pmacro.
(upof16): Define with dowh, specify print handler.
(qbit, qlobit, qhibit): Ditto.
(upag16): Ditto.
* xc16x.opc (CGEN_PRINT_NORMAL): Delete.
(print_with_dot_prefix): New functions.
(print_with_pof_prefix, print_with_pag_prefix): New functions.
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* sid-cpu.scm (cgen-desc.h): Ditto.
* enum.scm (enum-builtin!): New function.
* read.scm (reader-install-builtin!): Call it.
* rtl-c.scm (s-convop): Delete, replaced with ...
(s-int-convop, s-float-convop): ... new fns.
(ext, zext, trunc): Update.
(fext, ftrunc, float, ufloat, fix, ufix): Update.
* rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter
`how'.
* cpu/mep-fmax.cpu (fcvtsw): Update.
* cpu/sh.cpu (h-fsd, h-fmov): Update.
* doc/rtl.texi (float-convop): Update.
* frv.cpu (floating-point-conversion): Update call to fp conv op.
(floating-point-dual-conversion, ne-floating-point-dual-conversion,
conditional-floating-point-conversion, ne-floating-point-conversion,
float-parallel-mul-add-double-semantics): Ditto.
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* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
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Fix up all warnings generated by the addition of this switch.
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* xc16x.cpu (mov4): Fix mode of `sequence'.
(mov9, mov10): Ditto.
(movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
(callr, callseg, calls, trap, rets, reti): Ditto.
(jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'.
(atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
(exts, exts1, extsr, extsr1, prior): Ditto.
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* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
cgen-ops.h -> cgen/basic-ops.h.
include/opcode/
* cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
* cgen.h: Update. Improve multi-inclusion macro name.
include/cgen/
* basic-modes.h: New file. Moved here from opcodes/cgen-types.h.
* basic-ops.h: New file. Moved here from opcodes/cgen-ops.h.
* bitset.h: New file. Moved here from ../opcode/cgen-bitset.h.
Update license to GPL v3.
opcodes/
* cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h.
* cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h.
* cgen-bitset.c: Update.
* fr30-desc.h: Regenerate.
* frv-desc.h: Regenerate.
* ip2k-desc.h: Regenerate.
* iq2000-desc.h: Regenerate.
* lm32-desc.h: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-opc.h: Regenerate.
* m32r-desc.h: Regenerate.
* mep-desc.h: Regenerate.
* mt-desc.h: Regenerate.
* openrisc-desc.h: Regenerate.
* xc16x-desc.h: Regenerate.
* xstormy16-desc.h: Regenerate.
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(stb-plus): Ditto.
(clrpsw): Fix mask calculation.
(bset, bclr, btst): Make mode in bit calculation match expression.
* xc16x.cpu (rtl-version): Set to 0.8.
(gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
make uppercase. Remove unnecessary name-prefix spec.
(grb-names, conditioncode-names, extconditioncode-names): Ditto.
(grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
(reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
(h-cr): New hardware.
(muls): Comment out parts that won't compile, add fixme.
(mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
(scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
(bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
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(df): Invoke define-full-ifield instead of claiming it's an alias.
(dno): Define.
(dnop): Mark as deprecated.
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* m32c.opc (parse_lab_5_3): Use correct enum.
opcodes/
* m32c-asm.c: Regenerate.
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(DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
(media-arith-sat-semantics): Explicitly sign- or zero-extend
arguments of "operation" to DI using "mode" and the new pmacros.
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of number 2, PID.
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to source.
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updating flags.
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(Lab-24-8, Lab-32-8, Lab-40-8): Fix.
(arith-jnz-imm4-dst-defn): Make relaxable.
(arith-jnz16-imm4-dst-defn): Fix encodings.
* m32c-desc.c: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-opc.c: Regenerate.
* config/tc-m32c.c (rl_for, relaxable): Protect argument.
(md_relax_table): Add entries for ADJNZ macros.
(M32C_Macros): Add ADJNZ macros.
(subtype_mappings): Add entries for ADJNZ macros.
(insn_to_subtype): Check for adjnz and sbjnz insns.
(md_estimate_size_before_relax): Pass insn to insn_to_subtype.
(md_convert_frag): Convert adjnz and sbjnz.
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mem20): New.
(src16-16-20-An-relative-*): New.
(dst16-*-20-An-relative-*): New.
(dst16-16-16sa-*): New
(dst16-16-16ar-*): New
(dst32-16-16sa-Unprefixed-*): New
(jsri): Fix operands.
(setzx): Fix encoding.
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.h: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
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decides if this function accepts symbolic constants or not.
(parse_signed_bitbase): Likewise.
(parse_unsigned_bitbase8): Pass the new parameter.
(parse_unsigned_bitbase11): Likewise.
(parse_unsigned_bitbase16): Likewise.
(parse_unsigned_bitbase19): Likewise.
(parse_unsigned_bitbase27): Likewise.
(parse_signed_bitbase8): Likewise.
(parse_signed_bitbase11): Likewise.
(parse_signed_bitbase19): Likewise.
* m32c-asm.c: Regenerate.
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(btst:s): New.
* m32c.opc (parse_bit3_S): New.
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