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6_3-branch'.
Sprout from gdb_6_4-branch 2005-11-04 02:48:52 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_4-branch'.'
Cherrypick from gdb_6_4-branch 2005-11-01 22:57:24 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_4-branch'.':
gdb/README
Cherrypick from master 2005-11-17 00:00:02 UTC gdbadmin <gdbadmin@sourceware.org> '*** empty log message ***':
ChangeLog
Makefile.def
Makefile.in
Makefile.tpl
bfd/ChangeLog
bfd/archures.c
bfd/bfd-in2.h
bfd/bfdio.c
bfd/cache.c
bfd/config.in
bfd/configure
bfd/configure.host
bfd/configure.in
bfd/cpu-ms1.c
bfd/elf.c
bfd/elf32-ms1.c
bfd/elflink.c
bfd/elfxx-mips.c
bfd/elfxx-mips.h
bfd/libbfd-in.h
bfd/libbfd.h
bfd/opncls.c
bfd/reloc.c
bfd/version.h
bfd/warning.m4
configure
configure.in
cpu/ChangeLog
cpu/ms1.cpu
cpu/ms1.opc
gdb/ChangeLog
gdb/MAINTAINERS
gdb/Makefile.in
gdb/NEWS
gdb/arm-linux-tdep.c
gdb/cli/cli-script.c
gdb/doc/ChangeLog
gdb/doc/gdb.texinfo
gdb/dwarf2loc.c
gdb/dwarf2read.c
gdb/elfread.c
gdb/event-top.c
gdb/frv-linux-tdep.c
gdb/frv-tdep.c
gdb/gdbserver/ChangeLog
gdb/gdbserver/configure.srv
gdb/gdbserver/linux-arm-low.c
gdb/gdbserver/linux-x86-64-low.c
gdb/hppa-linux-nat.c
gdb/ia64-tdep.c
gdb/infrun.c
gdb/inftarg.c
gdb/interps.h
gdb/linux-nat.c
gdb/m32r-linux-tdep.c
gdb/m32r-tdep.c
gdb/m68hc11-tdep.c
gdb/main.c
gdb/main.h
gdb/monitor.c
gdb/ppc-sysv-tdep.c
gdb/remote-e7000.c
gdb/remote-m32r-sdi.c
gdb/sh-tdep.c
gdb/sh64-tdep.c
gdb/solib-frv.c
gdb/testsuite/ChangeLog
gdb/testsuite/gdb.arch/gdb1558.c
gdb/testsuite/gdb.asm/asm-source.exp
gdb/testsuite/gdb.asm/m68hc11.inc
gdb/testsuite/gdb.base/break.exp
gdb/testsuite/gdb.base/structs2.exp
gdb/thread.c
gdb/top.c
gdb/tui/tui-command.c
gdb/tui/tui-interp.c
gdb/tui/tui-win.c
gdb/version.in
include/ChangeLog
include/bfdlink.h
include/elf/ChangeLog
include/elf/hppa.h
include/elf/mips.h
include/elf/ms1.h
include/opcode/ChangeLog
include/opcode/mips.h
libiberty/ChangeLog
libiberty/splay-tree.c
opcodes/ChangeLog
opcodes/arm-dis.c
opcodes/configure
opcodes/i386-dis.c
opcodes/iq2000-desc.c
opcodes/iq2000-desc.h
opcodes/iq2000-dis.c
opcodes/iq2000-opc.c
opcodes/m32c-desc.c
opcodes/m68k-dis.c
opcodes/mips-dis.c
opcodes/mips16-opc.c
opcodes/ms1-asm.c
opcodes/ms1-desc.c
opcodes/ms1-desc.h
opcodes/ms1-dis.c
opcodes/ms1-ibld.c
opcodes/ms1-opc.c
opcodes/ms1-opc.h
opcodes/ppc-opc.c
sim/ChangeLog
sim/cris/cris-tmpl.c
sim/sh/ChangeLog
sim/sh/interp.c
Delete:
gdb/config/ms1/ms1.mt
gdb/config/v850/v850.mt
gdb/testsuite/gdb.ada/array_return/p.adb
gdb/testsuite/gdb.ada/array_return/pck.adb
gdb/testsuite/gdb.ada/array_return/pck.ads
gdb/testsuite/gdb.ada/arrayidx/p.adb
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Sprout from gdb-csl-arm-20051020-branch 2005-10-20 00:09:02 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb-csl-'
Cherrypick from master 2005-11-01 22:57:23 UTC Alan Modra <amodra@gmail.com> ' PR ld/1775':
ChangeLog
Makefile.def
Makefile.in
Makefile.tpl
bfd/ChangeLog
bfd/Makefile.am
bfd/Makefile.in
bfd/aoutx.h
bfd/archures.c
bfd/bfd-in2.h
bfd/bfdwin.c
bfd/cache.c
bfd/coff-rs6000.c
bfd/coff-z80.c
bfd/coff64-rs6000.c
bfd/coffcode.h
bfd/config.bfd
bfd/configure
bfd/configure.in
bfd/cpu-ia64-opc.c
bfd/cpu-z80.c
bfd/dep-in.sed
bfd/elf-bfd.h
bfd/elf.c
bfd/elf32-arm.c
bfd/elf32-bfin.c
bfd/elf32-cris.c
bfd/elf32-hppa.c
bfd/elf32-i370.c
bfd/elf32-i386.c
bfd/elf32-m32r.c
bfd/elf32-m68k.c
bfd/elf32-ppc.c
bfd/elf32-s390.c
bfd/elf32-sh.c
bfd/elf64-ppc.c
bfd/elf64-s390.c
bfd/elf64-x86-64.c
bfd/elflink.c
bfd/elfxx-ia64.c
bfd/elfxx-mips.c
bfd/elfxx-mips.h
bfd/elfxx-sparc.c
bfd/elfxx-sparc.h
bfd/hppabsd-core.c
bfd/hpux-core.c
bfd/libbfd-in.h
bfd/libbfd.c
bfd/libbfd.h
bfd/linker.c
bfd/osf-core.c
bfd/po/SRC-POTFILES.in
bfd/po/bfd.pot
bfd/reloc.c
bfd/rs6000-core.c
bfd/sco5-core.c
bfd/targets.c
bfd/trad-core.c
bfd/version.h
bfd/xcoff-target.h
cpu/ChangeLog
cpu/frv.opc
cpu/m32c.cpu
cpu/m32c.opc
cpu/m32r.opc
depcomp
etc/ChangeLog
etc/texi2pod.pl
gdb/ChangeLog
gdb/Makefile.in
gdb/NEWS
gdb/config/i386/tm-cygwin.h
gdb/config/iq2000/iq2000.mt
gdb/config/ms1/ms1.mt
gdb/doc/ChangeLog
gdb/doc/gdb.texinfo
gdb/doublest.c
gdb/dwarf2read.c
gdb/event-top.c
gdb/gdbserver/ChangeLog
gdb/gdbserver/linux-ia64-low.c
gdb/gdbserver/server.c
gdb/hppa-hpux-tdep.c
gdb/hppa-tdep.h
gdb/inf-ttrace.c
gdb/main.c
gdb/mi/gdb-mi.el
gdb/po/gdbtext
gdb/ppc-tdep.h
gdb/regformats/reg-ia64.dat
gdb/rs6000-tdep.c
gdb/testsuite/ChangeLog
gdb/testsuite/gdb.ada/array_return/p.adb
gdb/testsuite/gdb.ada/array_return/pck.adb
gdb/testsuite/gdb.ada/array_return/pck.ads
gdb/testsuite/gdb.ada/arrayidx/p.adb
gdb/testsuite/gdb.asm/asm-source.exp
gdb/testsuite/gdb.base/bfp-test.exp
gdb/tui/tui-command.c
gdb/tui/tui-data.c
gdb/tui/tui-data.h
gdb/tui/tui-disasm.c
gdb/tui/tui-layout.c
gdb/tui/tui-source.c
gdb/tui/tui-source.h
gdb/tui/tui-stack.c
gdb/tui/tui-win.c
gdb/tui/tui-winsource.c
gdb/tui/tui-winsource.h
gdb/vax-tdep.c
gdb/version.in
gdb/win32-nat.c
include/ChangeLog
include/coff/ChangeLog
include/coff/internal.h
include/coff/z80.h
include/dis-asm.h
include/elf/ChangeLog
include/floatformat.h
include/opcode/ChangeLog
include/opcode/cgen-bitset.h
include/opcode/cgen.h
include/opcode/ia64.h
libiberty/ChangeLog
libiberty/floatformat.c
opcodes/ChangeLog
opcodes/Makefile.am
opcodes/Makefile.in
opcodes/arm-dis.c
opcodes/bfin-dis.c
opcodes/cgen-dis.in
opcodes/cgen-opc.c
opcodes/configure
opcodes/configure.in
opcodes/dep-in.sed
opcodes/disassemble.c
opcodes/fr30-desc.c
opcodes/fr30-desc.h
opcodes/fr30-dis.c
opcodes/fr30-opc.c
opcodes/frv-desc.c
opcodes/frv-desc.h
opcodes/frv-dis.c
opcodes/frv-opc.c
opcodes/frv-opc.h
opcodes/ia64-asmtab.c
opcodes/ip2k-desc.c
opcodes/ip2k-desc.h
opcodes/ip2k-dis.c
opcodes/ip2k-opc.c
opcodes/m32c-asm.c
opcodes/m32c-desc.c
opcodes/m32c-desc.h
opcodes/m32c-dis.c
opcodes/m32c-ibld.c
opcodes/m32c-opc.c
opcodes/m32c-opc.h
opcodes/m32r-asm.c
opcodes/m32r-desc.c
opcodes/m32r-desc.h
opcodes/m32r-dis.c
opcodes/m32r-opc.c
opcodes/ms1-desc.c
opcodes/ms1-desc.h
opcodes/ms1-dis.c
opcodes/openrisc-desc.c
opcodes/openrisc-desc.h
opcodes/openrisc-dis.c
opcodes/openrisc-opc.c
opcodes/po/POTFILES.in
opcodes/po/opcodes.pot
opcodes/xstormy16-desc.c
opcodes/xstormy16-desc.h
opcodes/xstormy16-dis.c
opcodes/xstormy16-opc.c
opcodes/z80-dis.c
sim/frv/ChangeLog
sim/frv/arch.c
sim/frv/arch.h
sim/frv/cpu.c
sim/frv/cpu.h
sim/frv/cpuall.h
sim/frv/decode.c
sim/frv/decode.h
sim/frv/frv-sim.h
sim/frv/mloop.in
sim/frv/model.c
sim/frv/pipeline.c
sim/frv/sem.c
sim/frv/traps.c
Delete:
intl/ChangeLog
intl/Makefile.in
intl/acconfig.h
intl/aclocal.m4
intl/bindtextdom.c
intl/cat-compat.c
intl/config.in
intl/configure
intl/configure.in
intl/dcgettext.c
intl/dgettext.c
intl/explodename.c
intl/finddomain.c
intl/gettext.c
intl/gettext.h
intl/gettextP.h
intl/hash-string.h
intl/intl-compat.c
intl/intlh.inst.in
intl/l10nflist.c
intl/libgettext.h
intl/libintl.glibc
intl/linux-msg.sed
intl/loadinfo.h
intl/loadmsgcat.c
intl/localealias.c
intl/po2tbl.sed.in
intl/textdomain.c
intl/xopen-msg.sed
mmalloc/COPYING.LIB
mmalloc/ChangeLog
mmalloc/MAINTAINERS
mmalloc/Makefile.in
mmalloc/TODO
mmalloc/acinclude.m4
mmalloc/aclocal.m4
mmalloc/attach.c
mmalloc/configure
mmalloc/configure.in
mmalloc/detach.c
mmalloc/keys.c
mmalloc/mcalloc.c
mmalloc/mfree.c
mmalloc/mm.c
mmalloc/mmalloc.c
mmalloc/mmalloc.h
mmalloc/mmalloc.texi
mmalloc/mmap-sup.c
mmalloc/mmcheck.c
mmalloc/mmemalign.c
mmalloc/mmprivate.h
mmalloc/mmstats.c
mmalloc/mmtrace.awk
mmalloc/mmtrace.c
mmalloc/mrealloc.c
mmalloc/mvalloc.c
mmalloc/sbrk-sup.c
sim/sh64/ChangeLog
sim/sh64/Makefile.in
sim/sh64/arch.c
sim/sh64/arch.h
sim/sh64/config.in
sim/sh64/configure
sim/sh64/configure.ac
sim/sh64/cpu.c
sim/sh64/cpu.h
sim/sh64/cpuall.h
sim/sh64/decode-compact.c
sim/sh64/decode-compact.h
sim/sh64/decode-media.c
sim/sh64/decode-media.h
sim/sh64/decode.h
sim/sh64/defs-compact.h
sim/sh64/defs-media.h
sim/sh64/eng-compact.h
sim/sh64/eng-media.h
sim/sh64/eng.h
sim/sh64/mloop-compact.c
sim/sh64/mloop-media.c
sim/sh64/sem-compact-switch.c
sim/sh64/sem-compact.c
sim/sh64/sem-media-switch.c
sim/sh64/sem-media.c
sim/sh64/sh-desc.c
sim/sh64/sh-desc.h
sim/sh64/sh-opc.h
sim/sh64/sh64-sim.h
sim/sh64/sh64.c
sim/sh64/sim-if.c
sim/sh64/sim-main.h
sim/sh64/tconfig.in
sim/testsuite/sim/sh64/ChangeLog
sim/testsuite/sim/sh64/compact.exp
sim/testsuite/sim/sh64/compact/ChangeLog
sim/testsuite/sim/sh64/compact/add.cgs
sim/testsuite/sim/sh64/compact/addc.cgs
sim/testsuite/sim/sh64/compact/addi.cgs
sim/testsuite/sim/sh64/compact/addv.cgs
sim/testsuite/sim/sh64/compact/and.cgs
sim/testsuite/sim/sh64/compact/andb.cgs
sim/testsuite/sim/sh64/compact/andi.cgs
sim/testsuite/sim/sh64/compact/bf.cgs
sim/testsuite/sim/sh64/compact/bfs.cgs
sim/testsuite/sim/sh64/compact/bra.cgs
sim/testsuite/sim/sh64/compact/braf.cgs
sim/testsuite/sim/sh64/compact/brk.cgs
sim/testsuite/sim/sh64/compact/bsr.cgs
sim/testsuite/sim/sh64/compact/bsrf.cgs
sim/testsuite/sim/sh64/compact/bt.cgs
sim/testsuite/sim/sh64/compact/bts.cgs
sim/testsuite/sim/sh64/compact/clrmac.cgs
sim/testsuite/sim/sh64/compact/clrs.cgs
sim/testsuite/sim/sh64/compact/clrt.cgs
sim/testsuite/sim/sh64/compact/cmpeq.cgs
sim/testsuite/sim/sh64/compact/cmpeqi.cgs
sim/testsuite/sim/sh64/compact/cmpge.cgs
sim/testsuite/sim/sh64/compact/cmpgt.cgs
sim/testsuite/sim/sh64/compact/cmphi.cgs
sim/testsuite/sim/sh64/compact/cmphs.cgs
sim/testsuite/sim/sh64/compact/cmppl.cgs
sim/testsuite/sim/sh64/compact/cmppz.cgs
sim/testsuite/sim/sh64/compact/cmpstr.cgs
sim/testsuite/sim/sh64/compact/div0s.cgs
sim/testsuite/sim/sh64/compact/div0u.cgs
sim/testsuite/sim/sh64/compact/div1.cgs
sim/testsuite/sim/sh64/compact/dmulsl.cgs
sim/testsuite/sim/sh64/compact/dmulul.cgs
sim/testsuite/sim/sh64/compact/dt.cgs
sim/testsuite/sim/sh64/compact/extsb.cgs
sim/testsuite/sim/sh64/compact/extsw.cgs
sim/testsuite/sim/sh64/compact/extub.cgs
sim/testsuite/sim/sh64/compact/extuw.cgs
sim/testsuite/sim/sh64/compact/fabs.cgs
sim/testsuite/sim/sh64/compact/fadd.cgs
sim/testsuite/sim/sh64/compact/fcmpeq.cgs
sim/testsuite/sim/sh64/compact/fcmpgt.cgs
sim/testsuite/sim/sh64/compact/fcnvds.cgs
sim/testsuite/sim/sh64/compact/fcnvsd.cgs
sim/testsuite/sim/sh64/compact/fdiv.cgs
sim/testsuite/sim/sh64/compact/fipr.cgs
sim/testsuite/sim/sh64/compact/fldi0.cgs
sim/testsuite/sim/sh64/compact/fldi1.cgs
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sim/testsuite/sim/sh64/compact/float.cgs
sim/testsuite/sim/sh64/compact/fmac.cgs
sim/testsuite/sim/sh64/compact/fmov.cgs
sim/testsuite/sim/sh64/compact/fmul.cgs
sim/testsuite/sim/sh64/compact/fneg.cgs
sim/testsuite/sim/sh64/compact/frchg.cgs
sim/testsuite/sim/sh64/compact/fschg.cgs
sim/testsuite/sim/sh64/compact/fsqrt.cgs
sim/testsuite/sim/sh64/compact/fsts.cgs
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sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
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sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
sim/testsuite/sim/sh64/compact/lds-fpul.cgs
sim/testsuite/sim/sh64/compact/lds-mach.cgs
sim/testsuite/sim/sh64/compact/lds-macl.cgs
sim/testsuite/sim/sh64/compact/lds-pr.cgs
sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
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sim/testsuite/sim/sh64/compact/macw.cgs
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sim/testsuite/sim/sh64/compact/movb1.cgs
sim/testsuite/sim/sh64/compact/movb10.cgs
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sim/testsuite/sim/sh64/compact/movb9.cgs
sim/testsuite/sim/sh64/compact/movcal.cgs
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sim/testsuite/sim/sh64/compact/movl1.cgs
sim/testsuite/sim/sh64/compact/movl10.cgs
sim/testsuite/sim/sh64/compact/movl11.cgs
sim/testsuite/sim/sh64/compact/movl2.cgs
sim/testsuite/sim/sh64/compact/movl3.cgs
sim/testsuite/sim/sh64/compact/movl4.cgs
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sim/testsuite/sim/sh64/compact/nop.cgs
sim/testsuite/sim/sh64/compact/not.cgs
sim/testsuite/sim/sh64/compact/ocbi.cgs
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sim/testsuite/sim/sh64/compact/ori.cgs
sim/testsuite/sim/sh64/compact/pref.cgs
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sim/testsuite/sim/sh64/compact/stc-gbr.cgs
sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
sim/testsuite/sim/sh64/compact/sts-fpul.cgs
sim/testsuite/sim/sh64/compact/sts-mach.cgs
sim/testsuite/sim/sh64/compact/sts-macl.cgs
sim/testsuite/sim/sh64/compact/sts-pr.cgs
sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
sim/testsuite/sim/sh64/compact/stsl-mach.cgs
sim/testsuite/sim/sh64/compact/stsl-macl.cgs
sim/testsuite/sim/sh64/compact/stsl-pr.cgs
sim/testsuite/sim/sh64/compact/sub.cgs
sim/testsuite/sim/sh64/compact/subc.cgs
sim/testsuite/sim/sh64/compact/subv.cgs
sim/testsuite/sim/sh64/compact/swapb.cgs
sim/testsuite/sim/sh64/compact/swapw.cgs
sim/testsuite/sim/sh64/compact/tasb.cgs
sim/testsuite/sim/sh64/compact/testutils.inc
sim/testsuite/sim/sh64/compact/trapa.cgs
sim/testsuite/sim/sh64/compact/tst.cgs
sim/testsuite/sim/sh64/compact/tstb.cgs
sim/testsuite/sim/sh64/compact/tsti.cgs
sim/testsuite/sim/sh64/compact/xor.cgs
sim/testsuite/sim/sh64/compact/xorb.cgs
sim/testsuite/sim/sh64/compact/xori.cgs
sim/testsuite/sim/sh64/compact/xtrct.cgs
sim/testsuite/sim/sh64/interwork.exp
sim/testsuite/sim/sh64/media.exp
sim/testsuite/sim/sh64/media/ChangeLog
sim/testsuite/sim/sh64/media/add.cgs
sim/testsuite/sim/sh64/media/addi.cgs
sim/testsuite/sim/sh64/media/addil.cgs
sim/testsuite/sim/sh64/media/addl.cgs
sim/testsuite/sim/sh64/media/addzl.cgs
sim/testsuite/sim/sh64/media/alloco.cgs
sim/testsuite/sim/sh64/media/and.cgs
sim/testsuite/sim/sh64/media/andc.cgs
sim/testsuite/sim/sh64/media/andi.cgs
sim/testsuite/sim/sh64/media/beq.cgs
sim/testsuite/sim/sh64/media/beqi.cgs
sim/testsuite/sim/sh64/media/bge.cgs
sim/testsuite/sim/sh64/media/bgeu.cgs
sim/testsuite/sim/sh64/media/bgt.cgs
sim/testsuite/sim/sh64/media/bgtu.cgs
sim/testsuite/sim/sh64/media/blink.cgs
sim/testsuite/sim/sh64/media/bne.cgs
sim/testsuite/sim/sh64/media/bnei.cgs
sim/testsuite/sim/sh64/media/brk.cgs
sim/testsuite/sim/sh64/media/byterev.cgs
sim/testsuite/sim/sh64/media/cmpeq.cgs
sim/testsuite/sim/sh64/media/cmpgt.cgs
sim/testsuite/sim/sh64/media/cmpgtu.cgs
sim/testsuite/sim/sh64/media/cmveq.cgs
sim/testsuite/sim/sh64/media/cmvne.cgs
sim/testsuite/sim/sh64/media/fabsd.cgs
sim/testsuite/sim/sh64/media/fabss.cgs
sim/testsuite/sim/sh64/media/faddd.cgs
sim/testsuite/sim/sh64/media/fadds.cgs
sim/testsuite/sim/sh64/media/fcmpeqd.cgs
sim/testsuite/sim/sh64/media/fcmpeqs.cgs
sim/testsuite/sim/sh64/media/fcmpged.cgs
sim/testsuite/sim/sh64/media/fcmpges.cgs
sim/testsuite/sim/sh64/media/fcmpgtd.cgs
sim/testsuite/sim/sh64/media/fcmpgts.cgs
sim/testsuite/sim/sh64/media/fcmpund.cgs
sim/testsuite/sim/sh64/media/fcmpuns.cgs
sim/testsuite/sim/sh64/media/fcnvds.cgs
sim/testsuite/sim/sh64/media/fcnvsd.cgs
sim/testsuite/sim/sh64/media/fdivd.cgs
sim/testsuite/sim/sh64/media/fdivs.cgs
sim/testsuite/sim/sh64/media/fgetscr.cgs
sim/testsuite/sim/sh64/media/fiprs.cgs
sim/testsuite/sim/sh64/media/fldd.cgs
sim/testsuite/sim/sh64/media/fldp.cgs
sim/testsuite/sim/sh64/media/flds.cgs
sim/testsuite/sim/sh64/media/fldxd.cgs
sim/testsuite/sim/sh64/media/fldxp.cgs
sim/testsuite/sim/sh64/media/fldxs.cgs
sim/testsuite/sim/sh64/media/floatld.cgs
sim/testsuite/sim/sh64/media/floatls.cgs
sim/testsuite/sim/sh64/media/floatqd.cgs
sim/testsuite/sim/sh64/media/floatqs.cgs
sim/testsuite/sim/sh64/media/fmacs.cgs
sim/testsuite/sim/sh64/media/fmovd.cgs
sim/testsuite/sim/sh64/media/fmovdq.cgs
sim/testsuite/sim/sh64/media/fmovls.cgs
sim/testsuite/sim/sh64/media/fmovqd.cgs
sim/testsuite/sim/sh64/media/fmovs.cgs
sim/testsuite/sim/sh64/media/fmovsl.cgs
sim/testsuite/sim/sh64/media/fmuld.cgs
sim/testsuite/sim/sh64/media/fmuls.cgs
sim/testsuite/sim/sh64/media/fnegd.cgs
sim/testsuite/sim/sh64/media/fnegs.cgs
sim/testsuite/sim/sh64/media/fputscr.cgs
sim/testsuite/sim/sh64/media/fsqrtd.cgs
sim/testsuite/sim/sh64/media/fsqrts.cgs
sim/testsuite/sim/sh64/media/fstd.cgs
sim/testsuite/sim/sh64/media/fstp.cgs
sim/testsuite/sim/sh64/media/fsts.cgs
sim/testsuite/sim/sh64/media/fstxd.cgs
sim/testsuite/sim/sh64/media/fstxp.cgs
sim/testsuite/sim/sh64/media/fstxs.cgs
sim/testsuite/sim/sh64/media/fsubd.cgs
sim/testsuite/sim/sh64/media/fsubs.cgs
sim/testsuite/sim/sh64/media/ftrcdl.cgs
sim/testsuite/sim/sh64/media/ftrcdq.cgs
sim/testsuite/sim/sh64/media/ftrcsl.cgs
sim/testsuite/sim/sh64/media/ftrcsq.cgs
sim/testsuite/sim/sh64/media/ftrvs.cgs
sim/testsuite/sim/sh64/media/getcfg.cgs
sim/testsuite/sim/sh64/media/getcon.cgs
sim/testsuite/sim/sh64/media/gettr.cgs
sim/testsuite/sim/sh64/media/icbi.cgs
sim/testsuite/sim/sh64/media/ldb.cgs
sim/testsuite/sim/sh64/media/ldhil.cgs
sim/testsuite/sim/sh64/media/ldhiq.cgs
sim/testsuite/sim/sh64/media/ldl.cgs
sim/testsuite/sim/sh64/media/ldlol.cgs
sim/testsuite/sim/sh64/media/ldloq.cgs
sim/testsuite/sim/sh64/media/ldq.cgs
sim/testsuite/sim/sh64/media/ldub.cgs
sim/testsuite/sim/sh64/media/lduw.cgs
sim/testsuite/sim/sh64/media/ldw.cgs
sim/testsuite/sim/sh64/media/ldxb.cgs
sim/testsuite/sim/sh64/media/ldxl.cgs
sim/testsuite/sim/sh64/media/ldxq.cgs
sim/testsuite/sim/sh64/media/ldxub.cgs
sim/testsuite/sim/sh64/media/ldxuw.cgs
sim/testsuite/sim/sh64/media/ldxw.cgs
sim/testsuite/sim/sh64/media/mabsl.cgs
sim/testsuite/sim/sh64/media/mabsw.cgs
sim/testsuite/sim/sh64/media/maddl.cgs
sim/testsuite/sim/sh64/media/maddsl.cgs
sim/testsuite/sim/sh64/media/maddsub.cgs
sim/testsuite/sim/sh64/media/maddsw.cgs
sim/testsuite/sim/sh64/media/maddw.cgs
sim/testsuite/sim/sh64/media/mcmpeqb.cgs
sim/testsuite/sim/sh64/media/mcmpeql.cgs
sim/testsuite/sim/sh64/media/mcmpeqw.cgs
sim/testsuite/sim/sh64/media/mcmpgtl.cgs
sim/testsuite/sim/sh64/media/mcmpgtub.cgs
sim/testsuite/sim/sh64/media/mcmpgtw.cgs
sim/testsuite/sim/sh64/media/mcmv.cgs
sim/testsuite/sim/sh64/media/mcnvslw.cgs
sim/testsuite/sim/sh64/media/mcnvswb.cgs
sim/testsuite/sim/sh64/media/mcnvswub.cgs
sim/testsuite/sim/sh64/media/mextr1.cgs
sim/testsuite/sim/sh64/media/mextr2.cgs
sim/testsuite/sim/sh64/media/mextr3.cgs
sim/testsuite/sim/sh64/media/mextr4.cgs
sim/testsuite/sim/sh64/media/mextr5.cgs
sim/testsuite/sim/sh64/media/mextr6.cgs
sim/testsuite/sim/sh64/media/mextr7.cgs
sim/testsuite/sim/sh64/media/mmacfxwl.cgs
sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
sim/testsuite/sim/sh64/media/mmulfxl.cgs
sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
sim/testsuite/sim/sh64/media/mmulfxw.cgs
sim/testsuite/sim/sh64/media/mmulhiwl.cgs
sim/testsuite/sim/sh64/media/mmull.cgs
sim/testsuite/sim/sh64/media/mmullowl.cgs
sim/testsuite/sim/sh64/media/mmulsumwq.cgs
sim/testsuite/sim/sh64/media/mmulw.cgs
sim/testsuite/sim/sh64/media/movi.cgs
sim/testsuite/sim/sh64/media/mpermw.cgs
sim/testsuite/sim/sh64/media/msadubq.cgs
sim/testsuite/sim/sh64/media/mshaldsl.cgs
sim/testsuite/sim/sh64/media/mshaldsw.cgs
sim/testsuite/sim/sh64/media/mshardl.cgs
sim/testsuite/sim/sh64/media/mshardsq.cgs
sim/testsuite/sim/sh64/media/mshardw.cgs
sim/testsuite/sim/sh64/media/mshfhib.cgs
sim/testsuite/sim/sh64/media/mshfhil.cgs
sim/testsuite/sim/sh64/media/mshfhiw.cgs
sim/testsuite/sim/sh64/media/mshflob.cgs
sim/testsuite/sim/sh64/media/mshflol.cgs
sim/testsuite/sim/sh64/media/mshflow.cgs
sim/testsuite/sim/sh64/media/mshlldl.cgs
sim/testsuite/sim/sh64/media/mshlldw.cgs
sim/testsuite/sim/sh64/media/mshlrdl.cgs
sim/testsuite/sim/sh64/media/mshlrdw.cgs
sim/testsuite/sim/sh64/media/msubl.cgs
sim/testsuite/sim/sh64/media/msubsl.cgs
sim/testsuite/sim/sh64/media/msubsub.cgs
sim/testsuite/sim/sh64/media/msubsw.cgs
sim/testsuite/sim/sh64/media/msubw.cgs
sim/testsuite/sim/sh64/media/mulsl.cgs
sim/testsuite/sim/sh64/media/mulul.cgs
sim/testsuite/sim/sh64/media/nop.cgs
sim/testsuite/sim/sh64/media/nsb.cgs
sim/testsuite/sim/sh64/media/ocbi.cgs
sim/testsuite/sim/sh64/media/ocbp.cgs
sim/testsuite/sim/sh64/media/ocbwb.cgs
sim/testsuite/sim/sh64/media/or.cgs
sim/testsuite/sim/sh64/media/ori.cgs
sim/testsuite/sim/sh64/media/prefi.cgs
sim/testsuite/sim/sh64/media/pta.cgs
sim/testsuite/sim/sh64/media/ptabs.cgs
sim/testsuite/sim/sh64/media/ptb.cgs
sim/testsuite/sim/sh64/media/ptrel.cgs
sim/testsuite/sim/sh64/media/putcfg.cgs
sim/testsuite/sim/sh64/media/putcon.cgs
sim/testsuite/sim/sh64/media/rte.cgs
sim/testsuite/sim/sh64/media/shard.cgs
sim/testsuite/sim/sh64/media/shardl.cgs
sim/testsuite/sim/sh64/media/shari.cgs
sim/testsuite/sim/sh64/media/sharil.cgs
sim/testsuite/sim/sh64/media/shlld.cgs
sim/testsuite/sim/sh64/media/shlldl.cgs
sim/testsuite/sim/sh64/media/shlli.cgs
sim/testsuite/sim/sh64/media/shllil.cgs
sim/testsuite/sim/sh64/media/shlrd.cgs
sim/testsuite/sim/sh64/media/shlrdl.cgs
sim/testsuite/sim/sh64/media/shlri.cgs
sim/testsuite/sim/sh64/media/shlril.cgs
sim/testsuite/sim/sh64/media/shori.cgs
sim/testsuite/sim/sh64/media/sleep.cgs
sim/testsuite/sim/sh64/media/stb.cgs
sim/testsuite/sim/sh64/media/sthil.cgs
sim/testsuite/sim/sh64/media/sthiq.cgs
sim/testsuite/sim/sh64/media/stl.cgs
sim/testsuite/sim/sh64/media/stlol.cgs
sim/testsuite/sim/sh64/media/stloq.cgs
sim/testsuite/sim/sh64/media/stq.cgs
sim/testsuite/sim/sh64/media/stw.cgs
sim/testsuite/sim/sh64/media/stxb.cgs
sim/testsuite/sim/sh64/media/stxl.cgs
sim/testsuite/sim/sh64/media/stxq.cgs
sim/testsuite/sim/sh64/media/stxw.cgs
sim/testsuite/sim/sh64/media/sub.cgs
sim/testsuite/sim/sh64/media/subl.cgs
sim/testsuite/sim/sh64/media/swapq.cgs
sim/testsuite/sim/sh64/media/synci.cgs
sim/testsuite/sim/sh64/media/synco.cgs
sim/testsuite/sim/sh64/media/testutils.inc
sim/testsuite/sim/sh64/media/trapa.cgs
sim/testsuite/sim/sh64/media/xor.cgs
sim/testsuite/sim/sh64/media/xori.cgs
sim/testsuite/sim/sh64/misc/fr-dr.s
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* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
* elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16,
R_M32C_HI8, R_M32C_HI16.
(m32c_reloc_map): Likewise.
(m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16.
[cpu]
* m32c.opc (parse_unsigned8): Add %dsp8().
(parse_signed8): Add %hi8().
(parse_unsigned16): Add %dsp16().
(parse_signed16): Add %lo16() and %hi16().
(parse_lab_5_3): Make valuep a bfd_vma *.
[gas]
* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
Support %mod() modifiers from opcodes.
* doc/c-m32c.texi (M32C-Modifiers): New section.
[include/elf]
* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.
[opcodes]
* m32c-asm.c Regenerate.
* m32c-dis.c Regenerate.
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Restore alpha- sorting to the architecture tables.
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to represent isa sets.
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2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
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Contributed by Red Hat.
* ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
* ms1.opc: New file. Written by Stan Cox.
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2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* elf32-frv.c (elf32_frv_relocate_section): Force local binding
for TLSMOFF.
* reloc.c: Add R_FRV_TLSMOFF.
* elf32-frv.c (elf32_frv_howto_table): Likewise.
(frv_reloc_map, frv_reloc_type_lookup): Map it.
(elf32_frv_relocate_section): Handle it.
(elf32_frv_check_relocs): Likewise.
* libbfd.h, bfd-in2.h: Rebuilt.
2004-11-26 Alexandre Oliva <aoliva@redhat.com>
* elf32-frv.c (_frvfdpic_emit_got_relocs_plt_entries): Don't crash
when given an undefweak TLS symbol. Fix constant TLS PLT entries
such that they return the constant in gr9.
(_frvfdpic_relax_tls_entries): Don't crash for undefweak TLS
symbols.
(_frvfdpic_size_got_plt): Set _cooked_size of dynamic sections.
too, such that they shrink on relaxation.
(elf32_frvfdpic_finish_dynamic_sections): Check __ROFIXUP_END__ as
marking the position right past the _GLOBAL_OFFSET_TABLE_ value.
(_frvfdpic_assign_plt_entries): Shrink constant TLS PLT entries
if we can guarantee the use of 16-bit constants.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
Introduce TLS support for FR-V FDPIC.
* reloc.c: Add TLS relocations.
* elf32-frv.c (elf32_frv_howto_table): Add TLS relocations.
(elf32_frv_rel_tlsdesc_value_howto): New.
(elf32_frv_rel_tlsoff_howto): New.
(frv_reloc_map): Add new mappings.
(struct frvfdpic_elf_link_hash_table): Add pointer to summary
reloc information.
(frvfdpic_dynamic_got_plt_info): New.
(frvfdpic_plt_tls_ret_offset): New.
(ELF_DYNAMIC_INTERPRETER, DEFAULT_STACK_SIZE): Move earlier.
(struct _frvfdpic_dynamic_got_info): Likewise. Add TLS members.
(struct _frvfdpic_dynamic_got_plt_info): Likewise.
(FRVFDPIC_SYM_LOCAL): Regard symbols defined in the absolute
section as local.
(struct frvfdpic_relocs_info): Add TLS fields.
(frvfdpic_relocs_info_hash): Warning clean up.
(frvfdpic_relocs_info_find): Initialize tlsplt_entry.
(frvfdpic_pic_merge_early_relocs_info): Merge TLS fields.
(FRVFDPIC_TLS_BIAS): Define.
(tls_biased_base): New.
(_frvfdpic_emit_got_relocs_plt_entries): Deal with TLS
relocations.
(frv_reloc_type_lookup): Likewise.
(frvfdpic_info_to_howto_rel): Likewise.
(elf32_frv_relocate_section): Likewise.
(_frv_create_got_section): Create the PLT section here.
(elf32_frvfdpic_create_dynamic_sections): Not here.
(_frvfdpic_count_nontls_entries): Move out of...
(_frvfdpic_count_got_plt_entries): ... here.
(_frvfdpic_count_tls_entries): Likewise. Add TLS support.
(_frvfdpic_count_relocs_fixups): Likewise. Add relaxation
support.
(_frvfdpic_relax_tls_entries): New.
(_frvfdpic_compute_got_alloc_data): Add TLS support.
(_frvfdpic_get_tlsdesc_entry): New.
(_frvfdpic_assign_got_entries): Add TLS support.
(_frvfdpic_assign_plt_entries): Likewise.
(_frvfdpic_reset_got_plt_entries): New.
(_frvfdpic_size_got_plt): Move out of...
(elf32_frvfdpic_size_dynamic_sections): ... here.
(_frvfdpic_relax_got_plt_entries): New.
(elf32_frvfdpic_relax_section): New.
(elf32_frvfdpic_finish_dynamic_sections): Add TLS sanity check.
(elf32_frv_check_relocs): Add TLS support.
(bfd_elf32_bfd_relax_section): Define for FDPIC.
* libbfd.h, bfd-in2.h: Rebuilt.
cpu/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv.cpu: Add support for TLS annotations in loads and calll.
* frv.opc (parse_symbolic_address): New.
(parse_ldd_annotation): New.
(parse_call_annotation): New.
(parse_ld_annotation): New.
(parse_ulo16, parse_uslo16): Use parse_symbolic_address.
Introduce TLS relocations.
(parse_d12, parse_s12, parse_u12): Likewise.
(parse_uhi16): Likewise. Fix constant checking on 64-bit host.
(parse_call_label, print_at): New.
gas/ChangeLog:
* config/tc-frv.c (md_apply_fix3): Mark TLS symbols as such.
2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* config/tc-frv.c (frv_pic_ptr): Add tlsmoff support.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* cgen.c (gas_cgen_parse_operand): Handle
CGEN_PARSE_OPERAND_SYMBOLIC.
* config/tc-frv.c (md_cgen_lookup_reloc): Handle TLS relocations.
(frv_force_relocation): Likewise. Fix handling of PIC
relocations.
(md_apply_fix3): Likewise.
include/elf/ChangeLog:
2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* frv.h: Add R_FRV_TLSMOFF.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv.h: Add TLS relocations.
include/opcode/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* cgen.h (enum cgen_parse_operand_type): Add
CGEN_PARSE_OPERAND_SYMBOLIC.
ld/testsuite/ChangeLog:
* ld-frv/fdpic.exp: Add -mfdpic to ASFLAGS.
* ld-frv/tls.exp: Likewise.
2004-11-26 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/tls-3.s: New.
* ld-frv/tls-static-3.d: New.
* ld-frv/tls-dynamic-3.d: New.
* ld-frv/tls-pie-3.d: New.
* ld-frv/tls-shared-3.d: New.
* ld-frv/tls-relax-static-3.d: New.
* ld-frv/tls-relax-dynamic-3.d: New.
* ld-frv/tls-relax-pie-3.d: New.
* ld-frv/tls-relax-shared-3.d: New.
* ld-frv/tls.exp: Run the new tests.
* ld-frv/tls-dynamic-2.d: Adjust for improved relaxation.
* ld-frv/tls-relax-dynamic-2.d: Likewise.
* ld-frv/tls-relax-initial-shared-2.d: Likewise.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/tls-1-dep.s: New.
* ld-frv/tls-1-shared.lds: New.
* ld-frv/tls-1.s: New.
* ld-frv/tls-2.s: New.
* ld-frv/tls-dynamic-1.d: New.
* ld-frv/tls-dynamic-2.d: New.
* ld-frv/tls-initial-shared-2.d: New.
* ld-frv/tls-pie-1.d: New.
* ld-frv/tls-relax-dynamic-1.d: New.
* ld-frv/tls-relax-dynamic-2.d: New.
* ld-frv/tls-relax-initial-shared-2.d: New.
* ld-frv/tls-relax-pie-1.d: New.
* ld-frv/tls-relax-shared-1.d: New.
* ld-frv/tls-relax-shared-2.d: New.
* ld-frv/tls-relax-static-1.d: New.
* ld-frv/tls-shared-1-fail.d: New.
* ld-frv/tls-shared-1.d: New.
* ld-frv/tls-shared-2.d: New.
* ld-frv/tls-static-1.d: New.
* ld-frv/tls.exp: New.
* ld-frv/fdpic-pie-1.d: Adjust for 64-bit host.
* ld-frv/fdpic-pie-2.d: Likewise.
* ld-frv/fdpic-pie-6.d: Likewise.
* ld-frv/fdpic-pie-7.d: Likewise.
* ld-frv/fdpic-pie-8.d: Likewise.
* ld-frv/fdpic-shared-1.d: Likewise.
* ld-frv/fdpic-shared-2.d: Likewise.
* ld-frv/fdpic-shared-3.d: Likewise.
* ld-frv/fdpic-shared-4.d: Likewise.
* ld-frv/fdpic-shared-5.d: Likewise.
* ld-frv/fdpic-shared-6.d: Likewise.
* ld-frv/fdpic-shared-7.d: Likewise.
* ld-frv/fdpic-shared-8.d: Likewise.
* ld-frv/fdpic-shared-local-2.d: Likewise.
* ld-frv/fdpic-shared-local-8.d: Likewise.
* ld-frv/fdpic-static-1.d: Likewise.
* ld-frv/fdpic-static-2.d: Likewise.
* ld-frv/fdpic-static-6.d: Likewise.
* ld-frv/fdpic-static-7.d: Likewise.
* ld-frv/fdpic-static-8.d: Likewise.
opcodes/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv-asm.c: Rebuilt.
* frv-desc.c: Rebuilt.
* frv-desc.h: Rebuilt.
* frv-dis.c: Rebuilt.
* frv-ibld.c: Rebuilt.
* frv-opc.c: Rebuilt.
* frv-opc.h: Rebuilt.
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of guile.
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* frv.cpu (cfmovs): Change UNIT attribute to FMALL.
opcodes/
* frv-desc.[ch], frv-opc.[ch]: Regenerated.
gas/testsuite/
* gas/frv/fr550-pack1.[sd]: New test.
* gas/frv/allinsn.exp: Run it.
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* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
opcodes/
* frv-desc.c, frv-opc.c: Regenerate.
sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
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* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
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* m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
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* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
written by Ben Elliston.
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* frv.cpu (UNIT): Add IACC.
(iacc-multiply-r-r): Use it.
* frv.opc (fr400_unit_mapping): Add entry for IACC.
(fr500_unit_mapping, fr550_unit_mapping): Likewise.
opcodes/
* frv-desc.h: Regenerate.
* frv-desc.c: Regenerate.
* frv-opc.c: Regenerate.
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* frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
cut&paste errors in shifting/truncating numerical operands.
2003-08-08 Alexandre Oliva <aoliva@redhat.com>
* frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
(parse_s12): Likewise.
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
* frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gothi and gotfuncdeschi.
(parse_d12): Parse got12 and gotfuncdesc12.
(parse_s12): Likewise.
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* frv.cpu (dnpmop): New p-macro.
(GRdoublek): Use dnpmop.
(CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
(store-double-r-r): Use (.sym regtype doublek).
(r-store-double): Ditto.
(store-double-r-r-u): Ditto.
(conditional-store-double): Ditto.
(conditional-store-double-u): Ditto.
(store-double-r-simm): Ditto.
(fmovs): Assign to UNIT FMALL.
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* frv.cpu, frv.opc: Add support for fr550.
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* frv.cpu (u-commit): New modelling unit for fr500.
(mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
(commit-r): Use u-commit model for fr500.
(commit): Ditto.
(conditional-float-binary-op): Take profiling data as an argument.
Update callers.
(ne-float-binary-op): Ditto.
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* frv.cpu (nldqi): Delete unimplemented instruction.
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* frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
(clear-ne-flag-r): Pass insn profiling in as an argument. Call
frv_ref_SI to get input register referenced for profiling.
(clear-ne-flag-all): Pass insn profiling in as an argument.
(clrgr,clrfr,clrga,clrfa): Add profiling information.
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* frv.cpu: Typographical corrections.
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* frv.cpu (media-dual-complex): Change UNIT to FMALL.
(conditional-media-dual-complex, media-quad-complex): Likewise.
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* frv.cpu (register-transfer): Pass in all attributes in on argument.
Update all callers.
(conditional-register-transfer): Ditto.
(cache-preload): Ditto.
(floating-point-conversion): Ditto.
(floating-point-neg): Ditto.
(float-abs): Ditto.
(float-binary-op-s): Ditto.
(conditional-float-binary-op): Ditto.
(ne-float-binary-op): Ditto.
(float-dual-arith): Ditto.
(ne-float-dual-arith): Ditto.
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* frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
* frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
MCLRACC-1.
(A): Removed operand.
(A0,A1): New operands replace operand A.
(mnop): Now a real insn
(mclracc): Removed insn.
(mclracc-0, mclracc-1): New insns replace mclracc.
(all insns): Use new UNIT attributes.
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with output parameter.
(cmbtoh): Add profiling hack.
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Contributed by Red Hat.
* iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
Stan Cox, and Frank Ch. Eigler.
* iq2000.opc: New file. Written by Ben Elliston, Frank
Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
* iq2000m.cpu: New file. Written by Jeff Johnston.
* iq10.cpu: New file. Written by Jeff Johnston.
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