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2020-02-03ubsan: m32c: left shift of negative valueAlan Modra1-0/+4
2020-02-01ubsan: frv: left shift of negative valueAlan Modra1-0/+5
2020-01-30ubsan: m32c: left shift of negative valueAlan Modra1-0/+12
2020-01-30cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi1-0/+6
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-13ubsan: fr30: left shift of negative valueAlan Modra1-0/+5
2020-01-06ubsan: m32c: left shift of negative valueAlan Modra1-1/+10
2020-01-04ubsan: m32r: left shift of negative valueAlan Modra1-0/+5
2019-12-23ubsan: iq2000: left shift of negative valueAlan Modra1-0/+4
2019-12-20ubsan: or1k: left shift of negative valueAlan Modra1-0/+4
2019-12-17ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')Alan Modra1-0/+4
2019-12-16ubsan: xstormy16: left shift of negative valueAlan Modra1-0/+4
2019-12-11Remove more shifts for sign/zero extensionAlan Modra1-0/+6
2019-12-11ubsan: epiphany: left shift of negative valueAlan Modra1-0/+5
2019-11-20cpu: fix comment in bpf.cpuJose E. Marchesi1-0/+4
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell1-0/+4
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi1-0/+5
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-0/+5
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi1-0/+5
2019-06-13cpu/or1k: Update fpu compare symbols to imply set flagStafford Horne1-0/+4
2019-06-13cpu/or1k: Document no branch delay slot architectures and l.adrpStafford Horne1-0/+5
2019-06-13cpu/or1k: Define unordered comparisonsStafford Horne1-0/+12
2019-06-13cpu/or1k: Add support for orfp64a32 specStafford Horne1-0/+35
2019-05-23cpu: add eBPF cpu descriptionJose E. Marchesi1-0/+5
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson1-0/+13
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+14
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson1-0/+14
2018-07-24PR23430, Indices misspelledAlan Modra1-0/+5
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra1-0/+4
2018-03-03opcodes error messagesAlan Modra1-0/+7
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2017-03-20Update the openrisc previous program counter (ppc) when running code in the c...Stafford Horne1-0/+4
2016-10-06Add fall through comment to source in cpu/Alan Modra1-0/+4
2016-03-03Correct fr30 commentAlan Modra1-0/+5
2016-03-02Fix shift left warning at sourceAlan Modra1-0/+4
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess1-0/+5
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-7/+7
2014-07-20or1k: add missing l.msync, l.psync and l.psync instructions.Stefan Kristiansson1-0/+4
2014-06-12Whitespace fixes for cpu/or1k.opcAlan Modra1-0/+4
2014-05-08or1k: add support for l.swa/l.lwa atomic instructionsStefan Kristiansson1-0/+12
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson1-0/+10
2013-12-07strip off +x bits on non-executable/script filesMike Frysinger1-0/+4
2013-03-08 PR binutils/15241Nick Clifton1-0/+6
2012-12-10Add copyright noticesNick Clifton1-0/+6
2012-11-302012-11-30 Oleg Raikhman <oleg@adapteva.com>Joern Rennecke1-0/+18
2012-02-27cpu/Alan Modra1-0/+4
2011-12-15 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bitNick Clifton1-0/+5
2011-10-26cpu:Joern Rennecke1-0/+6
2011-10-25bfd:Nick Clifton1-0/+5
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