aboutsummaryrefslogtreecommitdiff
path: root/binutils
AgeCommit message (Collapse)AuthorFilesLines
2017-07-02DWARF-5: readelf: .debug_namesJan Kratochvil4-1/+376
Display DWARF-5 .debug_names (standardized .gdb_index). binutils/ChangeLog 2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com> * dwarf.c: Include assert.h. (MAX, MIN, get_IDX_name, display_debug_names): New. (debug_displays): Add .debug_names. * dwarf.h: (enum dwarf_section_display_enum): Add debug_names. * readelf.c (process_section_headers): Add ".debug_names".
2017-07-02Use bfd_malloc_and_get_sectionAlan Modra4-43/+25
It's nicer than xmalloc followed by bfd_get_section_contents, since xmalloc exits on failure and needs a check that its size_t arg doesn't lose high bits when converted from bfd_size_type. PR binutils/21665 * objdump.c (strtab): Make var a bfd_byte*. (disassemble_section): Don't limit malloc size. Instead, use bfd_malloc_and_get_section. (read_section_stabs): Use bfd_malloc_and_get_section. Return bfd_byte*. (find_stabs_section): Remove now unnecessary cast. * objcopy.c (copy_object): Use bfd_malloc_and_get_section. Free contents on error return. * nlmconv.c (copy_sections): Use bfd_malloc_and_get_section.
2017-06-30Fix failures in MMIX linker tests introduced by fix for PR 21665.Nick Clifton2-1/+32
PR binutils/21665 * objdump.c (disassemble_section): Move check for an overlarge section to just before the allocation of memory. Do not check section size against file size, but instead use an arbitrary 2Gb limit. Issue a warning message if the section is too big.
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki2-0/+7
Add support for the base and Virtualization ASE microMIPS instructions as per the architecture specifications[1][2][3][4]. Most of this change by Andrew Bennett. [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", p. 340 [2] "microMIPS32 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00848, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 133, 136 [3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 415, 444 [4] "microMIPS64 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00849, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140 binutils/ * NEWS: Mention microMIPS XPA support. opcodes/ * micromips-opc.c (XPA, XPAVZ): New macros. (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_ases): Add microMIPS XPA support. * testsuite/gas/mips/micromips@xpa.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. Enable `xpa-virt-err' test for `micromips'.
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki2-0/+7
Add base microMIPS Release 5 ISA support and the ERETNC instruction in particular, as per the architecture specifications[1][2]. Most of this change by Andrew Bennett. References: [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 266-267 [2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 326-327 binutils/ * NEWS: Mention microMIPS Release 5 ISA support. opcodes/ * micromips-opc.c (I36): New macro. (micromips_opcodes): Add "eretnc". gas/ * testsuite/gas/mips/micromips@r5.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki7-0/+79
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov3-17/+70
There is a bug in handling of cpu=... disassembler option in case there are other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is treated as an option value, and strcasecmp reports is as non-equal to "EM". This is fixed by using disassembler_options_cmp function, which compares string treating `,' the same way as `\0'. This function also solves a problem with option order in parse_option. Previously, if several option had same prefix (e.g. fpud, fpuda), then the longer one should have been compared first, otherwise when longer option is passed it would be treated as a short one, because CONST_STRNEQ ("fpud", "fpuda") would be true. The order of options was correct for ARC, so there were no bugs per se, but with disassembler_option_cmp there is no risk of such a bug being introduced in the future. opcodes/ChangeLog: yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com> * arc-dis.c (parse_option): Use disassembler_options_cmp to compare disassembler option strings. (parse_cpu_option): Likewise. binutils/ChangeLog yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com> * testsuite/binutils-all/arc/double_store.s: New file. * testsuite/binutils-all/arc/objdump.exp: Tests for disassembler options. (do_objfile): New function. (check_assembly): Likewise.
2017-06-29S390: Support guarded-storage core note sectionsAndreas Arnez2-0/+8
Newer Linux kernel versions offer two new register sets in support of the z/Architecture's guarded storage facility: NT_S390_GS_CB, the "guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage broadcast control block". This patch adds support for the respective core notes sections to binutils. bfd/ChangeLog: * elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype. (elfcore_write_s390_gs_bc): Likewise. * elf.c (elfcore_grok_s390_gs_cb): New function. (elfcore_grok_s390_gs_bc): New function. (elfcore_grok_note): Call them. (elfcore_write_s390_gs_cb): New function. (elfcore_write_s390_gs_bc): New function. (elfcore_write_register_note): Call them. binutils/ChangeLog: * readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC. include/ChangeLog: * elf/common.h (NT_S390_GS_CB): New macro. (NT_S390_GS_BC): Likewise.
2017-06-28Change bfd_get_size/bfd_get_file_size to ufile_ptrH.J. Lu2-1/+6
bfd_get_size and bfd_get_file_size should return the unsigned file size. Otherwise they return negative values for file >= 2GB with 32-bit ufile_ptr. bfd/ * bfd-in2.h: Regenerated. * bfdio.c (bfd_get_size): Change return type to ufile_ptr. (bfd_get_file_size): Likewise. binutils/ * objdump.c (dump_relocs_in_section): Cast to ufile_ptr when comparing against bfd_get_file_size return.
2017-06-28Add support for version 2 of the GNU Build Attribute note specification.Nick Clifton3-30/+65
* objcopy.c (merge_gnu_build_notes): Add support for version 2 notes. * readelf.c (print_gnu_build_attribute_name): Likewise.
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki3-0/+15
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-26Fix address violations when atempting to parse fuzzed binaries.Nick Clifton2-2/+8
PR binutils/21665 bfd * opncls.c (get_build_id): Check that the section is beig enough to contain the whole note. * compress.c (bfd_get_full_section_contents): Check for and reject a section whoes size is greater than the size of the entire file. * elf32-v850.c (v850_elf_copy_notes): Allow for the ouput to not contain a notes section. binutils* objdump.c (disassemble_section): Skip any section that is bigger than the entire file.
2017-06-26Produce a consistent warning message when attempting to run a tool on a ↵Nick Clifton2-0/+8
directory. PR binutils/21659 * bucomm.c (get_file_size): Explicitly warn if the file is a directory.
2017-06-26Add pgste marker changelogAndreas Krebbel1-0/+6
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme2-1/+5
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro.
2017-06-23Make the strings utility reject directories.Nick Clifton2-0/+11
PR binutils/21659 * strings.c (strings_file): Warn about attempts to run strings on a directory.
2017-06-23S/390: Add support for pgste markerAndreas Krebbel1-0/+14
This patch adds a new S/390 specific segment type: PT_S390_PGSTE. For binaries marked with that segment the kernel will allocate 4k page tables. The only user so far will be qemu. ld/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * Makefile.in: Add s390.em as build dependency. * emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em. * emultempl/s390.em: New file. * gen-doc.texi: Add documentation for --s390-pgste option. * ld.texinfo: Likewise. include/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf/s390.h (PT_S390_PGSTE): Define macro. binutils/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * readelf.c (get_s390_segment_type): Add support for the new segment type PT_S390_PGSTE. (get_segment_type): Call get_s390_segment_type. elfcpp/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elfcpp.h (enum PT): Add PT_S390_PGSTE to enum. bfd/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf-s390.h: New file. * elf64-s390.c (struct elf_s390_link_hash_table): Add params field. (elf_s390_additional_program_headers): New function. (elf_s390_modify_segment_map): New function. (bfd_elf_s390_set_options): New function. (elf_backend_additional_program_headers) (elf_backend_modify_segment_map): Add macro definitions.
2017-06-22x86: Support Intel Shadow Stack with SHSTK propertyH.J. Lu7-0/+103
To support Intel Shadow Stack (SHSTK) in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) is added to GNU program properties to indicate that all executable sections are compatible with SHSTK where return address popped from shadow stack always matches return address popped from normal stack. GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all relocatable inputs. bfd/ * elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_i386_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. * elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_x86_64_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. binutils/ * readelf.c (decode_x86_feature): Decode GNU_PROPERTY_X86_FEATURE_1_SHSTK. * testsuite/binutils-all/i386/shstk.d: New file. * testsuite/binutils-all/i386/shstk.s: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. * testsuite/binutils-all/x86-64/shstk.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add shstk. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New. ld/ * NEWS: Mention -z shstk and GNU_PROPERTY_X86_FEATURE_1_SHSTK. * emulparams/cet.sh (PARSE_AND_LIST_OPTIONS_CET): Add "-z shstk". (PARSE_AND_LIST_ARGS_CASE_Z_CET): Support "-z shstk". * ld.texinfo: Document -z shstk. * testsuite/ld-i386/i386.exp: Run SHSTK tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/property-x86-shstk.s: New file. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk.s: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
2017-06-22x86: Support Intel IBT with IBT property and IBT-enable PLTH.J. Lu12-0/+218
To support IBT in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 #define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) are added to GNU program properties to indicate that all executable sections are compatible with IBT when ENDBR instruction starts each valid target where an indirect branch instruction can land. GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on all relocatable inputs. The followings changes are made to the Procedure Linkage Table (PLT): 1. For 64-bit x86-64, PLT is changed to PLT0: push GOT[1] bnd jmp *GOT[2] nop ... PLTn: endbr64 push namen_reloc_index bnd jmp PLT0 together with the second PLT section: PLTn: endbr64 bnd jmp *GOT[namen_index] nop BND prefix is also added so that IBT-enabled PLT is compatible with MPX. 2. For 32-bit x86-64 (x32) and i386, PLT is changed to PLT0: push GOT[1] jmp *GOT[2] nop ... PLTn: endbr64 # endbr32 for i386. push namen_reloc_index jmp PLT0 together with the second PLT section: PLTn: endbr64 # endbr32 for i386. jmp *GOT[namen_index] nop BND prefix isn't used since MPX isn't supported on x32 and BND registers aren't used in parameter passing on i386. GOT is an array of addresses. Initially, GOT[namen_index] is filled with the address of the ENDBR instruction of the corresponding entry in the first PLT section. The function, namen, is called via the ENDBR instruction in the second PLT entry. GOT[namen_index] is updated to the actual address of the function, namen, at run-time. 2 linker command line options are added: 1. -z ibtplt: Generate IBT-enabled PLT. 2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program properties as well as IBT-enabled PLT. bfd/ * elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New. (elf_i386_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_lazy_ibt_plt0_entry): Likewise. (elf_i386_non_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_non_lazy_ibt_plt_entry): Likewise. (elf_i386_eh_frame_lazy_ibt_plt): Likewise. (elf_i386_lazy_plt_layout): Likewise. (elf_i386_non_lazy_plt_layout): Likewise. (elf_i386_link_hash_entry): Add plt_second. (elf_i386_link_hash_table): Add plt_second and plt_second_eh_frame. (elf_i386_allocate_dynrelocs): Use the second PLT if needed. (elf_i386_size_dynamic_sections): Use .plt.got unwind info for the second PLT. Check the second PLT. (elf_i386_relocate_section): Use the second PLT to resolve PLT reference if needed. (elf_i386_finish_dynamic_symbol): Fill and use the second PLT if needed. (elf_i386_finish_dynamic_sections): Set sh_entsize on the second PLT. Generate unwind info for the second PLT. (elf_i386_plt_type): Add plt_second. (elf_i386_get_synthetic_symtab): Support the second PLT. (elf_i386_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_i386_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_i386_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. * elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New. (elf_x32_lazy_ibt_plt_entry): Likewise. (elf_x86_64_non_lazy_ibt_plt_entry): Likewise. (elf_x32_non_lazy_ibt_plt_entry): Likewise. (elf_x86_64_eh_frame_lazy_ibt_plt): Likewise. (elf_x32_eh_frame_lazy_ibt_plt): Likewise. (elf_x86_64_lazy_ibt_plt): Likewise. (elf_x32_lazy_ibt_plt): Likewise. (elf_x86_64_non_lazy_ibt_plt): Likewise. (elf_x32_non_lazy_ibt_plt): Likewise. (elf_x86_64_get_synthetic_symtab): Support the second PLT. (elf_x86_64_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_x86_64_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_x86_64_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. binutils/ * readelf.c (decode_x86_feature): New. (print_gnu_property_note): Call decode_x86_feature on GNU_PROPERTY_X86_FEATURE_1_AND. * testsuite/binutils-all/i386/empty.d: New file. * testsuite/binutils-all/i386/empty.s: Likewise. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/ibt.s: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/empty.s: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/ibt.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add ibtplt and ibt. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New. (GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh. * Makefile.in: Regenerated. * NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt and -z ibt. * emulparams/cet.sh: New file. * testsuite/ld-i386/ibt-plt-1.d: Likewise. * testsuite/ld-i386/ibt-plt-1.s: Likewise. * testsuite/ld-i386/ibt-plt-2.s: Likewise. * testsuite/ld-i386/ibt-plt-2a.d: Likewise. * testsuite/ld-i386/ibt-plt-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3.s: Likewise. * testsuite/ld-i386/ibt-plt-3a.d: Likewise. * testsuite/ld-i386/ibt-plt-3b.d: Likewise. * testsuite/ld-i386/ibt-plt-3c.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/plt-main-ibt.dd: Likewise. * testsuite/ld-i386/plt-pie-ibt.dd: Likewise. * testsuite/ld-i386/property-x86-empty.s: Likewise. * testsuite/ld-i386/property-x86-ibt.s: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3.s: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise. * testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise. * testsuite/ld-x86-64/plt-main-ibt.dd: Likewise. * testsuite/ld-x86-64/property-x86-empty.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * emulparams/elf32_x86_64.sh: Source emulparams/cet.sh. (TINY_READONLY_SECTION): Add .plt.sec. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Source emulparams/cet.sh. * ld.texinfo: Document -z ibtplt and -z ibt. * testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
2017-06-21Use DWARF_VMA_FMT to report errorH.J. Lu2-2/+7
Use DWARF_VMA_FMT to report error to work for both 32-bit and 64-bit builds. * dwarf.c (READ_ULEB): Use DWARF_VMA_FMT to report error. (READ_SLEB): Likewise.
2017-06-21Fix address violation when reading corrupt DWARF data.Nick Clifton2-58/+106
PR binutils/21648 * dwarf.c (LEB): Rename to SKIP_ULEB and READ_ULEB. Add check for reading a value that is too big for the containing variable. (SLEB): Rename to SKIP_SLEB and READ_SLEB. Add similar check. Replace uses of LEB and SLEB with appropriate new macro. (display_debug_frames): Use an unsigned int for the 'reg' variable. Use a signed long for the 'l' variable.
2017-06-19Fix address violation when attempting to display disassembled data.Nick Clifton2-12/+21
PR binutils/21619 * objdump.c (disassemble_bytes): Check that there is sufficient data available before attempting to display it.
2017-06-14Fix address violation when disassembling a corrupt binary.Nick Clifton1-12/+15
PR binutils/21580 binutils * objdump.c (disassemble_bytes): Check for buffer overrun when printing out rae insns. ld * testsuite/ld-nds32/diff.d: Adjust expected output.
2017-06-06Fix memory leaks in the sysinfo program.Simon Marchi2-1/+18
* sysinfo.y: Free memory allocated by token NAME.
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov2-0/+12
Currently print_insn_arc relies on BFD mach and ELF private headers to distinguish between various ARC architectures. Sometimes those values are not correct or available, mainly in the case of debugging targets without and ELF file available. Changing a BFD mach is not a problem for the debugger, because this is a generic BFD field, and GDB, for example, already sets it according to information provided in XML target description or specified via GDB 'set arch' command. However, things are more complicated for ELF private headers, since it requires existing of an actual ELF file. To workaround this problem this patch allows CPU model to be specified via disassemble info options. If CPU is specified in options, then it will take a higher precedence than whatever might be specified in ELF file. This is mostly needed for ARC EM and ARC HS, because they have the same "architecture" (mach) ARCv2 and differ in their private ELF headers. Other ARC architectures can be distinguished between each other purely via "mach" field. Proposed disassemble option format is "cpu=<CPU>", where CPU can be any valid ARC CPU name as supported by GAS. Note that this creates a seeming redundancy with objdump -m/--architecture option, however -mEM and -mHS still result in "ARCv2" architecture internally, while -Mcpu={HS,EM} would have an actual effect on disassembler. opcodes/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (enforced_isa_mask): Declare. (cpu_types): Likewise. (parse_cpu_option): New function. (parse_disassembler_options): Use it. (print_insn_arc): Use enforced_isa_mask. (print_arc_disassembler_options): Document new options. binutils/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * doc/binutils.texi: Document new cpu=... disassembler options for ARC.
2017-05-30Add bfd_get_file_size to get archive element sizeH.J. Lu3-54/+139
We can't use stat() to get archive element size. Add bfd_get_file_size to get size for both normal files and archive elements. bfd/ PR binutils/21519 * bfdio.c (bfd_get_file_size): New function. * bfd-in2.h: Regenerated. binutils/ PR binutils/21519 * objdump.c (dump_relocs_in_section): Replace get_file_size with bfd_get_file_size to get archive element size. * testsuite/binutils-all/objdump.exp (test_objdump_f): New proc. (test_objdump_h): Likewise. (test_objdump_t): Likewise. (test_objdump_r): Likewise. (test_objdump_s): Likewise. Add objdump tests on archive.
2017-05-24Refactor disassembler selectionYao Qi2-1/+7
Nowadays, opcodes/disassemble.c:disassembler selects the proper disassembler according to ABFD only. However, it actually selects disassemblers according to arch, mach, endianess, and abfd. This patch adds them to the parameters of disassembler, so that its caller can still select disassemblers in case that abfd is NULL (a typical case in GDB). There isn't any functionality change. binutils: 2017-05-24 Yao Qi <yao.qi@linaro.org> * objdump.c (disassemble_data): Caller update. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h (disassembler): Update declaration. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * disassemble.c (disassembler): Add arguments a, big and mach. Use them. sim/common: 2017-05-24 Yao Qi <yao.qi@linaro.org> * sim-trace.c (trace_disasm): Caller update.
2017-05-19binutils: remove sparc64/mips64 workaround in objcopy build notes merge codeJose E. Marchesi2-7/+6
This patch removes a workaround recently installed in objcopy that avoided removing duplicated notes in targets for which the number of internal relocations may be bigger than the number of external relocations. With the recent fixes in sparc64 and mips64, this workaround is no longer necessary. 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * objcopy.c (merge_gnu_build_notes): Remove workaround that prevented deleting relocations in duplicated notes in mips64 and sparc.
2017-05-20MIPS/BFD: For n64 hold the number of internal relocs in `->reloc_count'Maciej W. Rozycki8-0/+84
Revert parts of commit fee24f1c5bfe ("objdump improvements for mips elf64"), <https://sourceware.org/ml/binutils/2003-03/msg00108.html>, and make the `->reloc_count' member of `struct bfd_section' hold the actual number of internal relocations stored in its `->relocation' vector. To do so adjust `mips_elf64_slurp_one_reloc_table' to set `->reloc_count' to the actual number of internal relocations retrieved and discard `mips_elf64_canonicalize_reloc', `mips_elf64_canonicalize_dynamic_reloc' and their corresponding target macros. Contrary to the description of `mips_elf64_slurp_one_reloc_table', adjusted appropriately, this makes generic relocation processing code happy and satisfies the "merge notes section" binutils test case. Add extra binutils test cases to expand the coverage of the generic "merge notes section" test case, now passing with the n64 ABI, across the MIPS o32, n32 and n64 ABIs regardless of the default ABI selected in target configuration, and also to verify correctness of the relocations produced. Conversely, do not provide any additional test cases for the original issue addressed with the commit referred: - objdump would display only 1/3 of the total number of relocations, because it used the external relocation count, but each external relocation is brought in as 3 internal relocations. as n64 ABI relocation processing with `objdump -r' and `objdump -R' is already widely covered across the GAS and LD test suites. bfd/ * elf64-mips.c (mips_elf64_canonicalize_reloc): Remove prototype and function. (mips_elf64_canonicalize_dynamic_reloc): Likewise. (mips_elf64_slurp_one_reloc_table): Set `reloc_count' to the actual number of internal relocations retrieved. Adjust function description. (bfd_elf64_canonicalize_reloc): Remove macro. (bfd_elf64_canonicalize_dynamic_reloc): Likewise. binutils/ * testsuite/binutils-all/mips/mips-note-2.d: New test. * testsuite/binutils-all/mips/mips-note-2r.d: New test. * testsuite/binutils-all/mips/mips-note-2-n32.d: New test. * testsuite/binutils-all/mips/mips-note-2-n64.d: New test. * testsuite/binutils-all/mips/mips-note-2r-n32.d: New test. * testsuite/binutils-all/mips/mips-note-2r-n64.d: New test. * testsuite/binutils-all/mips/mips.exp: Define `has_newabi'. Run the new tests.
2017-05-20binutils/testsuite: Permit the reuse of dump patternsMaciej W. Rozycki2-1/+18
Complement commit 89210bdc8fd2 ("GAS: Permit the reuse of dump patterns"), <https://sourceware.org/ml/binutils/2010-07/msg00269.html>, and commit ef2b5578f693 ("MIPS: Enable NewABI tests for SDE targets"), <https://sourceware.org/ml/binutils/2012-08/msg00017.html>, and like the GAS and LD versions make the binutils version of `run_dump_test' also support the `dump' keyword, for reusing dump patterns between tests. binutils/ * testsuite/lib/utils-lib.exp (run_dump_test): Handle the `dump' option.
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi2-0/+7
This patch adds support for the new SPARC M8 processor (implementing OSA 2017) to binutils. New instructions: - Dictionary Unpack + dictunpack - Partitioned Compare with shifted result + Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl - Partitioned Dual-Equal compared, with shifted result + fpcmpde{8,16,32}shl - Partitioned Unsigned Range Compare, with shifted result + fpcmpur{8,16,32}shl - 64-bit shifts on Floating-Point registers + fps{ll,ra,rl}64x - Misaligned loads and stores + ldm{sh,uh,sw,uw,x,ux} + ldm{sh,uh,sw,uw,x,ux}a + ldmf{s,d} + ldmf{s,d}a + stm{h,w,x} + stm{h,w,x}a + stmf{s,d} + stmf{s,d}a - Oracle Numbers + on{add,sub,mul,div} - Reverse Bytes/Bits + revbitsb + revbytes{h,w,x} - Run-Length instructions + rle_burst + rle_length - New crypto instructions + sha3 - Instruction to read the new register %entropy + rd %entropy New Alternate Address Identifiers: - 0x24, #ASI_CORE_COMMIT_COUNT - 0x24, #ASI_CORE_SELECT_COUNT - 0x48, #ASI_ARF_ECC_REG - 0x53, #ASI_ITLB_PROBE - 0x58, #ASI_DSFAR - 0x5a, #ASI_DTLB_PROBE_PRIMARY - 0x5b, #ASI_DTLB_PROBE_REAL - 0x64, #ASI_CORE_SELECT_COMMIT_NHT The new assembler command-line options for selecting the M8 architecture are: -Av9m8 or -Asparc6 for 64-bit binaries. -Av8plusm8 for 32-bit (v8+) binaries. The corresponding disassembler command-line options are: -msparc:v9m8 for 64-bit binaries. -msparc:v8plusm8 for 32-bit (v8+) binaries. Tested for regressions in the following targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux bfd/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v9m8): Define. (bfd_mach_sparc_v8plusm8): Likewise. (bfd_mach_sparc_v9_p): Adjust to M8. (bfd_mach_sparc_64bit_p): Likewise. * aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and bfd_mach_sparc_v8plusm8. * bfd-in2.h: Regenerated. * cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and sparc:v8plusm8. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and SHA3. * elf32-sparc.c (elf32_sparc_final_write_processing): Handle bfd_mach_sparc_v8plusm8. binutils/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Mention the SPARC M8 support. gas/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6', `v9m8' and `v8plusm8'. (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8. (get_hwcap_name): Support the M8 hardware capabilities. (sparc_ip): Handle new operand types. * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and -Asparc6, and the corresponding -xarch aliases. * testsuite/gas/sparc/sparc6.s: New file. * testsuite/gas/sparc/sparc6.d: Likewise. * testsuite/gas/sparc/sparc6-diag.s: Likewise. * testsuite/gas/sparc/sparc6-diag.l: Likewise. * testsuite/gas/sparc/fpcmpshl.s: Likewise. * testsuite/gas/sparc/fpcmpshl.d: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise. * testsuite/gas/sparc/ldm-stm.s: Likewise. * testsuite/gas/sparc/ldm-stm.d: Likewise. * testsuite/gas/sparc/ldm-stm-diag.s: Likewise. * testsuite/gas/sparc/ldm-stm-diag.l: Likewise. * testsuite/gas/sparc/ldmf-stmf.s: Likewise. * testsuite/gas/sparc/ldmf-stmf.d: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise. * testsuite/gas/sparc/on.s: Likewise. * testsuite/gas/sparc/on.d: Likewise. * testsuite/gas/sparc/on-diag.s: Likewise. * testsuite/gas/sparc/on-diag.l: Likewise. * testsuite/gas/sparc/rle.s: Likewise. * testsuite/gas/sparc/rle.d: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests. * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY. * testsuite/gas/sparc/rdasr.d: Likewise. include/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define. (ELF_SPARC_HWCAP2_ONADDSUB): Likewise. (ELF_SPARC_HWCAP2_ONMUL): Likewise. (ELF_SPARC_HWCAP2_ONDIV): Likewise. (ELF_SPARC_HWCAP2_DICTUNP): Likewise. (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise. (ELF_SPARC_HWCAP2_RLE): Likewise. (ELF_SPARC_HWCAP2_SHA3): Likewise. * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8 and adjust SPARC_OPCODE_ARCH_MAX. (HWCAP2_SPARC6): Define. (HWCAP2_ONADDSUB): Likewise. (HWCAP2_ONMUL): Likewise. (HWCAP2_ONDIV): Likewise. (HWCAP2_DICTUNP): Likewise. (HWCAP2_FPCMPSHL): Likewise. (HWCAP2_RLE): Likewise. (HWCAP2_SHA3): Likewise. (OPM): Likewise. (OPMI): Likewise. (ONFCN): Likewise. (REVFCN): Likewise. (SIMM10): Likewise. opcodes/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. (X_IMM2): Define. (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8. (print_insn_sparc): Handle new operand types. * sparc-opc.c (MASK_M8): Define. (v6): Add MASK_M8. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Likewise. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (v9andleon): Likewise. (m8): Define. (HWS_VM8): Define. (HWS2_VM8): Likewise. (sparc_opcode_archs): Add entry for "m8". (sparc_opcodes): Add OSA2017 and M8 instructions dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, fpx{ll,ra,rl}64x, ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19MIPS/binutils/testsuite: Bail out right away if !ELFMaciej W. Rozycki2-17/+20
We have but ELF binutils tests in the MIPS subset, and non-ELF MIPS/GAS ports are gone, making a future addition of any non-ELF tests unlikely. Bail out right away then if non-ELF, consuming one level of indentation across the actual tests run. binutils/ * testsuite/binutils-all/mips/mips.exp: Bail out right away if non-ELF.
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra2-2/+6
bfd/ * arc-got.h: Don't compare boolean values against TRUE or FALSE. * elf-m10300.c: Likewise. * elf.c: Likewise. * elf32-arc.c: Likewise. * elf32-bfin.c: Likewise. * elf32-m68k.c: Likewise. * elf32-nds32.c: Likewise. * elf32-tilepro.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-tilegx.c: Likewise. * mach-o.c: Likewise. * peXXigen.c: Likewise. * vms-alpha.c: Likewise. * vms-lib.c: Likewise. opcodes/ * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. binutils/ * strings.c: Don't compare boolean values against TRUE or FALSE. gas/ * config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE. * config/tc-hppa.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-score7.c: Likewise. ld/ * emultempl/elf32.em: Don't compare boolean values against TRUE or FALSE. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise.
2017-05-152017-05-15 Jeff Law <law@redhat.com>Jeff Law2-3/+8
* readelf.c (display_arc_attribute): Avoid implicit fallthru.
2017-05-15MIPS16e2: Add new MIPS16e2 ASE binutils and GAS testsMaciej W. Rozycki6-2/+557
Verify MIPS16e2 ASE instruction assembly, disassembly and object file flags. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Add `-mips3' to `as' flags. * testsuite/binutils-all/mips/mips16e2-undecoded.d: New test. * testsuite/binutils-all/mips/mips16e2-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-undecoded.s: Remove `.module mips3'. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/mips16e2.d: New test. * testsuite/gas/mips/mips16e2-mt.d: New test. * testsuite/gas/mips/mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-hilo.d: New test. * testsuite/gas/mips/mips16e2-hilo-n32.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.d: New test. * testsuite/gas/mips/mips16e2-imm-error.d: New test. * testsuite/gas/mips/elf_ase_mips16e2.d: New test. * testsuite/gas/mips/elf_ase_mips16e2-2.d: New test. * testsuite/gas/mips/elf-rel9-mips16e2.d: New test. * testsuite/gas/mips/mips16e2-lui.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test. * testsuite/gas/mips/mips16e2@lui-2.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output. * testsuite/gas/mips/mips16e2-imm-error.l: New stderr output. * testsuite/gas/mips/mips16e2@lui-2.l: New stderr output. * testsuite/gas/mips/mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-mt.s: New test source. * testsuite/gas/mips/mips16e2-sub.s: New test source. * testsuite/gas/mips/mips16e2-mt-sub.s: New test source. * testsuite/gas/mips/mips16e2-hilo.s: New test source. * testsuite/gas/mips/mips16e2-reloc-error.s: New test source. * testsuite/gas/mips/mips16e2-imm-error.s: New test source. * testsuite/gas/mips/elf-rel9-mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-lui.s: New test source. * testsuite/gas/mips/mips.exp: Expand `mips32r2-sync', `mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2 architectures. Run the new tests.
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki3-0/+9
Add MIPS16e2 ASE support as per the architecture specification[1], including in particular: 1. A new ELF ASE flag to mark MIPS16e2 binaries. 2. MIPS16e2 instruction assembly support, including a relaxation update to use LUI rather than an LI/SLL instruction pair for loading the high part of 32-bit addresses. 3. MIPS16e2 instruction disassembly support, including updated rules for extended forms of instructions that are now subdecoded and therefore do not alias to the original MIPS16 ISA revision instructions even for encodings that are not valid in the MIPS16e2 instruction set. Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and `.module' pseudo-ops. Control the availability of the MT ASE subset of the MIPS16e2 instruction set with a combination of these controls and the preexisting MT ASE controls. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific Extension Technical Reference Manual", Imagination Technologies Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016 include/ * elf/mips.h (AFL_ASE_MIPS16E2): New macro. (AFL_ASE_MASK): Adjust accordingly. * opcode/mips.h: Document new operand codes defined. (mips_operand_type): Add OP_REG28 enum value. (INSN2_SHORT_ONLY): Update description. (ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros. bfd/ * elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. (print_insn_arg) <OP_REG28>: Add handler. (validate_insn_args) <OP_REG28>: Handle. (print_mips16_insn_arg): Handle MIPS16 instructions that require 32-bit encoding and 9-bit immediates. (print_insn_mips16): Handle MIPS16 instructions that require 32-bit encoding and MFC0/MTC0 operand decoding. * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. (RD_C0, WR_C0, E2, E2MT): New macros. (mips16_opcodes): Add entries for MIPS16e2 instructions: GP-relative "addiu" and its "addu" spelling, "andi", "cache", "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" instructions, "swl", "swr", "sync" and its "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, "xori", "dmt", "dvpe", "emt" and "evpe". Add split regular/extended entries for original MIPS16 ISA revision instructions whose extended forms are subdecoded in the MIPS16e2 ISA revision: "li", "sll" and "srl". binutils/ * readelf.c (print_mips_ases): Handle MIPS16e2 ASE. * NEWS: Mention MIPS16e2 ASE support. gas/ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag. (RELAX_MIPS16_E2): New macro. (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO) (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT) (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT) (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED) (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED) (RELAX_MIPS16_MARK_ALWAYS_EXTENDED) (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO) (RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits. (mips16_immed_extend): New prototype. (options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum values. (md_longopts): Add "mmips16e2" and "mno-mips16e2" options. (mips_ases): Add "mips16e2" entry. (mips_set_ase): Handle MIPS16e2 ASE. (insn_insert_operand): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (is_opcode_valid_16): Pass enabled ASE bitmask on to `opcode_is_member'. (validate_mips_insn): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (operand_reg_mask) <OP_REG28>: Add handler. (match_reg28_operand): New function. (match_operand) <OP_REG28>: Add handler. (append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE. (match_mips16_insn): Handle MIPS16 instructions that require 32-bit encoding and `V' and `u' operand codes. (mips16_ip): Allow any characters except from `.' in opcodes. (mips16_immed_extend): Handle 9-bit immediates. Do not shuffle immediates whose width is not one of these listed. (md_estimate_size_before_relax): Handle MIPS16e2 relaxation. (mips_relax_frag): Likewise. (md_convert_frag): Likewise. (mips_convert_ase_flags): Handle MIPS16e2 ASE. * doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and `-mno-mips16e2' options. (-mmips16e2, -mno-mips16e2): New options. * doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and `-mno-mips16e2' options. (MIPS ASE Instruction Generation Overrides): Add `.set mips16e2' and `.set nomips16e2'.
2017-05-12MIPS16/opcodes: Make the handling of BREAK and SDBBP consistentMaciej W. Rozycki2-2/+7
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand in the hexadecimal rather than decimal numeral system and add respective operandless variants with an implicit 0 operand, making our handling of these instructions consistent with how we have processed their regular MIPS and microMIPS counterparts since forever. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand type to hexadecimal. (mips16_opcodes): Add operandless "break" and "sdbbp" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK and SDBBP disassembly. gas/ * testsuite/gas/mips/mips16.d: Adjust BREAK disassembly. * testsuite/gas/mips/mips16-64@mips16.d: Likewise. * testsuite/gas/mips/mips16-64.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-64.d: Likewise. * testsuite/gas/mips/mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-sub.d: Likewise. * testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
2017-05-10MIPS/binutils/testsuite: Define names of temporary filesMaciej W. Rozycki2-0/+13
Define `tempfile' and `copyfile' in `mips.exp' so that standalone script execution via `RUNTESTFLAGS=mips.exp' works rather than producing: Running .../binutils/testsuite/binutils-all/mips/mips.exp ... ERROR: tcl error sourcing .../binutils/testsuite/binutils-all/mips/mips.exp. ERROR: can't read "tempfile": no such variable while executing "binutils_assemble_flags ${srcfile} $tempfile $opts(as)" (procedure "run_dump_test" line 207) invoked from within "run_dump_test "mips-ase-1"" invoked from within "if [is_elf_format] { run_dump_test "mips-ase-1" run_dump_test "mips-ase-2" run_dump_test "mips-ase-3" run_dump_test "mixed-mips16" ..." (file ".../binutils/testsuite/binutils-all/mips/mips.exp" line 22) invoked from within "source .../binutils/testsuite/binutils-all/mips/mips.exp" ("uplevel" body line 1) invoked from within "uplevel #0 source .../binutils/testsuite/binutils-all/mips/mips.exp" invoked from within "catch "uplevel #0 source $test_file_name"" testcase .../binutils/testsuite/binutils-all/mips/mips.exp completed in 0 seconds binutils/ * testsuite/binutils-all/mips/mips.exp: Define `tempfile' and `copyfile' variables.
2017-05-10[ARC] Object attributes.Claudiu Zissulescu3-1/+210
gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10Remove Kaz Kojima as SH maintainer.Kaz Kojima2-1/+4
2017-05-02Cast relcount to unsigned long when comparing with sec->reloc_countH.J. Lu2-1/+6
The type of relcount is long and the type of sec->reloc_count is unsigned int. On 32-bit hosts, GCC issues an error: objcopy.c:2144:20: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare] if (relcount > sec->reloc_count) Cast relcount to unsigned long to silence GCC. * objcopy.c (merge_gnu_build_notes): Cast relcount to unsigned long when comparing with sec->reloc_count.
2017-05-02Don't merge notes when the relocs associated with them cannot be reliably ↵Nick Clifton2-0/+12
deleted. * objcopy.c (merge_gnu_build_notes): Disable merge if there are more internal relocs than external relocs.
2017-05-02MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki2-10/+15
Correct the disassembly of the PC-relative immediate argument of the MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the LSB, which in this case is a part of the data address rather than the ISA bit and has to be fully presented. opcodes/ * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps and branches and not synthetic data instructions. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the disassembly of PC-relative LA and LW synthetic instructions.
2017-05-02Prevent memory exhaustion from a corrupt PE binary with an overlarge number ↵Nick Clifton2-0/+14
of relocs. PR 21440 * objdump.c (dump_relocs_in_section): Check for an excessive number of relocs before attempting to dump them.
2017-05-01merge_gnu_build_notes reloc deletionAlan Modra2-5/+13
If moving relocs, the next reloc to look at is at the same location. * objcopy.c (merge_gnu_build_notes): Correct code deleting relocs.
2017-04-28Fix off by one error when checking for empty note names.Nick Clifton2-5/+16
PR binutils/21439 * readelf.c (print_gnu_build_attribute_name): Allow for an empty name field.
2017-04-28Fix heap-buffer address violation when reading version data from a corrupt ↵Nick Clifton2-2/+9
binary. PR binutils/21437 * readelf.c (process_version_sections): Check for underflow when computing the start address of the auxillary version data.
2017-04-28Fix heap-buffer overflow bugs caused when dumping debug information from a ↵Nick Clifton2-16/+60
corrupt binary. PR binutils/21438 * dwarf.c (process_extended_line_op): Do not assume that the string extracted from the section is NUL terminated. (fetch_indirect_string): If the string retrieved from the section is not NUL terminated, return an error message. (fetch_indirect_line_string): Likewise. (fetch_indexed_string): Likewise.
2017-04-26Fix PR number in ChangeLog comment.Nick Clifton1-1/+1
2017-04-26Fix invocation of stat() on a NULL pointer.Nick Clifton3-0/+13
PR binutils/21407 * bucomm.c (get_file_size): Return -1 if file_name is NULL. * ar.c (main): Fail with usage() invocation if no file names are provided.
generated by cgit v1.1 at 2025-01-31 05:19:05 +0000