aboutsummaryrefslogtreecommitdiff
path: root/binutils/ChangeLog
AgeCommit message (Collapse)AuthorFilesLines
2017-01-27Update description of the -plugin option used by the linker, ar and nm.Dilyan Palauzov1-0/+9
PR 20343 ld * ld.texinfo (Options): Extend documentation of the --plugin option. Include a description of where the plugins should be located. binutils* doc/binutils.texi (ar): Extend documentation of the --plugin option. Include a description of where the plugins should be located. (nm): Likewise.
2017-01-23Fix typo in MAINTAINERS fileNick Clifton1-1/+1
2017-01-23Remove Mei Ligang as SCORE maintainerNick Clifton1-0/+2
2017-01-23Add Bernd Schmidt to Past Maintainers listNick Clifton1-0/+4
2017-01-23 * MAINTAINERS (BFIN): Remove myself as Blackfin maintainer.Bernd Schmidt1-0/+4
2017-01-20objdump: Better objdump section headers in wide modeAndrew Burgess1-0/+8
When displaying the section headers table using objdump (-h), the column containing the section header name is currently fixed at 13 characters. A section name that is longer than 13 characters will overflow the column causing the table to become miss-aligned. In this commit I change the behaviour so that _in wide mode_ (-w -h) the section name column is dynamically resized to fit the longest section name we plan to display. In wide mode the column still retains a minimum width of 13 characters. In non-wide more the behaviour is completely unchanged. While I was changing the dump_headers function I have unified the two printf lines that handled the different address widths into a single printf, the address width is now passed into printf using the '*' field width format character. binutils/ChangeLog: * objdump.c (dump_section_header): Extract max section name length from data parameter, use this when formatting output. (find_longest_section_name): New function. (dump_headers): Calculate longest section name when in wide mode, reformat to unify printing of header line. ld/ChangeLog: * testsuite/ld-elf/eh-frame-hdr.d: Update expected results.
2017-01-18Add support for processing lex source files with flex v 2.6.3Bernhard Rosenkranzer1-0/+6
PR 21059 binutils* arlex.l: Support processing with flex 2.6.3. * deflex.l: Likewise. gas * config/bfin-lex.l: Support processing with flex 2.6.3. * itbl-lex.l: Likewise.
2017-01-18Stop the (optional) dialong control data from being aligned when ↵Dmitry Timoshkov1-0/+8
parsing/writing windows resource files. binutils* resbin.c: Optional dialog control data immediately follow the control description without alignment. * testsuite/binutils-all/windres/controldata.rc: New test. source. * testsuite/binutils-all/windres/controldata.rsd: New test.
2017-01-12Add support for locating separate debug info files via the build-id method.Nick Clifton1-0/+8
PR binutils/20876 bfd * opncls.c (find_separate_debug_file): Add include_dirs parameter. Only include the directory part of the bfd's filename in search paths if include_dirs is true. Add a couple of extra locations for looking for debug files. ( bfd_follow_gnu_debuglink): Update invocation of find_separate_debug_file. (bfd_follow_gnu_debugaltlink): Likewise. (get_build_id): New function: Finds the build-id of the given bfd. (get_build_id_name): New function: Computes the name of the separate debug info file for a bfd, based upon its build-id. (check_build_id_file): New function: Checks to see if a separate debug info file exists at the given location, and that its build-id matches that of the original bfd. (bfd_follow_build_id_debuglink): New function: Finds a separate debug info file for a given bfd by using the build-id method. * dwarf2.c (_bfd_dwarf2_slurp_debug_info): Try using the build-id method of locating a separate debug info file before using the debuglink method. * bfd-in2.h: Regenerate. binutils * NEWS: Mention the new feature. * testsuite/binutils-all/objdump.exp (test_build_id_debuglink): New proc to test the location of separate debug info files using the build-id method.
2017-01-10Fix compile time warning about pointer comparison.Nick Clifton1-0/+6
PR 21034 * stabs.c (parse_stab_members): Fix thinko checking for g++ version 1 stabs information.
2017-01-09Speed up objdump when displaying disassembly mixed with line number and ↵Nick Clifton1-0/+8
source code information. bfd * dwarf2.c (lookup_address_in_function_table): Return early if there are no functions in the given comp unit, or if the high address of the last function in the comp unit is less than the desired address. binutils * objdump.c (display_file): Add new parameter 'last_file'. If last_file is true, do not call bfd_close at the end of the function. (main): Set the value of the last_file parameter when calling display_file.
2017-01-09.rela.dyn comment fix and add missing ChangeLog entryAlan Modra1-0/+5
ChangeLog entry missed from commit dd90581873. * readelf.c (process_section_headers): Correct .rel.dyn/.rela.dyn comment.
2017-01-06Retire Paul Brook as an ARM maintainer.Nick Clifton1-0/+4
* MAINTAINERS: Move Paul Brook to the Past Maintainers section.
2017-01-04Use noyywrap option in lex files.Dilan Palauzov1-0/+6
ld PR 20958 * ldlex.l (option): Add noyywrap (yywrap): Delete. * ldlex.h (yywrap): Delete prototype. binutils PR 20958 * syslex.l (option): Add noyywrap (yywrap): Delete.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-973/+2
2016-12-31PRU Binutils portDimitar Dimitrov1-0/+9
* readelf.c (guess_is_rela): Add EM_TI_PRU. (dump_relocations): Invoke elf_pru_reloc_type. (get_machine_name): Handle EM_TI_PRU. (is_32bit_abs_reloc): Handle R_PRU_BFD_RELOC_32. (is_16bit_abs_reloc): Handle R_PRU_BFD_RELOC_16. (is_none_reloc): Handle PRU_NONE and PRU_DIFF variants. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-0/+5
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+7
Identify non-extensible instructions in the MIPS16 opcode table and disallow their use with the `.e' instruction size suffix in assembly and do not interpret any EXTEND prefix present as a part of the instruction in disassembly. According to all versions of the MIPS16 ASE specifications the following instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R, I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [3][5]. Therefore in the presence of an EXTEND prefix none of these instructions are supposed to be handled as extended instructions and supporting these forms in disassembly causes confusion, and in the case of the RRR major opcode it also clashes with the ASMACRO encoding. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39 [4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49 [5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41 [6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51 include/ * opcode/mips.h (INSN2_SHORT_ONLY): New macro. gas/ * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix instruction size override for INSN2_SHORT_ONLY opcode table entries. * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-insn-e.s: New test source. * testsuite/gas/mips/mips16-insn-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix matching for INSN2_SHORT_ONLY opcode table entries. * mips16-opc.c (SH): New macro. (mips16_opcodes): Set SH in `pinfo2' for non-extensible instruction entries: "nop", "addu", "and", "break", "cmp", "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", "seh", "sew", "zeb", "zeh", "zew" and "extend". binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-extend-insn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-23Bump version to 2.28.51Tristan Gingold1-0/+4
bfd/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.28.51 * configure: Regenerate. binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2016-12-23Add marker in NEWS filesTristan Gingold1-0/+4
binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.28.
2016-12-23Regenerate pot files.Tristan Gingold1-0/+4
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki1-0/+5
Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+5
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-0/+6
We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki1-0/+9
Respect any ASE flags recorded in ELF file structures for the purpose of selecting instructions to be disassembled, preventing code from being hex-dumped even though having been clearly indicated as valid at the assembly time. Use date from the MIPS ABI flags structure if present, and otherwise there may be an MDMX ASE flag set in the ELF file header. For backwards compatibility only set extra flags and do not clear any, preserving all previously set by the architecture selected to be disassembled for. include/ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct typedef as `elf_internal_abiflags_v0'. bfd/ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration. (bfd_mips_elf_get_abiflags): New prototype. * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (mips_convert_abiflags_ases): New function. (set_default_mips_dis_options): Also infer ASE flags from ELF file structures. binutils/ * testsuite/binutils-all/mips/mips-ase-1.d: New test. * testsuite/binutils-all/mips/mips-ase-2.d: New test. * testsuite/binutils-all/mips/mips-ase-3.d: New test. * testsuite/binutils-all/mips/mips-ase-1.s: New test source. * testsuite/binutils-all/mips/mips-ase-2.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-13[AArch64] Recognize R_AARCH64_P32_ABS32 as 32-bit relocation in readelfJiong Wang1-0/+4
binutils/ * readelf.c (is_32bit_abs_reloc): Recognize R_AARCH64_P32_ABS32.
2016-12-13Add a 'Past Maintainers' section to the MAINTAINERS file. Retire Mark ↵Nick Clifton1-0/+5
Mitchell's name to this section. * MAINTAINERS (Past Maintainers): New section. Move Mark Mitchell's name here.
2016-12-09MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki1-0/+7
Use a tab rather than a space to separate `extend' and its uninterpreted argument output, like with regular instructions. Separate hexadecimal halves of undecoded extended instructions output with a space instead of presenting them concatenated. opcodes/ * mips-dis.c (print_insn_mips16): Use a tab rather than a space to separate `extend' and its uninterpreted argument output. Separate hexadecimal halves of undecoded extended instructions output. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: New test. * testsuite/binutils-all/mips/mips16-extend-noinsn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.
2016-12-08MIPS16/opcodes: Fix PC-relative operation delay-slot adjustmentMaciej W. Rozycki1-0/+6
Complement commit dd8b7c222e0e ("MIPS: mips16e jalrc/jrc opcodes"), <https://sourceware.org/ml/binutils/2005-07/msg00349.html>, and stop the disassembler making a delay-slot adjustment for PC-relative operations following either MIPS16e compact jumps, or undefined RR/J(AL)R(C) encodings that have the `l' (link) and `ra' (source register is `ra') bits set both at a time. Adjust code description for accuracy. Add a suitable test case. opcodes/ * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot adjustment for PC-relative operations following MIPS16e compact jumps or undefined RR/J(AL)R(C) encodings. binutils/ * testsuite/binutils-all/mips/mips16-pcrel.d: New test. * testsuite/binutils-all/mips/mips16-pcrel.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.
2016-12-08Always use a hex prefix when displaying the alignment of program headers.Etienne Buira1-0/+5
* readelf.c (process_program_headers): Always use hex prefix when displaying the segment alignment.
2016-12-06Fix seg-fault running strip on a corrupt binary.Nick Clifton1-0/+7
PR binutils/20930 * objcopy.c (mark_symbols_used_in_relocations): Check for a null symbol pointer pointer before attempting to mark the symbol as kept.
2016-12-05binutils: add myself to MAINTAINERSJose E. Marchesi1-0/+4
2016-12-05 Jose E. Marchesi <jose.marchesi@oracle.com> * MAINTAINERS: Add myself as maintainer for the SPARC targets.
2016-12-05Fix seg-fault running strip on a corrupt binary.Nick Clifton1-0/+6
PR ld/20923 * objcopy.c (mark_symbols_used_in_relocations): Check for a null symbol pointer before attempting to mark the symbol as kept.
2016-12-01Fix calculation of synthetic symbol sizes (ppc64)Luis Machado1-0/+5
The attached patch fixes a problem where nm displays bogus information for synthetic symbol sizes when --size-sort is used. This happens because the synthetic symbols (dot symbols for ppc64) are generated based on their non-dot symbols. The generation process doesn't copy over the ELF-specific bits of the regular non-dot symbols. When --size-sort is used, the code attempts to access the symbol size from the ELF-specific bits and ends up reading gargabe, causing the size to be displayed incorrectly. With the patch, i can see dot and non-dot symbols having the same size with --size-sort. This doesn't fix the fact that we don't display size information for synthetic symbols without --size-sort, which i may address in the future. binutils/ChangeLog: 2016-12-01 Luis Machado <lgustavo@codesourcery.com> * nm.c (sort_symbols_by_size): Don't read symbol size if symbol is synthetic.
2016-11-30Stop readelf from complaining about out of order PT_LOAD segments.Nick Clifton1-0/+6
PR ld/20815 * readelf.c (process_program_headers): Do not warn about out of order PT_LOAD segments.
2016-11-29[ARC] Fix disassembler option.Claudiu Zissulescu1-0/+5
This patch fixes: - fpus and fpud are swaped. - quarkse_em doesn't include FPX extensions. - auto guessed opcode mechanism may ignore the option passed via -M<feature> option. opcodes/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (is_compatible_p): Remove function. (skip_this_opcode): Don't add any decoding class to decode list. Remove warning. (find_format_from_table): Go through all opcodes, and warn if we use a guessed mnemonic. binutils/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/binutils-all/arc/objdump.exp (Warning test): Update test.
2016-11-27Fix spelling in comments in C source files (binutils)Ambrogino Modigliani1-0/+10
* dwarf.c: Fix spelling in comments. * dwarf.h: Fix spelling in comments. * objcopy.c: Fix spelling in comments. * od-macho.c: Fix spelling in comments. * rclex.c: Fix spelling in comments. * readelf.c: Fix spelling in comments. * stabs.c: Fix spelling in comments.
2016-11-23Fix the linker so that it will not silently generate ELF binaries with ↵Nick Clifton1-0/+6
invalid program headers. Fix readelf to report such invalid binaries. PR ld/20815 bfd * elf.c (elf_modify_segment_map): Allow empty LOAD segments if they contain the program headers. (_bfd_elf_map_sections_to_segments): If the linker created the PHDR segment then always attempt to include it in a LOAD segment. (assign_file_positions_for_non_load_sections): Allow LOAD segments to overlap PHDR segments. (phdr_sorter): New function. Sorts program headers. (assign_file_positions_except_relocs): Sort the program headers before writing them out. Issue an error if the PHDR segment is not covered by a LOAD segment, unless the backend allows it. * elf-bfd.h (struct elf_backend_data): Add elf_backend_allow_non_load_phdr. * elfxx-target.h (elf_backend_allow_non_load_phdr): Provide default definition that returns FALSE. (elfNN_bed): Initialise the elf_backend_allow_non_load_phdr field. * elf64-hppa.c (elf64_hppa_allow_non_load_phdr): New function. Returns TRUE. (elf_backend_allow_non_load_phdr): Define. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Do not place the interpreter string into the .interp section if the nointerp flag is set in the link info structure. * elf32-arc.c (elf_arc_size_dynamic_sections): Likewise. * elf32-score7.c (score_elf_final_link_relocate): Allow for the _gp symbol not being part of the output. binutils* readelf.c (process_program_headers): Check PT_LOAD and PT_PHDR segments for validity. ld * ld.texinfo: Note that PT_TLS can be used as a segment type. * testsuite/ld-discard/discard.ld: Add space for program headers. * testsuite/ld-elf/flags1.ld: Likewise. * testsuite/ld-elf/maxpage3.t: Likewise. * testsuite/ld-elf/noload-1.t: Likewise. * testsuite/ld-elf/orphan.ld: Likewise. * testsuite/ld-elf/overlay.t: Likewise. * testsuite/ld-elf/pr14052.t: Likewise. * testsuite/ld-elf/pr19539.t: Likewise. * testsuite/ld-elf/provide-hidden-1.ld: Likewise. * testsuite/ld-elf/provide-hidden-s.ld: Likewise. * testsuite/ld-elf/weak-dyn-1.ld: Likewise. * testsuite/ld-i386/pr19539.t: Likewise. * testsuite/ld-scripts/defined.t: Likewise. * testsuite/ld-scripts/defined6.t: Likewise. * testsuite/ld-scripts/dynamic-sections.t: Likewise. * testsuite/ld-scripts/empty-aligned.t: Likewise. * testsuite/ld-scripts/provide-2.t: Likewise. * testsuite/ld-scripts/provide-4.t: Likewise. * testsuite/ld-vax-elf/plt-local.ld: Likewise. * testsuite/ld-x86-64/pr19539.t: Likewise. * testsuite/ld-elf/ehdr_start-missing.d: Do not initialise the dynamic linker. * testsuite/ld-elf/ehdr_start-weak.d: Likewise. * testsuite/ld-elf/elf.exp (pr14170, pr17068): Likewise. * testsuite/ld-elf/loadaddr1.d: Update expected readelf output. * testsuite/ld-elf/noload-2.d: Likewise. * testsuite/ld-powerpc/vxworks2.sd: Likewise. * testsuite/ld-scripts/phdrs3a.d: Likewise. * testsuite/ld-scripts/size-2.d: Likewise. * testsuite/ld-elf/group.ld: Add program headers. * testsuite/ld-elf/overlay.d: Skip for SPU. * testsuite/ld-elf/flags1.d: Skip for RX. * testsuite/ld-elf/pr19162.d: Skip for HPPA64. * testsuite/ld-elf/pr19539.d: Skip for ALPHA. * testsuite/ld-scripts/empty-orphan.t: Update program headers. * testsuite/ld-scripts/size-2.t: Likewise.
2016-11-22Fix spelling mistakes in comments in configure scriptsAmbrogino Modigliani1-0/+4
All changes are limited to comments, and no run-time behavior is affected. bfd/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * warning.m4: Fix spelling in comments. * configure.ac: Fix spelling in comments. * configure: Regenerate. binutils/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gdb/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure.ac: Fix spelling in comments. * configure: Regenerate. gas/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gold/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gprof/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. ld/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. opcodes/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate.
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-0/+5
VLE 16A and 16D relocs were functionally swapped. PR 20744 include/ * opcode/ppc.h: Define VLE insns using 16A and 16D relocs. bfd/ * elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field. * elf32-ppc.c: Include opcode/ppc.h. (ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A, R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A, R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D, R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D, R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs. (ppc_elf_link_hash_table_create): Update default_params init. (ppc_elf_vle_split16): Correct shift and mask. Add params. Report or fix insn/reloc mismatches. (ppc_elf_relocate_section): Pass input_section, offset and fixup to ppc_elf_vle_split16. binutils/ * NEWS: Mention PowerPC VLE relocation error. gas/ * config/tc-ppc.c: Delete VLE insn defines. (md_assemble): Swap use_a_reloc and use_d_reloc. * testsuite/gas/ppc/vle-reloc.d: Update. ld/ * emultempl/ppc32elf.em (params): Update initializer. Handle --vle-reloc-fixup command line arg.
2016-11-18cxxfilt: Recognize rust_demangling.Mark Wielaard1-0/+4
2016-11-14Generate correct hint value for IDATA6.Rudy1-0/+9
PR binutils/20814 * dlltool.c (struct export): Remove hint field. (make_one_lib_file): Store the ordinal value for IDATA6 not the hint. (gen_lib_file): Delete reference to hint field. (mangle_defs): Delete computation of hint field.
2016-11-11Add the ability for nm to display symbol version information.Nick Clifton1-0/+15
PR binutils/20751 * nm.c (with_symbol_versions): New local variable. (long_options): Add --with-symbol-versions. (usage): Mention --with-symbol-versions. (print_symbol): If with_symbol_versions is set then display the version information associated with the symbol. * NEWS: Mention the new feature. * doc/binutils.texi (nm): Document the new option. (objdump): Describe how symbol version information is displayed for dynamic symbol dumps. (readelf): Describe how symbol version information is displayed. * testsuite/binutils-all/nm.exp: Add a test of the new feature.
2016-11-08Fix heap-buffer-overflow error detected by address sanitization on a fuzzed ↵Nick Clifton1-0/+6
binary. PR binutils/20794 * readelf.c (process_section_headers): Fix off-by-one error when checking for invalid sh_link and sh_info fields.
2016-11-04objcopy: Close some memory leaks in error pathsAndrew Burgess1-0/+5
Closes some memory leaks within objcopy for error paths. binutils/ChangeLog: * objcopy.c (copy_section): Add extra calls to free for error paths.
2016-11-04set default-directory in dwarf-browseTom Tromey1-0/+5
I've been using dwarf-mode.el again recently and I found it mildly annoying that the mode doesn't set default-directory. Setting it means that operations in the dwarf-browsing buffer default to the directory holding the object file being investigated. This bumps the version number as well so that updating it via the package manager works properly. 2016-11-04 Tom Tromey <tom@tromey.com> * dwarf-mode.el (dwarf-browse): Set default-directory. Bump version number.
2016-11-04Add maintainers for RISC-V target.Palmer Dabbelt1-0/+5
* MAINTAINERS: Add myself and Andrew Waterman as maintainers for the RISC-V target.
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+14
bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-10-17Display unknown notes. Decode NT_GNU_HWCAP notes.Nick Clifton1-0/+16
* readelf.c (apply_relocations): Fail if the symbol table section linked to by the reloc section does not have either the SHT_SYMTAB or SHT_DYNSYM type. (print_gnu_note): Decode the contents of NT_GNU_HWCAP notes. Print the contents of unknown note types. (process_note): Add the file and section to the parameter list. Use print_symbol to display the note name. Display the contents of unknown note types. (process_corefile_note_segment): Rename to process_notes_at. Add section parameter. Apply relocations to the notes when loading from a section. Display section name when processing notes in a section. * testsuite/binutils-all/readelf.n: Update expected output.
generated by cgit v1.1 at 2024-11-22 05:41:23 +0000