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output unreproducible.
bfd
* peXXigen.c (_bfd_XXi_only_swap_filehdr_out): If inserting a timestamp, use the value held in the SOURCE_DATE_EPOCH environment variable, if it is defined.
binutils
* doc/binutils.texi (objcopy): Document change in behaviour of objcopy's --preserve-dates command line option.
ld
* pe-dll.c (fill_edata): If inserting a timestamp, use the value held in the SOURCE_DATE_EPOCH environment variable, if it is defined.
* ld.texi (--insert-timestamp): Document change in behaviour.
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In LoongArch, the R_LARCH_IRELATIVE relocations for local ifunc symbols are
in .rela.dyn. Before, this is done by loongarch_elf_finish_dynamic_sections.
But this function is called after elf_link_sort_relocs, it need to find a
null slot to insert IRELATIVE relocation.
Now, it is processed by elf_loongarch_output_arch_local_syms before
elf_link_sort_relocs, just need to call loongarch_elf_append_rela to
insert IRELATIVE relocation.
bfd/ChangeLog:
* elfnn-loongarch.c (elfNN_allocate_local_ifunc_dynrelocs): Return
type change to int.
(loongarch_elf_size_dynamic_sections): Delete (void *).
(loongarch_elf_finish_dynamic_symbol): Use loongarch_elf_append_rela
insert IRELATIVE relocation to .rela.dyn.
(elfNN_loongarch_finish_local_dynamic_symbol): Return type change to
int.
(loongarch_elf_finish_dynamic_sections): Delete process of local
ifunc symbols.
(elf_backend_output_arch_local_syms): New.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/local-ifunc-reloc.d: Regenerated.
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For B16/B21/B26/PCREL20_S2 relocations, if immediate overflow check after
rightshift, and the mask need to include sign bit.
Now, the immediate overflow check before rightshift for easier understand.
bfd/ChangeLog:
* elfxx-loongarch.c (reloc_bits_pcrel20_s2): Delete.
(reloc_bits_b16): Delete.
(reloc_bits_b21): Delete.
(reloc_bits_b26): Delete.
(reloc_sign_bits): New.
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For extreme code mode, the instruction sequences is
pcalau12i $t0, hi20
addi.d $t1, $zero, lo12
lu32i.d $t1, lo20
lu52i.d $t1, hi12
add.d $t1, $t0, $t1
If lo12 > 0x7ff, hi20 need to add 0x1, lo20 need to sub 0x1.
If hi20 > 0x7ffff, lo20 need to add 0x1.
bfd/ChangeLog:
* elfnn-loongarch.c (RELOCATE_CALC_PC32_HI20): Redefined.
(RELOCATE_CALC_PC64_HI32): Redefined.
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This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
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CGEN is cool, but the BPF architecture is simply too bizarre for it.
The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port. The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update. Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.
This is getting un-maintenable.
So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN. Overall, this involved:
* To remove the cpu/bpf.{cpu,opc} descriptions.
* To remove the CGEN generated files.
* To replace the CGEN generated opcodes table with a new hand-written
opcodes table for BPF.
* To replace the CGEN generated disassembler wih a new disassembler
that uses the new opcodes.
* To replace the CGEN generated assembler with a new assembler that uses the
new opcodes.
* To replace the CGEN generated simulator with a new simulator that uses the
new opcodes. [This is pushed in GDB in another patch.]
* To adapt the build systems to the new situation.
Additionally, this patch introduces some extensions and improvements:
* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These
relocations are used for section-relative 16-bit offsets used in
load/store instructions.
* The disassembler now has support for the "pseudo-c" assembly syntax of
BPF. What dialect to use when disassembling is controlled by a command
line option.
* The disassembler now has support for dumping instruction immediates in
either octal, hexadecimal or decimal. The used output base is controlled
by a new command-line option.
* The GAS BPF test suite has been re-structured and expanded in order to
test the disassembler pseudoc syntax support. Minor bugs have been also
fixed there. The assembler generic tests that were disabled for bpf-*-*
targets due to the previous implementation of pseudoc syntax are now
re-enabled. Additional tests have been added to test the new features of
the assembler. .dump files are no longer used.
* The linker BPF test suite has been adapted to the command line options
used by the new disassembler.
The result is very satisfactory. This patchs adds 3448 lines of code
and removes 10542 lines of code.
Tested in:
* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
little-endian host.
* Target x86-64-linux-gnu with --enable-targets=all
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port. I beg the indulgence of the global maintainers.
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* elfxx-mips.c (_bfd_mips_elf_symbol_processing): Don't treat
__gnu_lto_slim as SHN_MIPS_SCOMMON.
(_bfd_mips_elf_add_symbol_hook): Likewise.
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This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'. Zcb also imply Zca extension to enable the compressing
features.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcb.d: New test.
* testsuite/gas/riscv/zcb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
(MASK_C_LBU): New mask.
(MATCH_C_LHU): New opcode.
(MASK_C_LHU): New mask.
(MATCH_C_LH): New opcode.
(MASK_C_LH): New mask.
(MATCH_C_SB): New opcode.
(MASK_C_SB): New mask.
(MATCH_C_SH): New opcode.
(MASK_C_SH): New mask.
(MATCH_C_ZEXT_B): New opcode.
(MASK_C_ZEXT_B): New mask.
(MATCH_C_SEXT_B): New opcode.
(MASK_C_SEXT_B): New mask.
(MATCH_C_ZEXT_H): New opcode.
(MASK_C_ZEXT_H): New mask.
(MATCH_C_SEXT_H): New opcode.
(MASK_C_SEXT_H): New mask.
(MATCH_C_ZEXT_W): New opcode.
(MASK_C_ZEXT_W): New mask.
(MATCH_C_NOT): New opcode.
(MASK_C_NOT): New mask.
(MATCH_C_MUL): New opcode.
(MASK_C_MUL): New mask.
(DECLARE_INSN): New opcode.
* opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
(EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
(ENCODE_ZCB_BYTE_UIMM): Ditto.
(ENCODE_ZCB_HALFWORD_UIMM): Ditto.
(VALID_ZCB_BYTE_UIMM): Ditto.
(VALID_ZCB_HALFWORD_UIMM): Ditto.
(enum riscv_insn_class): New extension class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operators.
* riscv-opc.c: New instructions.
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This patch add Zca/f/d extensions support, since all ZC*
extensions will imply Zca extension, just enabled compress
feature when Zca extension is available.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (riscv_set_arch): Extend compress check.
* testsuite/gas/riscv/zca.d: New test.
* testsuite/gas/riscv/zca.s: New test.
* testsuite/gas/riscv/zcd.d: New test.
* testsuite/gas/riscv/zcd.s: New test.
* testsuite/gas/riscv/zcf.d: New test.
* testsuite/gas/riscv/zcf.s: New test.
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Many of the reloc error messages have already been converted from
using %C to using %H in ld.bfd, to print section+offset as well as
file/line/function. This catches a few remaining, and changes gold to
do the same.
PR 10957
bfd/
* elf32-sh.c (sh_elf_relocate_section): Use %H in error messages.
gold/
* object.cc (Relocate_info::location): Always report section+offset.
* testsuite/debug_msg.sh: Adjust to suit.
* testsuite/x32_overflow_pc32.sh: Likewise.
* testsuite/x86_64_overflow_pc32.sh: Likewise.
ld/
* emultempl/pe.em (read_addend): Use %H in error message.
* emultempl/pep.em (read_addend): Likewise.
* ldcref.c (check_reloc_refs): Likewise.
* ldmain.c (warning_find_reloc, undefined_symbol): Likewise.
* pe-dll.c (pe_create_import_fixup): Likewise.
* testsuite/ld-cris/undef2.d: Adjust expected output to suit.
* testsuite/ld-cris/undef3.d: Likewise.
* testsuite/ld-elf/shared.exp: Likewise.
* testsuite/ld-i386/compressed1.d: Likewise.
* testsuite/ld-ia64/line.exp: Likewise.
* testsuite/ld-plugin/lto.exp: Likewise.
* testsuite/ld-undefined/undefined.exp: Likewise.
* testsuite/ld-x86-64/compressed1.d: Likewise.
* testsuite/ld-x86-64/line.exp: Likewise.
* testsuite/ld-x86-64/pr27587.err: Likewise.
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Making target code depend on a host define like _AIX52 is never
correct, so out it goes. Also, sort some config.bfd entries a little
to make it more obvious there is a config difference between aix5.1
and aix5.2. These two changes should make no difference to anything
in binutils. The gas define of AIX_WEAK_SUPPORT on the other hand was
wrong, so fix that. Finally, fix some testsuite fails on aix < 5.2 by
simply not running the tests.
include/
* coff/internal.h (C_WEAKEXT): Don't depend on _AIX52.
bfd/
* coffcode.h (coff_slurp_symbol_table): Don't depend on _AIX52.
(coff_classify_symbol): Likewise.
* config.bfd: Sort some entries.
gas/
* configure.ac (AIX_WEAK_SUPPORT): Don't set for aix5.[01].
* configure: Regenerate.
* testsuite/gas/ppc/aix.exp (xcoff-visibility-1*) Don't run
for aix < 5.2.
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This fixes an uninitialised memory access on a fuzzed file:
0 0xf22e9b in offset_from_vma /src/binutils-gdb/bfd/elf.c:1899:2
1 0xf1e90f in _bfd_elf_get_dynamic_symbols /src/binutils-gdb/bfd/elf.c:2099:13
2 0x10e6a54 in bfd_elf32_object_p /src/binutils-gdb/bfd/elfcode.h:851:9
Hopefully it will also stop any attempt to load dynamic symbols from
eu-strip debug files.
* elfcode.h (elf_object_p): Do not attempt to load dynamic
symbols for a file with no section headers until all the
program headers are swapped in. Do not fail on eu-strip debug
files.
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bfd/
* coff-rs6000.c (add_range): Revise comment, noting possible fail.
(_bfd_xcoff_openr_next_archived_file): Start with clean ranges.
binutils/
* bfdtest1.c: Enhance to catch errors on second scan.
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For example, objcopy --set-section-flags .data=alloc,large will add
SHF_X86_64_LARGE to the .data section. Omitting "large" will drop the
SHF_X86_64_LARGE flag.
The bfd_section flag is named generically, SEC_ELF_LARGE, in case other
processors want to follow SHF_X86_64_LARGE. SEC_ELF_LARGE has the same
value as SEC_TIC54X_BLOCK used by coff.
bfd/
* section.c: Define SEC_ELF_LARGE.
* bfd-in2.h: Regenerate.
* elf64-x86-64.c (elf_x86_64_section_flags, elf_x86_64_fake_sections,
elf_x86_64_copy_private_section_data): New.
binutils/
* NEWS: Mention the new feature for objcopy.
* doc/binutils.texi: Mention "large".
* objcopy.c (parse_flags): Parse "large".
(check_new_section_flags): Error if "large" is used with a
non-x86-64 ELF target.
* testsuite/binutils-all/x86-64/large-sections.d: New.
* testsuite/binutils-all/x86-64/large-sections.s: New.
* testsuite/binutils-all/x86-64/large-sections-i386.d: New.
* testsuite/binutils-all/x86-64/large-sections-2.d: New.
* testsuite/binutils-all/x86-64/large-sections-2-x32.d: New.
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Currently we have three instruction classes defined for Zvkh[a,b]:
- INSN_CLASS_ZVKNHA
- INSN_CLASS_ZVKNHB
- INSN_CLASS_ZVKNHA_OR_ZVKNHB
The encodings of all instructions in Zvknh[a,b] are identical.
Therefore, we don't need the individual instruction classes
and can remove them.
This patch also adds the missing support of the combined instruction
class in riscv_multi_subset_supports_ext().
Fixes: 62edb233ef5 ("RISC-V: Add support for the Zvknh[a,b] ISA extensions")
Reported-By: Nelson Chu <nelson@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvksc is part of the vector crypto extensions.
Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksc.d: New test.
* testsuite/gas/riscv/zvksc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvknc is part of the vector crypto extensions.
Zvknc is shorthand for the following set of extensxions:
- Zvkn
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvknc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvknc.d: New test.
* testsuite/gas/riscv/zvknc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvksg is part of the vector crypto extensions.
Zvksg is shorthand for the following set of extensions:
- Zvks
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksg extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksg.d: New test.
* testsuite/gas/riscv/zvksg.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvks is part of the vector crypto extensions.
Zvks is shorthand for the following set of extensions:
- Zvksed
- Zvksh
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvks extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvks.d: New test.
* testsuite/gas/riscv/zvks.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvkng is part of the vector crypto extensions.
Zvkng is shorthand for the following set of extensions:
- Zvkn
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkng extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkng.d: New test.
* testsuite/gas/riscv/zvkng.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Certain extensions require two levels of implications. For example,
zvkng implies zvkn and zvkn implies zvkned. Enabling zvkng should also
enable zvkned.
This patch fixes this behavior.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_add_implicit_subsets): Allow nested
implications for extensions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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Zvkn is part of the vector crypto extensions.
Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkn extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkn.d: New test.
* testsuite/gas/riscv/zvkn.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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