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2024-01-01Automatic date update in version.inGDB Administrator1-1/+1
2023-12-31Automatic date update in version.inGDB Administrator1-1/+1
2023-12-30Regen bfd-in2.hAlan Modra1-1/+0
Please DON'T edit this file. READ THE COMMENT!
2023-12-30Automatic date update in version.inGDB Administrator1-1/+1
2023-12-29LoongArch: bfd: Add support for tls le relax.changjiachen6-5/+169
Add tls le relax support and related relocs in bfd. New relocation related explanation can refer to the following url: https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc This support does two main things: 1. Implement support for three new relocation items in bfd. The three new relocation items are shown below: R_LARCH_TLS_LE_ADD_R R_LARCH_TLS_LE_HI20_R R_LARCH_TLS_LE_LO12_R 2. ADD a new macro RELOCATE_TLS_TP32_HI20 Handle problems caused by symbol extensions in TLS LE, The processing is similar to the macro RELOCATE_CALC_PC32_HI20 method. 3. Implement the tls le relax function. bfd/ChangeLog: * bfd-in2.h: Add relocs related to tls le relax. * elfnn-loongarch.c: (loongarch_relax_tls_le): New function. (RELOCATE_TLS_TP32_HI20): New macro. (loongarch_elf_check_relocs): Add new reloc support. (perform_relocation): Likewise. (loongarch_elf_relocate_section): Handle new relocs related to relax. (loongarch_elf_relax_section): Likewise. * elfxx-loongarch.c: (LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise. * libbfd.h: Add relocs related to tls le relax. * reloc.c: Likewise.
2023-12-29Automatic date update in version.inGDB Administrator1-1/+1
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu4-3/+130
For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu4-18/+59
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objectsNelson Chu2-14/+32
* Problematic fix commit, 2029e13917d53d2289d3ebb390c4f40bd2112d21 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc *SUB* relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. ld/ * NEWS: Updated. * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with binutils 2.42 and up, to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
2023-12-28Automatic date update in version.inGDB Administrator1-1/+1
2023-12-27asan: buffer overflow in loongarch_elf_rtype_to_howtoAlan Modra1-21/+11
Seen when running ld-loongarch-elf/tlsdesc-dso test. elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for type 'loongarch_reloc_howto_type [124]' So either the loongarch_howto_table needs three more LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure it's worth wasting a little more space to get faster lookup. * elfxx-loongarch.c (loongarch_howto_table): Add LOONGARCH_EMPTY_HOWTO entries for 121..123. (loongarch_elf_rtype_to_howto): Don't support slow lookup. Assert exact table size and r_type indexing. Omit return cast. (loongarch_reloc_name_lookup): Omit assertion and return cast. (loongarch_reloc_type_lookup): Likewise.
2023-12-27Automatic date update in version.inGDB Administrator1-1/+1
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2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang5-11/+236
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
2023-12-25LoongArch: Add tls transition support.Lulu Cai1-1/+215
Transitions between DESC->IE/LE and IE->LE are supported now. 1. For DESC -> LE: pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 2. For DESC -> IE: pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 3. For IE -> LE: pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) add.d $a0,$a0,$tp 4. When a tls variable is accessed using both DESC and IE, DESC transitions to IE and uses the same GOT entry as IE.
2023-12-25LoongArch: Add support for TLSDESC in ld.Lulu Cai1-22/+146
1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic relocation, which relocation is placed at .rela.dyn. TLSDESC always allocates two GOT slots and one dynamic relocation space to TLSDESC. 2. When using multiple ways to access the same TLS variable, a maximum of 5 GOT slots are used. For example, using GD, TLSDESC, and IE to access the same TLS variable, GD always uses the first two of the five GOT, TLSDESC uses the third and fourth, and IE uses the last.
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai4-2/+261
The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp
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2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang2-29/+52
If the symbol index is not zero, the addend is used to represent the first and the third expressions of the .align. The lowest 8 bits are used to represent the first expression. Other bits are used to represent the third expression. The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.
2023-12-22Automatic date update in version.inGDB Administrator1-1/+1
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2023-12-20Re: PR31145, potential memory leak in binutils/ldAlan Modra2-10/+7
Revert most of this patch, it isn't correct to free the BFD_IN_MEMORY iostream in io_reinit. PR 31145 * format.c (io_reinit): Revert last change. Comment. * opncls.c (_bfd_delete_bfd): Likewise.
2023-12-19LoongArch: Allow la.got -> la.pcrel relaxation for shared objectXi Ruoyao1-2/+1
Even in shared objects, la.got -> la.pcrel relaxation can still be performed for symbols with hidden visibility. For example, if a.c is: extern int x; int f() { return x++; } and b.c is: int x = 114514; If compiling and linking with: gcc -shared -fPIC -O2 -fvisibility=hidden a.c b.c Then the la.got in a.o should be relaxed to la.pcrel, and the resulted f should be like: pcaddi $t0, x ldptr.w $a0, $t0, 0 addi.w $t1, $a0, 1 stptr.w $t1, $t0, 0 ret Remove bfd_link_executable from the condition of la.got -> la.pcrel relaxation so this will really happen. The SYMBOL_REFERENCES_LOCAL check is enough not to wrongly relax preemptable symbols (for e.g. when -fvisibility=hidden is not used). Note that on x86_64 this is also relaxed and the produced code is like: lea x(%rip), %rdx mov (%rdx), %rax lea 1(%rax), %ecx mov %ecx, (%rdx) ret Tested by running ld test suite, bootstrapping and regtesting GCC with the patched ld, and building and testing Glibc with the patched ld. No regression is observed. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2023-12-19Automatic date update in version.inGDB Administrator1-1/+1
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang5-6/+42
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
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2023-12-15Fix segmentation fault in bfd/elf32-hppa.cJohn David Anglin1-1/+3
2023-12-15 John David Anglin <danglin@gcc.gnu.org> PR ld/31148 bfd/ChangeLog: * elf32-hppa.c (elf32_hppa_finish_dynamic_symbol): Output relative reloc only when eh->root.type is bfd_link_hash_defined or bfd_link_hash_defweak.
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+1
Hi, This patch adds support for the Cortex-X3 CPU to binutils. Gas regression testing for aarch64-none-linux-gnu target and found no regressions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15PR31145, potential memory leak in binutils/ldAlan Modra4-6/+14
PR 31145 * bfd.c (BFD_IN_MEMORY): Mention that bim is malloc'd. * format.c (io_reinit): Free BFD_IN_MEMORY iostream. * opncls.c (_bfd_delete_bfd): Likewise. (bfd_make_readable): Delete unnecessary code. * bfd-in2.h: Regenerate.
2023-12-15RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'Xiao Zeng1-0/+4
This commit adds support for ratified extensions: 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'. This is based on: <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf> bfd/ChangeLog: * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'. (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
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2023-12-11bfd_find_nearest_line leaks dwarf_rnglists_bufferKonstantin Isakov1-0/+1
* dwarf2.c (_bfd_dwarf2_cleanup_debug_info): Free dwarf_rnglists_buffer.
2023-12-11regen bfd POTFILESAlan Modra2-0/+2
2023-12-11R_MICROMIPS_GPREL7_S2Alan Modra1-19/+24
This reloc is meant for the 16-bit LWGP instruction, 0x6400/0xfc00 match/mask encoding in `micromips_opcodes'. It is correctly specified to operate on a half-word by the howtos in elf32-mips.c, elfn32-mips.c and elf64-mips.c, but is incorrectly subject to shuffle/unshuffle in code like _bfd_mips_elf32_gprel16_reloc. Current behaviour when applying the reloc to .byte 0x11,0x22,0x33,0x44 is to apply the reloc to byte 0x22 when big-endian, and to byte 0x33 when little-endian. Big-endian behaviour is unchanged after this patch and little-endian correctly applies the reloc to byte 0x11. The patch also corrects REL addend extraction from section contents, and overflow checking. gold had all of the bfd problems with this reloc and additionally did not apply the rightshift by two. bfd/ * elfxx-mips.c (micromips_reloc_shuffle_p): Return false for R_MICROMIPS_GPREL7_S2. (mips_elf_calculate_relocation): Correct sign extension and overflow calculation for R_MICROMIPS_GPREL7_S2. (_bfd_mips_elf_relocate_section): Update small-data overflow message. gold/ * mips.cc (Mips_relocate_functions::should_shuffle_micromips_reloc): Return false for R_MICROMIPS_GPREL7_S2. (Mips_relocate_functions::mips_reloc_unshuffle): Update comment. (Mips_relocate_functions::relgprel): Remove R_MICROMIPS_GPREL7_S2 handling. (Mips_relocate_functions::relgprel7): New function. (Target_mips::Relocate::relocate): Adjust to suit. ld/ * testsuite/ld-mips-elf/reloc-4.d: Adjust expected error. * testsuite/ld-mips-elf/reloc-5.d: Likewise.
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2023-12-07RISC-V: Fix "withand" in LEB128 error messagesPalmer Dabbelt1-2/+2
This was split over multiple lines and ended up missing a space. Reported-by: David Abdurachmanov <davidlt@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-07Automatic date update in version.inGDB Administrator1-1/+1
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2023-12-05Fix: strip --strip-debug breaks relocationsNick Clifton2-1/+14
PR 31106 * elfcode.h (elf_write_relocs): Do not convert a relocation against a zero-value absolute symbol into a relocation without a symbol if the symbol is being used for a complex relocation.
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