Age | Commit message (Collapse) | Author | Files | Lines |
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relocation against a non-allocated readonly section.
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* elf64-ppc.c (ppc64_elf_relocate_section): Likewise. PLTGOT16_HA too.
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* Makefile.am (ALL_MACHINES): Use cpu-msp430.lo, not cpu-msp430.c.
(BFD32_BACKENDS): Use elf32-msp430.lo, not elf32-msp430.c.
* Makefile.in: Regenerate.
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(GET_RELOC_ADDEND): Use it. Parenthesize macro arguments.
(SET_RELOC_ADDEND): Parenthesize macro argument.
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adjust addil instructions if the symbol has no section.
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partial_inplace.
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PC relative relocations.
(elf_m68k_discard_copies): Set it here instead.
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(ALL_MACHINES_CFILES): Add cpu-iq2000.c.
(BFD32_BACKENDS): Add elf32-iq2000.lo.
(BFD32_BACKENDS_CFILES): Add elf32-iq2000.c.
(cpu-iq2000.lo): New target.
* Makefile.in: Regenerate.
* config.bfd: Handle iq2000-*-elf.
* archures.c (bfd_architecture): Add bfd_{arch,mach}_iq2000.
(bfd_archures_list): Add bfd_iq2000_arch.
* configure.in: Handle bfd_elf32_iq2000_vec.
* configure: Regenerate.
* reloc.c: Add BFD_RELOC_IQ2000_OFFSET_16, BFD_RELOC_IQ2000_OFFSET_21,
and BFD_RELOC_IQ2000_UHI16.
* targets.c (bfd_elf32_iq2000_vec): Declare.
(bfd_target_vector): Add bfd_elf32_iq2000_vec.
* elf.c (prep_headers): Set e_machine to EM_IQ2000.
* cpu-iq2000.c: New file.
* elf32-iq2000.c: Likewise.
* libbfd.h: Regenerate.
* bfd-in2.h: Likewise.
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* elfxx-mips.c: Include libiberty.h.
(elf_mips_isa, _bfd_mips_elf_mach_extends_p): Remove.
(mips_set_isa_flags): New function, split out from...
(_bfd_mips_elf_final_write_processing): ...here. Only call
mips_set_isa_flags if the EF_MIPS_MACH bits are clear.
(mips_mach_extensions): New array.
(mips_32bit_flags_p): New function.
(_bfd_mips_elf_merge_private_bfd_data): Rework architecture checks.
Use mips_32bit_flags_p to check if one binary is 32-bit and the
other is 64-bit. When adopting IBFD's architecture, adopt the
bfd_mach as well as the flags.
ld/testsuite/
* ld-mips-elf/jr.s: New file.
* ld-mips-elf/mips-elf-flags.exp: New test.
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2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
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(assign_file_positions_for_segments): Only adjust off/voff
for increased alignment in PT_LOAD or PT_NOTE segment,
but adjust p_filesz for .tbss too. in PT_LOAD consider
.tbss to have zero memory size.
(copy_private_bfd_data) [SECTION_SIZE]: Define.
[IS_CONTAINED_BY_VMA, IS_CONTAINED_BY_LMA]: Use it.
[INCLUDE_SECTION_IN_SEGMENT]: Only put SHF_TLS sections
into PT_TLS segment. Never put SHF_TLS sections in
segments other than PT_TLS or PT_LOAD.
* elf64-alpha.c (elf64_alpha_finish_dynamic_sections): Clear .plt
sh_entsize.
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architecture it does not recognise, unless it has explicitly told to accept
them.
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* coffcode.h: Likewise.
* cpu-cris.c: Likewise.
* elf32-vax.c: Likewise.
* genlink.h: Likewise.
* linker.c: Likewise.
* som.c: Likewise.
* tekhex.c: Likewise.
* vms-misc.c: Likewise.
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* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
* elf32-xstormy16.c (xstormy16_elf_howto): Add R_XSTORMY16_12.
(xstormy16_reloc_map): Add R_XSTORMY16_12.
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* configure.in (build-warnings): Likewise.
(Horrible hacks to build DLLs on Windows): Do not rely on "tail -1".
* aclocal.m4: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
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