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This patch adds the R_MICROBLAZE_32_NONE relocation type.
This is a 32-bit reloc that stores the 32-bit pc relative
value in two words (with an imm instruction).
Add test case to gas test suite.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
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This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9.
Maciej W. Rozycki <macro@orcam.me.uk>:
Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
...
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This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.
Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:
https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils
Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
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This reverts commit 06e8d9861d16c5b7e6920ad0e89889ccf45c575a.
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The new Synopsys's ARCv3 ISA is capable to run either 64-bit or
32-bit ISA. The new 32-bit ISA is not compatible with the old
Synopsys ARCv1/ARCv2 ISA, however, it retains a lot of common
concepts. Thus, this patch is reusing the old ARC BFD backend and
adds the necessary bits for the new architecture in a similar way as
it is done for RISCV backend.
bfd/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
Cupertino Miranda <cupertinomiranda@gmail.com>
* bfd/Makefile.am: Add ARC64 files.
* bfd/Makefile.in: Regerate.
* bfd/arc-got.h (TCB_SIZE): Depends on the target architecture.
(GOT_ENTRY_SIZE): New define.
(write_in_got): Likewise.
(read_from_got): Likewise.
(align_power): Likewise.
(arc_got_entry_type_for_reloc): Use RELA_SIZE and GOT_ENTRY_SIZE.
(arc_fill_got_info_for_reloc): Update formating.
(relocate_fix_got_relocs_for_got_info): Likewise.
(arc_static_sym_data): Deleted structure.
(get_static_sym_data): Deleted function.
(relocate_fix_got_relocs_for_got_info): Use symbol static data.
(create_got_dynrelocs_for_single_entry): Update formating.
(create_got_dynrelocs_for_got_info): Likewise.
* bfd/arc-plt.c: New file.
* bfd/arc-plt.def: Add ARC64 PLT entry.
* bfd/arc-plt.h: Clean it up, move functionality to arc-plt.c file.
* bfd/archures.c: Add ARC64 target.
* bfd/config.bfd: Likewise.
* bfd/configure.ac: Likewise.
* bfd/bfd-in2.h: Regenerate.
* bfd/configure: Likewise.
* bfd/libbfd.h: Likewise.
* bfd/cpu-arc.c: Clean it up.
* bfd/cpu-arc64.c: New file.
* bfd/elf32-arc.c: Renamed to elfnn-arc.c.
* bfd/elfnn-arc.c: New file.
* bfd/reloc.c: Add new ARC64 relocs.
* bfd/targets.c: Add ARC64 target.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d.
See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
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This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
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CGEN is cool, but the BPF architecture is simply too bizarre for it.
The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port. The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update. Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.
This is getting un-maintenable.
So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN. Overall, this involved:
* To remove the cpu/bpf.{cpu,opc} descriptions.
* To remove the CGEN generated files.
* To replace the CGEN generated opcodes table with a new hand-written
opcodes table for BPF.
* To replace the CGEN generated disassembler wih a new disassembler
that uses the new opcodes.
* To replace the CGEN generated assembler with a new assembler that uses the
new opcodes.
* To replace the CGEN generated simulator with a new simulator that uses the
new opcodes. [This is pushed in GDB in another patch.]
* To adapt the build systems to the new situation.
Additionally, this patch introduces some extensions and improvements:
* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These
relocations are used for section-relative 16-bit offsets used in
load/store instructions.
* The disassembler now has support for the "pseudo-c" assembly syntax of
BPF. What dialect to use when disassembling is controlled by a command
line option.
* The disassembler now has support for dumping instruction immediates in
either octal, hexadecimal or decimal. The used output base is controlled
by a new command-line option.
* The GAS BPF test suite has been re-structured and expanded in order to
test the disassembler pseudoc syntax support. Minor bugs have been also
fixed there. The assembler generic tests that were disabled for bpf-*-*
targets due to the previous implementation of pseudoc syntax are now
re-enabled. Additional tests have been added to test the new features of
the assembler. .dump files are no longer used.
* The linker BPF test suite has been adapted to the command line options
used by the new disassembler.
The result is very satisfactory. This patchs adds 3448 lines of code
and removes 10542 lines of code.
Tested in:
* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
little-endian host.
* Target x86-64-linux-gnu with --enable-targets=all
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port. I beg the indulgence of the global maintainers.
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Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared
to emit R_LARCH_64_PCREL.
The LoongArch ABI at here:
https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc
bfd/ChangeLog:
* bfd-in2.h (not): Add R_LARCH_64_PCREL
* elfnn-loongarch.c (perform_relocation): Likewise.
* elfxx-loongarch.c: Likewise.
* libbfd.h: Likewise.
* reloc.c: Likewise.
gas/ChangeLog:
* config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper):
(md_apply_fix): Add R_LARCH_64_PCREL.
* testsuite/gas/loongarch/64_pcrel.d: New test.
* testsuite/gas/loongarch/64_pcrel.s: New test.
include/ChangeLog:
* elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test.
* testsuite/ld-loongarch-elf/64_pcrel.d: New test.
* testsuite/ld-loongarch-elf/64_pcrel.s: New test.
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Add relax support and related relocs in bfd.
bfd/ChangeLog:
* bfd-in2.h: Add relocs related to relax.
* elfnn-loongarch.c (struct loongarch_elf_link_hash_table): New integer
pointer (data_segment_phase) to monitor the data segment phase.
(loongarch_elf_check_relocs): Swap B21/B26 reloc sequence.
(loongarch_elf_adjust_dynamic_symbol): Fix code format.
(loongarch_reloc_rewrite_imm_insn): Fix function call.
(perform_relocation): Handle new relocs related to relax.
(RELOCATE_CALC_PC32_HI20): Fix code format.
(RELOCATE_CALC_PC64_HI32): Likewise.
(loongarch_elf_relocate_section): Handle new relocs related to relax.
(loongarch_relax_delete_bytes): New function.
(loongarch_relax_pcala_addi): Likewise.
(loongarch_relax_pcala_ld): Likewise.
(bfd_elfNN_loongarch_set_data_segment_info): Likewise.
(loongarch_relax_align): Likewise.
(loongarch_elf_relax_section): Likewise.
(bfd_elfNN_bfd_relax_section): New macro define.
* elfxx-loongarch.c (reloc_bits): New bfd point parameter.
(reloc_bits_b16): Likewise.
(reloc_bits_b21): Likewise.
(reloc_bits_b26): Likewise.
(loongarch_adjust_reloc_bitsfield): Likewise.
(reloc_bits_pcrel20_s2): New function.
(loongarch_elf_add_sub_reloc): Likewise.
(loongarch_elf_add_sub_reloc_uleb128): Likewise.
(loongarch_write_unsigned_leb128): New function.
* elfxx-loongarch.h (loongarch_adjust_reloc_bitsfield): New bfd point
parameter.
(bfd_elf32_loongarch_set_data_segment_info): New declare.
(bfd_elf64_loongarch_set_data_segment_info): Likewise.
(loongarch_write_unsigned_leb128): Likewise.
* libbfd.h: Add relocs related to relax.
* reloc.c: Add relocs related to relax.
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https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/96d6e190e9fc04a8517f9ff7fb9aed3e9876cbd6
There are some known limitations for now,
* Do not shrink the length of the uleb128 value, even if the value is reduced
after relaxations. Also reports error if the length grows up.
* The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the
R_RISCV_SUB_ULEB128.
bfd/
* bfd-in2.h: Regenerated.
* elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the
uleb128 value, and report error if the length grows up. Called the
generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128,
to encode the uleb128 into the section contents.
(riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128
must be paired with and be placed before the R_RISCV_SUB_ULEB128.
* elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128.
(riscv_reloc_map): Likewise.
(riscv_elf_ignore_reloc): New function.
* libbfd.h: Regenerated.
* reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128):
New relocations to support .uleb128 subtraction.
gas/
* config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128
and BFD_RELOC_RISCV_SUB_ULEB128.
(s_riscv_leb128): Updated to allow uleb128 subtraction.
(riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction
expressions and insert fixups for them.
(riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections.
include/
* elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction.
binutils/
* testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
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bfd/doc/chew.c extracts documentation from source code comments
annotated with keywords, and generates much of bfd.h and libbfd.h from
those same comments. The docs have suffered from people (me too)
adding things like CODE_FRAGMENT to the source to put code into bfd.h
without realising that CODE_FRAGMENT also puts @example around said
code into the docs. So we have random senseless things in the docs.
This patch fixes that problem (well, the senseless things from
CODE_FRAGMENT), moves most of the code out of bfd-in.h, and improves a
few chew.c features. libbfd.h now automatically gets ATTRIBUTE_HIDDEN
prototypes, and indentation in bfd.h and libbfd.h is better.
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- Removed not needed relocations.
- Renamed relocations to match llvm and linux kernel.
Relocation changes:
R_BPF_INSN_64 => R_BPF_64_64
R_BPF_INSN_DISP32 => R_BPF_64_32
R_BPF_DATA_32 => R_BPF_64_ABS32
R_BPF_DATA_64 => R_BPF_64_ABS64
ChangeLog:
* bfd/bpf-reloc.def: Created file with BPF_HOWTO macro entries.
* bfd/reloc.c: Removed non needed relocations.
* bfd/bfd-in2.h: regenerated.
* bfd/libbfd.h: regenerated.
* bfd/elf64-bpf.c: Changed relocations.
* include/elf/bpf.h: Adapted relocation values/names.
* gas/config/tc-bpf.c: Changed relocation mapping.
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This adds a new flag to the reloc howtos that can be used to
incrementally change targets over to simple bfd_install_relocation
that just installs the addend without any weird adjustments.
I've made a few other changes to bfd_install_relocation, removing dead
code and comments that are really only applicable to
bfd_perform_relocation.
There is also a reloc offset bounds check change. I've moved the
check to where data is accessed, as it seems reasonable to me to not
perform the check unless it is needed. There is precedence for this;
Relocations against absolute symbols already avoided the check.
I also tried always performing the reloc offset check, and ran into
testsuite failures due to _NONE and _ALIGN relocs at the end of
sections. These likely would be fixed if all such reloc howtos had
size set to zero, but I would rather not edit lots of files when it
involves checking that target code does not use the size.
* reloc.c (struct reloc_howto_struct): Add install_addend.
(HOWTO_INSTALL_ADDEND): Define.
(HOWTO): Init new field with HOWTO_INSTALL_ADDEND.
(bfd_install_relocation): Remove comments copied from
bfd_perform_relocation that aren't applicable here. Remove
code dealing with output_offset and output_section. Just set
relocation to addend if install_addend. Move reloc offset
bounds check to just before section data is accessed, avoiding
the check when data is not accessed.
* bfd-in2.h: Regenerate.
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* reloc.c (bfd_perform_relocation, bfd_install_relocation): Remove
i960-coff target hack.
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The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
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This patch removes the bfd_malloc in default_indirect_link_order and
bfd_simple_get_relocated_section_contents, pushing the allocation down
to bfd_get_relocated_section_contents. The idea is to make use of the
allocation done with sanity checking in bfd_get_full_section_contents,
which is called by bfd_generic_get_relocated_section_contents.
Doing this exposed a bug in bfd_get_full_section_contents. With
relaxation it is possible that an input section rawsize is different
to the section size. In that case we want to use the larger of
rawsize (the on-disk size for input sections) and size.
* reloc.c (bfd_generic_get_relocated_section_contents),
* reloc16.c (bfd_coff_reloc16_get_relocated_section_contents),
* coff-alpha.c (alpha_ecoff_get_relocated_section_contents),
* coff-sh.c (sh_coff_get_relocated_section_contents),
* elf-m10200.c (mn10200_elf_get_relocated_section_contents),
* elf-m10300.c (mn10300_elf_get_relocated_section_contents),
* elf32-avr.c (elf32_avr_get_relocated_section_contents),
* elf32-cr16.c (elf32_cr16_get_relocated_section_contents),
* elf32-crx.c (elf32_crx_get_relocated_section_contents),
* elf32-h8300.c (elf32_h8_get_relocated_section_contents),
* elf32-nds32.c (nds32_elf_get_relocated_section_contents),
* elf32-sh.c (sh_elf_get_relocated_section_contents),
* elfxx-mips.c (_bfd_elf_mips_get_relocated_section_contents):
Handle NULL data buffer.
* bfd.c (bfd_get_section_alloc_size): New function.
* bfd-in2.h: Regenerate.
* compress.c (bfd_get_full_section_contents): Correct section
malloc size.
* linker.c (default_indirect_link_order): Don't malloc memory
here before calling bfd_get_relocated_section_contents.
* simple.c (bfd_simple_get_relocated_section_contents): Likewise.
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This tidies SEC_RELOC handling in bfd, in the process fixing a bug
with objcopy when renaming sections.
bfd/
* reloc.c (_bfd_generic_set_reloc): Set/clear SEC_RELOC depending
on reloc count.
* elf64-sparc.c (elf64_sparc_set_reloc): Likewise.
binutils/
* objcopy.c (copy_relocations_in_section): Remove now unnecessary
clearing of SEC_RELOC.
* testsuite/binutils-all/rename-section-01.d: New test.
* testsuite/binutils-all/objcopy.exp: Run it.
gas/
* write.c (size_seg): Remove unneccesary twiddle of SEC_RELOC.
(write_relocs): Likewise. Always call bfd_set_reloc.
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Don't overload bfd_reloc_outofrange with what is really a domain error
(target at odd address), or an overflow.
PR 11290
* reloc.c (bfd_reloc_other): Correct comment.
* elf32-avr.c (avr_final_link_relocate): Return bfd_reloc_other
for unaligned reloc target values. Return bfd_reloc_overflow
when stubs are too far away and when R_AVR_LDS_STS_16,
R_AVR_PORT6, or R_AVR_PORT5 overflow.
(elf32_avr_relocate_section): Report more descriptive relocation
errors.
* bfd-in2.h: Regenerate.
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Some R_LARCH_64 in section .eh_frame will to generate
R_LARCH_NONE, we change relocation to R_LARCH_32_PCREL
from R_LARCH_64 in setction .eh_frame and not generate
dynamic relocation for R_LARCH_32_PCREL.
Add New relocate type R_LARCH_32_PCREL for .eh_frame.
include/elf/
loongarch.h
bfd/
bfd/bfd-in2.h
libbfd.h
reloc.c
elfxx-loongarch.c
elfnn-loongarch.c
gas/config/
tc-loongarch.c
binutils/
readelf.c
ld/testsuite/ld-elf/
eh5.d
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Define new reloc types according to linker needs.
include/elf/
loongarch.h
bfd/
bfd-in2.h
libbfd.h
reloc.c
elfnn-loongarch.c
elfxx-loongarch.c
elfxx-loongarch.h
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Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved
the architecture from the "obsolete but still available" to the
"obsolete / support removed" list in config.bfd, making the architecture
impossible to enable (except maybe via "enable everything" options").
Note that I didn't touch */po/*.po{,t} on the assumption that these
would be updated by some (half)automatic means.
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MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation,
since R_MIPS_16 specifies a 16-bit field in a 32-bit word.
BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data
directives, expects fixups to operate on the whole of a 16-bit word.
This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd
reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in
md_apply_fix for cases where the fixup can be applied at assembly
time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object
file relocation, and thus .half, .hword, .short and .dc.w must be
resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this
patch since it isn't used.
PR 3243
PR 26542
* reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16.
* elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16.
* elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16.
* elfn32-mips.c (mips_reloc_map): Likewise.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16.
(macro_build): Likewise.
(mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16.
(md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done.
ld/
* testsuite/ld-mips-elf/reloc-local-overflow.d,
* testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
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I expect the encoded reloc.size field originally came from aout
r_length ecoding, but somehow went wrong for 64-bit relocs (which
should have been encoded as 3). Toss all that out, just use a byte
size instead. The changes outside of reloc.c in this patch should
make the code independent of how reloc.size is encoded.
* reloc.c (struct reloc_howto_struct): Increase size field by
one bit. Comment.
(HOWTO_RSIZE): Don't encode size.
(bfd_get_reloc_size): Adjust, and make it an inline function.
(read_reloc, write_reloc): Adjust.
* bfd-in2.h: Regenerate.
* aout-ns32k.c: Include libbfd.h.
(put_reloc): Don't use howto->size directly. Calculate r_length
using bfd_log2 and bfd_get_reloc_size.
* aoutx.h (swap_std_reloc_out): Likewise.
(aout_link_reloc_link_order): Likewise.
* i386lynx.c (swap_std_reloc_out
* mach-o-i386.c (bfd_mach_o_i386_swap_reloc_out
* pdp11.c (aout_link_reloc_link_order
* coff-arm.c (coff_arm_reloc): Don't use howto->size directly,
use bfd_get_reloc_size instead and adjust switch cases.
* coff-i386.c (coff_i386_reloc): Similarly.
* coff-x86_64.c (coff_amd64_reloc): Likewise.
* cpu-ns32k.c (do_ns32k_reloc): Likewise.
* elf32-arc.c (arc_do_relocation): Likewise.
* elf32-arm.c (elf32_arm_final_link_relocate): Likewise.
* elf32-bfin.c (bfin_bfd_reloc): Likewise.
* elf32-cr16.c (cr16_elf_final_link_relocate): Likewise.
* elf32-cris.c (cris_elf_pcrel_reloc): Likewise.
* elf32-crx.c (crx_elf_final_link_relocate): Likewise.
* elf32-csky.c (csky_elf_relocate_section): Likewise.
* elf32-d10v.c (extract_rel_addend, insert_rel_addend): Likewise.
* elf32-i386.c (elf_i386_relocate_section): Likewise.
* elf32-m32r.c (m32r_elf_generic_reloc): Likewise.
* elf32-nds32.c (nds32_elf_generic_reloc): Likewise.
* syms.c (_bfd_stab_section_find_nearest_line): Likewise.
* coff-rs6000.c (xcoff_ppc_relocate_section): Adjust howto.size.
* coff64-rs6000.c (xcoff64_ppc_relocate_section): Likewise.
|
|
This changes the HOWTO macro to encode the howto.size field from a
value given in bytes. This of course requires editing all target
uses of HOWTO, a major pain, but makes it a little nicer to specify
new target HOWTOs. Object files before/after this patch are
unchanged in .data and .rodata.
bfd/
* reloc.c (HOWTO_RSIZE): Encode size in bytes.
(EMPTY_HOWTO): Adjust to keep it all zero.
* aout-ns32k.c, * aoutx.h, * coff-alpha.c, * coff-arm.c,
* coff-i386.c, * coff-mcore.c, * coff-mips.c, * coff-rs6000.c,
* coff-sh.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
* elf-hppa.h, * elf-m10200.c, * elf-m10300.c, * elf32-arc.c,
* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
* elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c,
* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
* elf32-h8300.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c,
* elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c,
* elf32-m68hc12.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c,
* elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c,
* elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s12z.c,
* elf32-s390.c, * elf32-score.c, * elf32-score7.c,
* elf32-sh-relocs.h, * elf32-spu.c, * elf32-tic6x.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c,
* elf32-visium.c, * elf32-wasm32.c, * elf32-xc16x.c,
* elf32-xgate.c, * elf32-xstormy16.c, * elf32-xtensa.c,
* elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-gen.c,
* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
* elf64-s390.c, * elf64-x86-64.c, * elfn32-mips.c,
* elfnn-aarch64.c, * elfxx-ia64.c, * elfxx-loongarch.c,
* elfxx-mips.c, * elfxx-riscv.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * mach-o-aarch64.c, * mach-o-arm.c,
* mach-o-i386.c, * mach-o-x86-64.c, * pdp11.c, * reloc.c,
* som.c, * vms-alpha.c: Adjust all uses of HOWTO.
* bfd-in2.h: Regenerate.
include/
* elf/arc-reloc.def: Adjust all uses of HOWTO.
|
|
Define a helper macro for HOWTO.
* reloc.c (HOWTO_RSIZE): Define.
(HOWTO): Use it.
* bfd-in2.h: Regenerate.
|
|
Make them all zero size standard do-nothing howtos.
* elf32-csky.c (csky_elf_howto_table <R_CKCORE_NONE>): Correct howto.
* elf32-ft32.c (ft32_elf_howto_table <R_FT32_NONE>): Likewise.
* elf32-gen.c (dummy): Likewise.
* elf32-nds32.c (none_howto): Likewise.
* elf32-nios2.c (elf_nios2_r2_howto_table_rel <R_NIOS2_NONE>):
Likewise.
* elf32-pru.c (elf_pru_howto_table_rel <R_PRU_NONE>): Likewise.
* elf32-v850.c (v800_elf_howto_table <R_V810_NONE>): Likewise.
* elf64-gen.c (dummy): Likewise.
* elfn32-mips.c (elf_mips_howto_table_rela <R_MIPS_NONE): Likewise.
* elfxx-mips.c (none_howto): Likewise.
* reloc.c (none_howto): Likewise.
|
|
bfd * coff-i386.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_i386_relocation_section): Add support for R_SECTION.
(coff_i386_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* coff-x86_64.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_amd64_relocation_section): Add support for R_SECTION.
(coff_amd64_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* reloc.c: Add BFD_RELOC_16_SECIDX.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas * config/tc-i386.c (pe_directive_secidx): New function.
(md_pseudo_table): Add support for secidx.
(x86_cons_fix_new): Likewise.
(tc_gen_reloc): Likewise.
* expr.c (op_rank): Add O_secidx.
* expr.h (operatorT): Likewise.
* symbols.c (resolve_symbol_value): Add support for O_secidx.
* testsuite/gas/i386/secidx.s: New test source file.
* testsuite/gas/i386/secidx.d: New test driver file.
* testsuite/gas/i386/i386.exp: Run new test.
include * coff/i386.h: Define R_SECTION.
* coff/x86_64.h: Likewise.
ld * testsuite/ld-pe/secidx1.s: New test source file.
* testsuite/ld-pe/secidx2.s: New test source file.
* testsuite/ld-pe/secidx.d: New test driver file.
* testsuite/ld-pe/secidx_64.d: New test driver file.
* testsuite/ld-pe/pe.exp: Add new tests.
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on
@notoc cals from non-power10 code in the rare case that using such a
construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas
rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch
instruction if power10 instructions are not enabled at that point.
The new relocation tells the linker to not use power10 instructions on
any stub emitted for that branch, unless overridden by
--power10-stubs=yes.
The current linker heuristic of only generating power10 instructions
for stubs if power10-only relocations are detected, continues to be
used.
include/
* elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc.
(ppc64_elf_reloc_type_lookup): Handle it.
(enum ppc_stub_type): Delete.
(enum ppc_stub_main_type, ppc_stub_sub_type): New.
(struct ppc_stub_type): New.
(struct ppc_stub_hash_entry): Use the above new type.
(struct ppc_link_hash_table): Update stub_count.
(is_branch_reloc, ppc64_elf_check_relocs),
(toc_adjusting_stub_needed): Handle new reloc.
(stub_hash_newfunc, select_alt_stub, ppc_merge_stub),
(ppc_type_of_stub, plt_stub_size, build_plt_stub),
(build_tls_get_addr_head, build_tls_get_addr_tail),
(ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs),
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new
reloc. Modify stub handling to suit new scheme.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled
return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc.
(fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle
BFD_RELOC_PPC64_REL24_P9NOTOC.
ld/
* testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
|
|
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn>
Zhensong Liu <liuzhensong@loongson.cn>
Weinan Liu <liuweinan@loongson.cn>
bfd/
* Makefile.am: Add LoongArch.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* cpu-loongarch.c: New.
* elf-bfd.h: Add LoongArch.
* elf.c: Add LoongArch elfcore_grok_xxx.
* elfnn-loongarch.c: New.
* elfxx-loongarch.c: New.
* elfxx-loongarch.h: New.
* reloc.c: Add LoongArch BFD RELOC ENUM.
* targets.c: Add LoongArch target.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
include/
* elf/common.h: Add NT_LARCH_{CPUCFG,CSR,LSX,LASX}.
* elf/loongarch.h: New.
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|
This patch is more about the style of bounds checking we ought to use,
rather than a real problem. An overflow of "octet + reloc_size" can
only happen with huge sections which would certainly cause out of
memory errors.
* reloc.c (bfd_reloc_offset_in_range): Avoid possible overflow.
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The gotha() relocation mnemonic will be outputted by OpenRISC GCC when
using the -mcmodel=large option. This relocation is used along with
got() to generate 32-bit GOT offsets. This increases the previous GOT
offset limit from the previous 16-bit (64K) limit.
This is needed on large binaries where the GOT grows larger than 64k.
bfd/ChangeLog:
PR 21464
* bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation.
* elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise.
(or1k_final_link_relocate, or1k_elf_relocate_section,
or1k_elf_check_relocs): Likewise.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: Likewise.
cpu/ChangeLog:
PR 21464
* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
for gotha() relocation.
include/ChangeLog:
PR 21464
* elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number.
opcodes/ChangeLog:
PR 21464
* or1k-asm.c: Regenerate.
gas/ChangeLog:
PR 21464
* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
* testsuite/gas/or1k/reloc-1.d: Add test result for new
relocation.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
fixup reloc, add tests
|
|
order to manage C++ exceptions built with GCC.
bfd PR binutils/21700
* reloc.c (BFD_RELOC_PPC_NEG): New relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* coff-rs6000.c (_bfd_xcoff_reloc_type_lookup): Add
BFD_RELOC_PPC_NEG handler.
(xcoff_reloc_type_neg): Correctly substract addend.
* coff64-rs6000.c (xcoff64_howto_table): Add R_NEG_32
howto.
(xcoff64_rtype2howto): Add handler for R_NEG_32.
(xcoff64_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler.
* xcofflink.c (xcoff_need_ldrel_p): Check output section
for R_POS-like relocations. New argument added.
(xcoff_mark): Adapt to new xcoff_need_ldrel_p argument.
(xcoff_link_input_bfd): Likewise.
gas * config/tc-ppc.c (ppc_get_csect_to_adjust): New function.
(ppc_fix_adjustable): Manage fx_subsy part.
(tc_gen_reloc): Create second relocation when both
fx_addsy and fx_subsy are provided.
* config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define.
(MAX_RELOC_EXPANSION): Likewise.
(TC_FORCE_RELOCATION_SUB_SAME): Likewise
(UNDEFINED_DIFFERENCE_OK): Likewise
* testsuite/gas/all/gas.exp: Skip difference between two
undefined symbols test.
ld * testsuite/ld-powerpc/aix52.exp: Add new test.
* testsuite/ld-powerpc/aix-neg-reloc-32.d: New test.
* testsuite/ld-powerpc/aix-neg-reloc-64.d: New test.
* testsuite/ld-powerpc/aix-neg-reloc.ex: New test.
* testsuite/ld-powerpc/aix-neg-reloc.s: New test.
|
|
* sysdep.h: POISON_BFD_BOOLEAN: Define.
* aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h,
* aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c,
* bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c,
* coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c,
* coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c,
* coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c,
* coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
* coffcode.h, * coffgen.c, * cofflink.c, * compress.c,
* corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c,
* cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c,
* cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c,
* cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c,
* cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c,
* cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c,
* cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c,
* cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c,
* cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c,
* cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c,
* cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c,
* cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c,
* cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c,
* cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c,
* cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c,
* cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c,
* cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c,
* cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c,
* cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c,
* cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c,
* cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c,
* dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c,
* elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c,
* elf-nacl.h, * elf-properties.c, * elf-s390-common.c,
* elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h,
* elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c,
* elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c,
* elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c,
* elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c,
* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
* elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
* elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c,
* elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
* elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c,
* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
* elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c,
* elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h,
* elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h,
* elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h,
* elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
* elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c,
* elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c,
* elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c,
* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
* elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c,
* elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h,
* elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c,
* elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c,
* elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h,
* elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h,
* elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h,
* elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h,
* format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c,
* i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h,
* libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h,
* libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c,
* mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h,
* merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c,
* pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c,
* pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c,
* pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c,
* peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c,
* reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c,
* som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c,
* verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h,
* wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c,
* xsym.h: Replace bfd_boolean with bool, FALSE with false, and
TRUE with true throughout.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* libcoff.h: Regenerate.
|
|
Add support for TLS in XCOFF. Amongst the things done by this commit:
- Update XCOFF auxialiary header to match new version and allow TLS
sections.
- Add TLS sections (.tdata and .tbss) support in gas and ld.
- Add support for the TLS relocations in gas and ld.
Two different types BFD_RELOC are created for PPC and PPC64 as
the size is a pointer, thus distinct in 32 or 64bit.
The addresses given by ld to .tdata and .tbss is a bit special. In
XCOFF, these addresses are actually offsets from the TLS pointer
computed at runtime. AIX assembly and linker does the same. In
top of that, the .tdata must be before .data (this is mandatory for AIX
loader). Thus, the aix ld script is recomputing "." before .data to restore
its original value. There might be a simpler way, but this one is working.
Optimisation linked to TLS relocations aren't yet implemented.
bfd/
* reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE,
BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD,
BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE,
BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M,
BFD_RELOC_PPC64_TLS_ML): New relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* coff-rs6000.c (xcoff_calculate_relocation): Call
xcoff_reloc_type_tls for TLS relocations.
(xcoff_howto_table): Implement TLS relocations.
(_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations.
(xcoff_reloc_type_tls): New function.
* coff64-rs6000.c (xcoff_calculate_relocation): Likewise.
(xcoff_howto_table): Likewise.
(_bfd_xcoff_reloc_type_lookup): Likewise.
* coffcode.h (sec_to_styp_flags): Handle TLS sections.
(styp_to_sec_flags): Likewise.
(coff_compute_section_file_positions): Avoid file offset
optimisation for .data when the previous section is .tdata.
(coff_write_object_contents): Handle TLS sections.
* coffswap.h (coff_swap_aouthdr_out): Add support for
new fields in aouthdr.
* libxcoff.h (xcoff_reloc_type_tls): Add prototype.
* xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL.
(xcoff_need_ldrel_p): Add cases for TLS relocations.
(xcoff_create_ldrel): Add l_symndx for TLS sections.
gas/
* config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section,
(ppc_xcoff_bss_section, ppc_xcoff_tdata_section,
(ppc_xcoff_tbss_section): New variables.
(ppc_text_subsegment, ppc_text_csects, ppc_data_subgments,
(ppc_data_csects): Removed.
(ppc_xcoff_section_is_initialized, ppc_init_xcoff_section,
ppc_xcoff_parse_cons): New functions.
(md_being): Initialize XCOFF sections.
(ppc_xcoff_suffix): Add support for TLS relocations
(fixup_size, md_apply_fix): Add support for new BFD_RELOC.
(ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS
to .bss section. Handle new XCOFF section variables.
(ppc_comm): Likewise.
(ppc_toc): Likewise.
(ppc_symbol_new_hook): Likewise.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Add tbss support.
* config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define.
(ppc_xcoff_parse_cons): Add prototype.
(struct ppc_xcoff_section): New structure.
ld/
* emultempl/aix.em: Ensure .tdata section is removed
if empty, even with -r flag.
* scripttempl/aix.sc: Handle TLS sections.
* testsuite/ld-powerpc/aix52.exp: Add new tests.
* testsuite/ld-powerpc/aix-tls-reloc-32.d: New test.
* testsuite/ld-powerpc/aix-tls-reloc-64.d: New test.
* testsuite/ld-powerpc/aix-tls-reloc.ex: New test.
* testsuite/ld-powerpc/aix-tls-reloc.s: New test.
* testsuite/ld-powerpc/aix-tls-section-32.d: New test.
* testsuite/ld-powerpc/aix-tls-section-64.d: New test.
* testsuite/ld-powerpc/aix-tls-section.ex: New test.
* testsuite/ld-powerpc/aix-tls-section.s: New test.
include/
* coff/internal.h (struct internal_aouthdr): Add new fields.
* coff/rs6000.h (AOUTHDRÃ): Add new fields.
* coff/rs6k64.h (struct external_filehdr): Likewise.
* coff/xcoff.h (_TDATA), _TBSS): New defines
(RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA,
RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY,
RS6K_AOUTHDR_FORK_COR): New defines.
(XMC_TU): Removed.
(XMC_UL): New define.
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Implement support for largetoc on XCOFF.
R_TOCU and R_TOCL are referenced by the new BFD defines:
BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO.
A new toc storage class is added XMC_TE.
In order to correctly handle R_TOCU, the logic behind
xcoff_reloc_type_toc is changed to compute the whole TOC offset
instead of just the difference between the "link" offset and the
"assembly" offset.
In gas, add a function to transform addis format used by AIX
"addis RT, D(RA)" into the ELF format "addis RT, RA, SI".
bfd/
* reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO):
New relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* coff-rs6000.c (xcoff_calculate_relocation): Call
xcoff_reloc_type_toc for R_TOCU and R_TOCL.
(xcoff_howto_table): Remove src_mask for TOC relocations.
Add R_TOCU and R_TOCL howtos.
(_bfd_xcoff_reloc_type_lookup): Add cases for
BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO.
(xcoff_reloc_type_toc): Compute the whole offset.
Implement R_TOCU and R_TOCL.
* coff64-rs6000.c (xcoff64_calculate_relocation):
Likewise.
(xcoff64_howto_table): Likewise.
(xcoff64_reloc_type_lookup): Likewise.
gas/
* config/tc-ppc.c (ppc_xcoff_suffix): New function.
(MAP, MAP32, MAP64): New macros for XCOFF.
(ppc_xcoff_fixup_addis): New function.
(ppc_is_toc_sym): Handle XMC_TE.
(fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
(md_assemble): Call ppc_xcoff_fixup_addis for XCOFF.
(ppc_change_csect): Handle XMC_TE.
(ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE
storage class.
(ppc_symbol_new_hook): Handle XMC_TE.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Likewise.
(md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
ld/
* scripttempl/aix.sc: Add .te to .data section.
* testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+.
Add aix-largetoc-1 test.
* testsuite/ld-powerpc/aix-largetoc-1-32.d: New test.
* testsuite/ld-powerpc/aix-largetoc-1-64.d: New test.
* testsuite/ld-powerpc/aix-largetoc-1.ex: New test.
* testsuite/ld-powerpc/aix-largetoc-1.s: New test.
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bfd_perform_relocation should not have special case target code. This
patch moves the code that was there for x86_64 PE linking to ELF
output into the x86_64 PE howto special function, correcting that
function for linking to targets other than ELF too. The fixes in
bfd_perform_relocation were over-complicated due to needing to
compensate for things that had already gone wrong in coff_amd64_reloc.
In particular, an adjustment for pc-relative relocs was done in a way
that meant adjustment for things related to symbol offsets was lost.
I think those two things are orthogonal, but who knows with COFF where
addends and symbol values are found randomly in the section contents.
Note that linking natively to an x86_64 PE output relocates by
coff_pe_amd64_relocate_section, which does not use arelent relocs or
bfd_perform_relocation, but be aware of coff_amd64_rtype_to_howto
hacking addends for relocations. The adjustments for a particular
relocation type there and in coff_amd64_reloc ought to match after
taking into consideration CALC_ADDEND. They don't. For example,
the pc-relative adjustment for R_PCRWORD is 2 bytes in
coff_amd64_reloc and 4 bytes in coff_amd64_rtype_to_howto.
* reloc.c (bfd_perform_relocation): Revert 2021-01-12 and
2020-09-16 changes.
* coff-x86_64.c (coff_amd64_reloc): Do more or less the same
adjustments here instead. Separate pc-relative adjustments
from symbol related adjustments. Tidy comments and formatting.
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include/
* coff/internal.h: Delete obsolete relocation defines. Move used
relocation defines..
* coff/i386.h: ..to here..
* coff/ti.h: ..and here..
* coff/x86_64.h: ..and here..
* coff/z80.h: ..and here..
* coff/z8k.h: ..and here.
bfd/
* reloc.c: Include x86_64.h rather than internal.h.
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Subtract the value of the section contents for R_AMD64_DIR64 and
R_AMD64_DIR32 relocations when generating ELF output from PE/x86-64
inputs.
bfd/
PR ld/27171
* reloc.c (bfd_perform_relocation): Adjust R_AMD64_DIR64 and
R_AMD64_DIR32 relocations for PE/x86-64 inputs.
ld/
PR ld/27171
* testsuite/ld-x86-64/pe-x86-64-5.obj.bz2: New file.
* testsuite/ld-x86-64/pe-x86-64-5.od: Likewise.
* testsuite/ld-x86-64/pe-x86-64-5.rd: Likewise.
* testsuite/ld-x86-64/pe-x86-64.exp: Run PR ld/27171 test.
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PE linker calls _bfd_relocate_contents to resolve relocation, instead of
bfd_perform_relocation. But ELF linker calls bfd_perform_relocation, not
_bfd_relocate_contents. When linking PE/x86-64 inputs to generate ELF
output, we need to adjust PE/x86-64 relocations in bfd_perform_relocation.
Enable PE/x86-64 in bfd together with PEI/x86-64. Update run_ld_link_tests
to handle bzip2 binary inputs.
bfd/
PR ld/26583
* config.bfd (targ64_selvecs, targ_selvecs): Add x86_64_pe_vec
to x86_64_pei_vec.
* reloc.c: Include "coff/internal.h".
(bfd_perform_relocation): Adjust relocation for PE/x86-64 inputs.
ld/
PR ld/26583
* testsuite/ld-x86-64/pe-x86-64-1.od: New file.
* testsuite/ld-x86-64/pe-x86-64-1a.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-1b.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-1c.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-2.od: Likewise.
* testsuite/ld-x86-64/pe-x86-64-2a.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-2b.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-2c.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-3.od: Likewise.
* testsuite/ld-x86-64/pe-x86-64-3a.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-3b.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-3c.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-3d.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-4.od: Likewise.
* testsuite/ld-x86-64/pe-x86-64-4a.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-4b.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-4c.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64-4d.obj.bz2: Likewise.
* testsuite/ld-x86-64/pe-x86-64.exp: Likewise.
* testsuite/lib/ld-lib.exp (run_ld_link_tests): Handle bz2 binary
inputs.
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Link-time relaxations of branches are common for MSP430, given that GCC
can generate pessimal branch instructions, and the
-mcode-region=either/-mdata-region=either options to shuffle sections
can further change the type of branch instruction required.
These relaxations can result in invalid code when .uleb128
directives, used in the .gcc_except_table section, are used to calculate
the distance between two labels. A value for the .uleb128 directive is
calculated at assembly-time, and can't be updated at link-time, even if
relaxation causes the distance between the labels to change.
This patch adds relocations for subtract expressions in .uleb128
directives, to allow the linker to re-calculate the value of these
expressions after relaxation has been performed.
bfd/ChangeLog:
* bfd-in2.h (bfd_reloc_code_real): Add
BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* elf32-msp430.c (msp430_elf_ignore_reloc): New.
(elf_msp430_howto_table): Add R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
(msp430_reloc_map): Add R_MSP430_GNU_{SET,SUB}_ULEB128.
(msp430x_reloc_map): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
(write_uleb128): New.
(msp430_final_link_relocate): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
* libbfd.c (_bfd_write_unsigned_leb128): New.
* libbfd.h (_bfd_write_unsigned_leb128): New prototype.
Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* reloc.c: Document BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
binutils/ChangeLog:
* readelf.c (target_specific_reloc_handling): Handle
R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
gas/ChangeLog:
* config/tc-msp430.c (msp430_insert_uleb128_fixes): New.
(msp430_md_end): Call msp430_insert_uleb128_fixes.
include/ChangeLog:
* elf/msp430.h (elf_msp430_reloc_type): Add
R_MSP430_GNU_{SET,SUB}_ULEB128.
(elf_msp430x_reloc_type): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
ld/ChangeLog:
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
* testsuite/ld-msp430-elf/uleb128.s: New test.
* testsuite/ld-msp430-elf/uleb128_430.d: New test.
* testsuite/ld-msp430-elf/uleb128_430x.d: New test.
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* reloc.c (N_ONES): Handle N=0.
* elf32-arm.c (elf32_arm_howto_table_1): Set complain_overflow_dont
for R_ARM_TLS_DESCSEQ and R_ARM_THM_TLS_DESCSEQ.
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PR 26462
* reloc.c (bfd_check_overflow): Return early if zero bitsize.
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These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
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Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
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Labels don't go in the first column according to standard emacs C
indent rules, and I got annoyed enough at seeing diff -p show a label
rather than the function name to fix this.
bfd/
* aoutx.h: Indent labels correctly. Format error strings.
* archive.c: Likewise.
* archive64.c: Likewise.
* coff-arm.c: Likewise.
* coff-rs6000.c: Likewise.
* coff-stgo32.c: Likewise.
* cpu-arm.c: Likewise.
* dwarf2.c: Likewise.
* elf-ifunc.c: Likewise.
* elf-properties.c: Likewise.
* elf-s390-common.c: Likewise.
* elf-strtab.c: Likewise.
* elf.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-cr16.c: Likewise.
* elf32-csky.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-m68k.c: Likewise.
* elf32-msp430.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-nios2.c: Likewise.
* elf32-pru.c: Likewise.
* elf32-xtensa.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-x86-64.c: Likewise.
* elfcode.h: Likewise.
* elfcore.h: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfnn-riscv.c: Likewise.
* elfxx-mips.c: Likewise.
* elfxx-sparc.c: Likewise.
* elfxx-x86.c: Likewise.
* i386lynx.c: Likewise.
* merge.c: Likewise.
* pdp11.c: Likewise.
* plugin.c: Likewise.
* reloc.c: Likewise.
binutils/
* elfedit.c: Indent labels correctly.
* readelf.c: Likewise.
* resres.c: Likewise.
gas/
* config/obj-elf.c: Indent labels correctly.
* config/obj-macho.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-riscv.c: Likewise.
* config/tc-s12z.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* read.c: Likewise.
* symbols.c: Likewise.
* write.c: Likewise.
ld/
* emultempl/cskyelf.em: Indent labels correctly.
* ldfile.c: Likewise.
* ldlang.c: Likewise.
* plugin.c: Likewise.
opcodes/
* aarch64-asm.c: Indent labels correctly.
* aarch64-dis.c: Likewise.
* aarch64-gen.c: Likewise.
* aarch64-opc.c: Likewise.
* alpha-dis.c: Likewise.
* i386-dis.c: Likewise.
* nds32-asm.c: Likewise.
* nfp-dis.c: Likewise.
* visium-dis.c: Likewise.
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