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path: root/bfd/reloc.c
AgeCommit message (Expand)AuthorFilesLines
2020-09-08MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz1-0/+5
2020-09-01arm: ubsan: shift exponent 4GAlan Modra1-2/+3
2020-08-27PR26462 UBSAN: reloc.c:473 shift exponent 4294967295Alan Modra1-0/+3
2020-06-06Rename PowerPC64 pcrel GOT TLS relocationsAlan Modra1-4/+4
2020-04-22xtensa: fix PR ld/25861Max Filippov1-0/+24
2020-02-26Indent labelsAlan Modra1-1/+1
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov1-0/+4
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. A...Sergey Belyashov1-0/+24
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-25Pass section when available to bfd_octets_per_byteAlan Modra1-16/+13
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers1-7/+25
2019-11-19PR25200, SIGSEGV in _bfd_elf_validate_relocAlan Modra1-22/+5
2019-11-07Remove CR16C supportAlan Modra1-82/+0
2019-09-19bfd_section_* macrosAlan Modra1-2/+1
2019-09-18Constify target name, reloc name, and carsym nameAlan Modra1-1/+1
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-0/+14
2019-05-24PowerPC relocations for prefix insnsAlan Modra1-0/+34
2019-05-23bfd: add support for eBPFJose E. Marchesi1-0/+13
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra1-8/+8
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira1-0/+2
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma...Andre Vieira1-0/+5
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira1-0/+5
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira1-0/+5
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira1-0/+5
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira1-0/+5
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo...Andre Vieira1-0/+5
2019-01-16S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate.John Darrington1-0/+5
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-10-13_bfd_clear_contents bounds checkingAlan Modra1-6/+13
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+24
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson1-3/+9
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton1-7/+41
2018-09-14PR23425, unresolved symbol diagnosticAlan Modra1-1/+12
2018-08-31PowerPC64 higher REL16 relocationsAlan Modra1-0/+12
2018-08-21Pack reloc_howto_structAlan Modra1-59/+51
2018-08-21Delete NEWHOWTO and tidy some uses of reloc_howto_structAlan Modra1-29/+2
2018-08-11Factor out common relocation processingAlan Modra1-244/+108
2018-08-11Deal with relocations which are 3 bytes in sizeJohn Darrington1-4/+21
2018-08-05R_PPC64_REL24_NOTOC supportAlan Modra1-0/+2
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner1-0/+133
2018-06-18Add support for the TLV relocation generated by LLVM for x86_64 MACH-O targets.Mephi1-0/+4
2018-05-18Add support for the Freescale s12z processor.John Darrington1-0/+17
2018-04-25[ARM] Add TLS relocations for FDPIC.Christophe Lyon1-0/+6
2018-04-25[ARM] Add FDPIC relocations definitionsChristophe Lyon1-0/+11
2018-04-17[MicroBlaze] PIC data text relativeMichael Eager1-0/+12
2018-04-16Remove m88k supportAlan Modra1-10/+10
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra1-80/+4
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-0/+46
2018-02-26BFD messagesAlan Modra1-2/+2
2018-02-26unrecognized/unsupported reloc messageAlan Modra1-1/+1
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