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2022-06-27drop XC16x bitsJan Beulich1-4/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-14BFD_RELOC_MIPS_16Alan Modra1-1/+1
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation, since R_MIPS_16 specifies a 16-bit field in a 32-bit word. BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data directives, expects fixups to operate on the whole of a 16-bit word. This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in md_apply_fix for cases where the fixup can be applied at assembly time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object file relocation, and thus .half, .hword, .short and .dc.w must be resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this patch since it isn't used. PR 3243 PR 26542 * reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16. * elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16. * elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16. * elfn32-mips.c (mips_reloc_map): Likewise. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16. (macro_build): Likewise. (mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16. (md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done. ld/ * testsuite/ld-mips-elf/reloc-local-overflow.d, * testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
2022-04-07Add support for COFF secidx relocationsMark Harmstone1-0/+1
bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.
2022-01-04ld: Improve thin archive member error messageH.J. Lu1-1/+1
Improve thin archive member error message with: ld: libbar.a(bar.o): error opening thin archive member: No such file or directory instead of ld: libbar.a: error adding symbols: No such file or directory PR ld/28722 * archive.c (_bfd_get_elt_at_filepos): Add a pointer argument for struct bfd_link_info. Call linker callback when failing to open thin archive member. (_bfd_generic_get_elt_at_index): Pass NULL to _bfd_get_elt_at_filepos. (bfd_generic_openr_next_archived_file): Likewise. * coff-alpha.c (alpha_ecoff_get_elt_at_filepos): Add a pointer argument for struct bfd_link_info and pass it to _bfd_get_elt_at_filepos. (alpha_ecoff_openr_next_archived_file): Pass NULL to _bfd_get_elt_at_filepos. (alpha_ecoff_get_elt_at_index): Likewise. * coff-rs6000.c (_bfd_xcoff_openr_next_archived_file): Likewise. * ecoff.c (ecoff_link_add_archive_symbols): Pass info to backend->get_elt_at_filepos. * elflink.c (elf_link_is_defined_archive_symbol): info to _bfd_get_elt_at_filepos. * libbfd-in.h (_bfd_get_elt_at_filepos): Add a pointer argument for struct bfd_link_info. * libbfd.h: Regenerate. * libecoff.h (ecoff_backend_data): Add a pointer argument for struct bfd_link_info to get_elt_at_filepos. * linker.c (_bfd_generic_link_add_archive_symbols): Pass info to _bfd_get_elt_at_filepos.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra1-0/+1
R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on @notoc cals from non-power10 code in the rare case that using such a construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch instruction if power10 instructions are not enabled at that point. The new relocation tells the linker to not use power10 instructions on any stub emitted for that branch, unless overridden by --power10-stubs=yes. The current linker heuristic of only generating power10 instructions for stubs if power10-only relocations are detected, continues to be used. include/ * elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc. (ppc64_elf_reloc_type_lookup): Handle it. (enum ppc_stub_type): Delete. (enum ppc_stub_main_type, ppc_stub_sub_type): New. (struct ppc_stub_type): New. (struct ppc_stub_hash_entry): Use the above new type. (struct ppc_link_hash_table): Update stub_count. (is_branch_reloc, ppc64_elf_check_relocs), (toc_adjusting_stub_needed): Handle new reloc. (stub_hash_newfunc, select_alt_stub, ppc_merge_stub), (ppc_type_of_stub, plt_stub_size, build_plt_stub), (build_tls_get_addr_head, build_tls_get_addr_tail), (ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs), (ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new reloc. Modify stub handling to suit new scheme. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc. (fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle BFD_RELOC_PPC64_REL24_P9NOTOC. ld/ * testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
2021-10-24LoongArch bfd supportliuzhensong1-0/+43
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> bfd/ * Makefile.am: Add LoongArch. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-loongarch.c: New. * elf-bfd.h: Add LoongArch. * elf.c: Add LoongArch elfcore_grok_xxx. * elfnn-loongarch.c: New. * elfxx-loongarch.c: New. * elfxx-loongarch.h: New. * reloc.c: Add LoongArch BFD RELOC ENUM. * targets.c: Add LoongArch target. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. include/ * elf/common.h: Add NT_LARCH_{CPUCFG,CSR,LSX,LASX}. * elf/loongarch.h: New.
2021-07-08ld: Limit cache size and add --max-cache-size=SIZEH.J. Lu1-0/+3
When link_info.keep_memory is true, linker caches the relocation information and symbol tables of input files in memory. When there are many input files with many relocations, we may run out of memory. Add --max-cache-size=SIZE to set the maximum cache size. bfd/ PR ld/18028 * bfd.c (bfd): Add alloc_size. * elf-bfd.h (_bfd_elf_link_info_read_relocs): New. * elf32-i386.c (elf_i386_check_relocs): Use _bfd_link_keep_memory. Update cache_size. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. * elflink.c (_bfd_elf_link_read_relocs): Renamed to ... (_bfd_elf_link_info_read_relocs): This. Update cache_size. (_bfd_elf_link_read_relocs): New. (_bfd_elf_link_check_relocs): Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (elf_link_add_object_symbols): Likewise. (elf_link_input_bfd): Likewise. (init_reloc_cookie_rels): Likewise. (init_reloc_cookie): Update cache_size. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (link_info_ok): New. (elf_gc_smash_unused_vtentry_relocs): Updated. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (bfd_elf_gc_sections): Use link_info_ok. Pass &link_info_ok to elf_gc_smash_unused_vtentry_relocs. * libbfd-in.h (_bfd_link_keep_memory): New. * linker.c (_bfd_link_keep_memory): New. * opncls.c (bfd_alloc): Update alloc_size. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. include/ PR ld/18028 * bfdlink.h (bfd_link_info): Add cache_size and max_cache_size. ld/ PR ld/18028 * NEWS: Mention --max-cache-size=SIZE. * ld.texi: Document --max-cache-size=SIZE. * ldlex.h (option_values): Add OPTION_MAX_CACHE_SIZE. * ldmain.c: (main): Set link_info.max_cache_size to -1. * lexsup.c (ld_options): Add --max-cache-size=SIZE. (parse_args): Support OPTION_MAX_CACHE_SIZE. * testsuite/ld-bootstrap/bootstrap.exp: Add test for --max-cache-size=-1.
2021-05-22bfd dwarf2 sanity checkingAlan Modra1-2/+1
This patch is aimed at the many places in dwarf2.c that blindly increment a data pointer after calling functions that are meant to read a fixed number of bytes. The problem with that is with damaged dwarf we might increment a data pointer past the end of data, which is UB and complicates (ie. bugs likely) any further use of that data pointer. To fix those problems, I've moved incrementing of the data pointer into the functions that do the reads. _bfd_safe_read_leb128 gets the same treatment for consistency. * libbfd.c (_bfd_safe_read_leb128): Remove length_return parameter. Replace data pointer with pointer to pointer. Increment pointer over bytes read. * libbfd-in.h (_bfd_safe_read_leb128): Update prototype. * elf-attrs.c (_bfd_elf_parse_attributes): Adjust to suit. Be careful not to increment data pointer past end. Remove now redundant pr17512 check. * wasm-module.c (READ_LEB128): Adjust to suit changes to _bfd_safe_read_leb128. * dwarf2.c (read_n_bytes): New inline function, old one renamed to.. (read_blk): ..this. Allocate and return block. Increment bfd_byte** arg. (read_3_bytes): New function. (read_1_byte, read_1_signed_byte, read_2_bytes, read_4_bytes), (read_8_bytes, read_string, read_indirect_string), (read_indirect_line_string, read_alt_indirect_string): Take a byte_byte** arg which is incremented over bytes read. Remove any bytes_read return. Rewrite limit checks to compare lengths rather than pointers. (read_abbrevs, read_attribute_value, read_formatted_entries), (decode_line_info, find_abstract_instance, read_ranges), (read_rnglists, scan_unit_for_symbols, parse_comp_unit), (stash_comp_unit): Adjust to suit. Rewrite limit checks to compare lengths rather than pointers. * libbfd.h: Regenerate.
2021-05-07Regenerate bfd-in2.h and libbfd.hAlan Modra1-1/+1
Commit 0b3e14c90283 edited these by hand. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne1-0/+1
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-04Define bfd_realloc(ptr,0) to return allocated memory, whilst ↵Nick Clifton1-6/+8
bfd_realloc_or_free(ptr,0) frees ptr. * libbfd.c (bfd_malloc): Provide some documenation. Treat a size of 0 as 1. (bfd_realloc): Likewise. (bfd_zmalloc): Likewise. (bfd_realloc_or_free): Provide some documentation. Treat a size of 0 as a request to free. * libbfd-in.h (bfd_realloc): Remove prototype. (bfd_realloc_or_free): Remove prototype. (bfd_zmalloc): Remove prototype. * libbfd.h: Regenerate.
2021-04-22fix string table generation for XCOFF64 .debug sectionCl?ment Chigot1-1/+1
bfd * hash.c (struct bfd_strtab_hash): Remove xcoff field. Add length_field_size field. (_bfd_stringtab_init): Change prototype. Adapt to new length_field_size. (_bfd_xcoff_stringtab_init): Likewise. (_bfd_stringtab_add): Likewise. (_bfd_stringtab_emit): Likewise. * libbfd-in.h (_bfd_xcoff_stringtab_init): Change prototype. * libbfd.h: Regenerate. * xcofflink.c (_bfd_xcoff_bfd_link_hash_table_create): Call _bfd_xcoff_stringtab_init with isxcoff64 value.
2021-04-20Rework the R_NEG support on both gas and ld for the PowerPC AIX targets, in ↵Cl?ment Chigot1-0/+1
order to manage C++ exceptions built with GCC. bfd PR binutils/21700 * reloc.c (BFD_RELOC_PPC_NEG): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (_bfd_xcoff_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. (xcoff_reloc_type_neg): Correctly substract addend. * coff64-rs6000.c (xcoff64_howto_table): Add R_NEG_32 howto. (xcoff64_rtype2howto): Add handler for R_NEG_32. (xcoff64_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. * xcofflink.c (xcoff_need_ldrel_p): Check output section for R_POS-like relocations. New argument added. (xcoff_mark): Adapt to new xcoff_need_ldrel_p argument. (xcoff_link_input_bfd): Likewise. gas * config/tc-ppc.c (ppc_get_csect_to_adjust): New function. (ppc_fix_adjustable): Manage fx_subsy part. (tc_gen_reloc): Create second relocation when both fx_addsy and fx_subsy are provided. * config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define. (MAX_RELOC_EXPANSION): Likewise. (TC_FORCE_RELOCATION_SUB_SAME): Likewise (UNDEFINED_DIFFERENCE_OK): Likewise * testsuite/gas/all/gas.exp: Skip difference between two undefined symbols test. ld * testsuite/ld-powerpc/aix52.exp: Add new test. * testsuite/ld-powerpc/aix-neg-reloc-32.d: New test. * testsuite/ld-powerpc/aix-neg-reloc-64.d: New test. * testsuite/ld-powerpc/aix-neg-reloc.ex: New test. * testsuite/ld-powerpc/aix-neg-reloc.s: New test.
2021-03-31Use bool in bfdAlan Modra1-118/+118
* sysdep.h: POISON_BFD_BOOLEAN: Define. * aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h, * aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c, * bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c, * coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c, * coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c, * coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c, * coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c, * coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c, * cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c, * cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c, * cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c, * cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c, * cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c, * cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c, * cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c, * cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c, * cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c, * cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c, * cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c, * cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c, * cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c, * cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c, * cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c, * cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c, * cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c, * cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c, * cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c, * cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c, * dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c, * elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c, * elf-nacl.h, * elf-properties.c, * elf-s390-common.c, * elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h, * elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c, * elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c, * elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c, * elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c, * elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c, * elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h, * elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h, * elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h, * elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c, * elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c, * elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c, * elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h, * elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h, * elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h, * elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h, * elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h, * format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c, * i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h, * libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h, * libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c, * mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h, * merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c, * pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c, * pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c, * pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c, * peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c, * reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c, * som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c, * verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h, * wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c, * xsym.h: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate.
2021-03-12aix: implement TLS relocation for gas and ldClément Chigot1-0/+10
Add support for TLS in XCOFF. Amongst the things done by this commit: - Update XCOFF auxialiary header to match new version and allow TLS sections. - Add TLS sections (.tdata and .tbss) support in gas and ld. - Add support for the TLS relocations in gas and ld. Two different types BFD_RELOC are created for PPC and PPC64 as the size is a pointer, thus distinct in 32 or 64bit. The addresses given by ld to .tdata and .tbss is a bit special. In XCOFF, these addresses are actually offsets from the TLS pointer computed at runtime. AIX assembly and linker does the same. In top of that, the .tdata must be before .data (this is mandatory for AIX loader). Thus, the aix ld script is recomputing "." before .data to restore its original value. There might be a simpler way, but this one is working. Optimisation linked to TLS relocations aren't yet implemented. bfd/ * reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE, BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD, BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE, BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M, BFD_RELOC_PPC64_TLS_ML): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_tls for TLS relocations. (xcoff_howto_table): Implement TLS relocations. (_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations. (xcoff_reloc_type_tls): New function. * coff64-rs6000.c (xcoff_calculate_relocation): Likewise. (xcoff_howto_table): Likewise. (_bfd_xcoff_reloc_type_lookup): Likewise. * coffcode.h (sec_to_styp_flags): Handle TLS sections. (styp_to_sec_flags): Likewise. (coff_compute_section_file_positions): Avoid file offset optimisation for .data when the previous section is .tdata. (coff_write_object_contents): Handle TLS sections. * coffswap.h (coff_swap_aouthdr_out): Add support for new fields in aouthdr. * libxcoff.h (xcoff_reloc_type_tls): Add prototype. * xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL. (xcoff_need_ldrel_p): Add cases for TLS relocations. (xcoff_create_ldrel): Add l_symndx for TLS sections. gas/ * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section, (ppc_xcoff_bss_section, ppc_xcoff_tdata_section, (ppc_xcoff_tbss_section): New variables. (ppc_text_subsegment, ppc_text_csects, ppc_data_subgments, (ppc_data_csects): Removed. (ppc_xcoff_section_is_initialized, ppc_init_xcoff_section, ppc_xcoff_parse_cons): New functions. (md_being): Initialize XCOFF sections. (ppc_xcoff_suffix): Add support for TLS relocations (fixup_size, md_apply_fix): Add support for new BFD_RELOC. (ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS to .bss section. Handle new XCOFF section variables. (ppc_comm): Likewise. (ppc_toc): Likewise. (ppc_symbol_new_hook): Likewise. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Add tbss support. * config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define. (ppc_xcoff_parse_cons): Add prototype. (struct ppc_xcoff_section): New structure. ld/ * emultempl/aix.em: Ensure .tdata section is removed if empty, even with -r flag. * scripttempl/aix.sc: Handle TLS sections. * testsuite/ld-powerpc/aix52.exp: Add new tests. * testsuite/ld-powerpc/aix-tls-reloc-32.d: New test. * testsuite/ld-powerpc/aix-tls-reloc-64.d: New test. * testsuite/ld-powerpc/aix-tls-reloc.ex: New test. * testsuite/ld-powerpc/aix-tls-reloc.s: New test. * testsuite/ld-powerpc/aix-tls-section-32.d: New test. * testsuite/ld-powerpc/aix-tls-section-64.d: New test. * testsuite/ld-powerpc/aix-tls-section.ex: New test. * testsuite/ld-powerpc/aix-tls-section.s: New test. include/ * coff/internal.h (struct internal_aouthdr): Add new fields. * coff/rs6000.h (AOUTHDRÃ): Add new fields. * coff/rs6k64.h (struct external_filehdr): Likewise. * coff/xcoff.h (_TDATA), _TBSS): New defines (RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA, RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY, RS6K_AOUTHDR_FORK_COR): New defines. (XMC_TU): Removed. (XMC_UL): New define.
2021-03-12aix: implement R_TOCU and R_TOCL relocationsClément Chigot1-0/+2
Implement support for largetoc on XCOFF. R_TOCU and R_TOCL are referenced by the new BFD defines: BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. A new toc storage class is added XMC_TE. In order to correctly handle R_TOCU, the logic behind xcoff_reloc_type_toc is changed to compute the whole TOC offset instead of just the difference between the "link" offset and the "assembly" offset. In gas, add a function to transform addis format used by AIX "addis RT, D(RA)" into the ELF format "addis RT, RA, SI". bfd/ * reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_toc for R_TOCU and R_TOCL. (xcoff_howto_table): Remove src_mask for TOC relocations. Add R_TOCU and R_TOCL howtos. (_bfd_xcoff_reloc_type_lookup): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (xcoff_reloc_type_toc): Compute the whole offset. Implement R_TOCU and R_TOCL. * coff64-rs6000.c (xcoff64_calculate_relocation): Likewise. (xcoff64_howto_table): Likewise. (xcoff64_reloc_type_lookup): Likewise. gas/ * config/tc-ppc.c (ppc_xcoff_suffix): New function. (MAP, MAP32, MAP64): New macros for XCOFF. (ppc_xcoff_fixup_addis): New function. (ppc_is_toc_sym): Handle XMC_TE. (fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (md_assemble): Call ppc_xcoff_fixup_addis for XCOFF. (ppc_change_csect): Handle XMC_TE. (ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE storage class. (ppc_symbol_new_hook): Handle XMC_TE. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Likewise. (md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. ld/ * scripttempl/aix.sc: Add .te to .data section. * testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+. Add aix-largetoc-1 test. * testsuite/ld-powerpc/aix-largetoc-1-32.d: New test. * testsuite/ld-powerpc/aix-largetoc-1-64.d: New test. * testsuite/ld-powerpc/aix-largetoc-1.ex: New test. * testsuite/ld-powerpc/aix-largetoc-1.s: New test.
2021-03-05elf/x86-64: Subtract __ImageBase for R_AMD64_IMAGEBASEH.J. Lu1-0/+2
When linking Windows x86-64 relocatable object files to generate x86-64 ELF executable, we need to subtract __ImageBase, aka __executable_start, for R_AMD64_IMAGEBASE relocation: 1. Add link_info to struct output_elf_obj_tdata to store linker info and _bfd_get_link_info() to retrieve it. 2. Add ldelf_set_output_arch to set up link_info. 3. Add pex64_link_add_symbols to create an indirect reference to __executable_start for __ImageBase to support R_AMD64_IMAGEBASE relocation when adding symbols from Windows x86-64 relocatable object files to generate x86-64 ELF executable. 4. Also subtract __ImageBase for R_AMD64_IMAGEBASE when generating x86-64 ELF executable. bfd/ PR ld/27425 PR ld/27432 * bfd.c (_bfd_get_link_info): New function. * elf-bfd.h (output_elf_obj_tdata): Add link_info. (elf_link_info): New. * libbfd-in.h (_bfd_get_link_info): New prototype. * coff-x86_64.c (coff_amd64_reloc): Also subtract __ImageBase for R_AMD64_IMAGEBASE when generating x86-64 ELF executable. * pe-x86_64.c: Include "coff/internal.h" and "libcoff.h". (pex64_link_add_symbols): New function. (coff_bfd_link_add_symbols): New macro. * libbfd.h: Regenerated. ld/ PR ld/27425 PR ld/27432 * ldelf.c (ldelf_set_output_arch): New function. * ldelf.h (ldelf_set_output_arch): New prototype. * emultempl/elf.em (LDEMUL_SET_OUTPUT_ARCH): Default to ldelf_set_output_arch. * ld-x86-64/pe-x86-64-1.od: Expect __executable_start. * testsuite/ld-x86-64/pe-x86-64-2.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-3.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-4.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-5.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-5.rd: Likewise. * testsuite/ld-x86-64/pe-x86-64-6.obj.bz2: New file. * testsuite/ld-x86-64/pe-x86-64-6.od: Likewise. * testsuite/ld-x86-64/pe-x86-64.exp: Run ld/27425 test.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-18Constify more arraysAlan Modra1-2/+2
bfd/ * coff-z80.c (bfd_howto_type): Make typedef const. * elf32-z80.c (bfd_howto_type): Likewise. * elf32-m32c.c (EncodingTable): Likewise. * elf32-csky.c (csky_arch_for_merge): Likewise. (csky_archs): Use typedef. * elf32-m68hc11.c (m68hc11_direct_relax_table): Make const. (find_relaxable_insn, m68hc11_elf_relax_section): Adjust to suit. * elf32-ppc.c (ppc_alt_plt): Make const. * elf32-rl78.c (relax_addr16): Likewise. * targets.c (_bfd_associated_vector): Likewise. (bfd_target_vector, bfd_associated_vector): Likewise. * libbfd-in.h (bfd_target_vector, bfd_associated_vector): Likewise. * libbfd.h: Regenerate. include/ * opcode/arc-attrs.h (CONFLICT_LIST): Make const.
2020-09-09Re: MSP430: Support relocations for subtract expressions in .uleb128 directivesAlan Modra1-1/+1
Put the prototype where it won't disappear on the next regen of libbfd.h. * libbfd-in.h (_bfd_write_unsigned_leb128): Declare. * libbfd.h: Regenerate.
2020-09-08MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz1-0/+4
Link-time relaxations of branches are common for MSP430, given that GCC can generate pessimal branch instructions, and the -mcode-region=either/-mdata-region=either options to shuffle sections can further change the type of branch instruction required. These relaxations can result in invalid code when .uleb128 directives, used in the .gcc_except_table section, are used to calculate the distance between two labels. A value for the .uleb128 directive is calculated at assembly-time, and can't be updated at link-time, even if relaxation causes the distance between the labels to change. This patch adds relocations for subtract expressions in .uleb128 directives, to allow the linker to re-calculate the value of these expressions after relaxation has been performed. bfd/ChangeLog: * bfd-in2.h (bfd_reloc_code_real): Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128. * elf32-msp430.c (msp430_elf_ignore_reloc): New. (elf_msp430_howto_table): Add R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. (msp430_reloc_map): Add R_MSP430_GNU_{SET,SUB}_ULEB128. (msp430x_reloc_map): Add R_MSP430X_GNU_{SET,SUB}_ULEB128. (write_uleb128): New. (msp430_final_link_relocate): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. * libbfd.c (_bfd_write_unsigned_leb128): New. * libbfd.h (_bfd_write_unsigned_leb128): New prototype. Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128. * reloc.c: Document BFD_RELOC_MSP430_{SET,SUB}_ULEB128. binutils/ChangeLog: * readelf.c (target_specific_reloc_handling): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128. gas/ChangeLog: * config/tc-msp430.c (msp430_insert_uleb128_fixes): New. (msp430_md_end): Call msp430_insert_uleb128_fixes. include/ChangeLog: * elf/msp430.h (elf_msp430_reloc_type): Add R_MSP430_GNU_{SET,SUB}_ULEB128. (elf_msp430x_reloc_type): Add R_MSP430X_GNU_{SET,SUB}_ULEB128. ld/ChangeLog: * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests. * testsuite/ld-msp430-elf/uleb128.s: New test. * testsuite/ld-msp430-elf/uleb128_430.d: New test. * testsuite/ld-msp430-elf/uleb128_430x.d: New test.
2020-06-06Rename PowerPC64 pcrel GOT TLS relocationsAlan Modra1-4/+4
These relocations should have had REL in their names, to reflect the fact that they are pc-relative. Fix that now by adding _PCREL. I've added some back-compatibility code to support anyone using .reloc with the old relocations. include/ * elf/ppc64.h (elf_ppc64_reloc_type): Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. bfd/ * reloc.c: Rename BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34, BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34, BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34, BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34. * elf64-ppc.c: Update throughout for reloc renaming. (ppc64_elf_reloc_name_lookup): Handle old reloc names. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c: Update throughout for reloc renaming. elfcpp/ * powerpc.h: Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. gold/ * powerpc.cc: Update throughout for reloc renaming.
2020-04-22xtensa: fix PR ld/25861Max Filippov1-0/+6
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences (subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32} for negative differences (subtracted symbol follows diminished symbol). Don't generate XTENSA_DIFF relocations in the assembler, generate XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position. Handle XTENSA_DIFF in BFD for compatibility with old object files. Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value as unsigned. 2020-04-22 Max Filippov <jcmvbkbc@gmail.com> bfd/ * bfd-in2.h: Regenerated. * elf32-xtensa.c (elf_howto_table): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. (elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc) (relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. * libbfd.h (bfd_reloc_code_real_names): Add names for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. * reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. binutils/ * readelf.c (is_none_reloc): Recognize BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. gas/ * config/tc-xtensa.c (md_apply_fix): Replace BFD_RELOC_XTENSA_DIFF{8,16,32} generation with BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32} generation. * testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16 with BFD_RELOC_XTENSA_PDIFF16 in the expected output. include/ * elf/xtensa.h (elf_xtensa_reloc_type): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. ld/ * testsuite/ld-xtensa/relax-loc.d: New test definition. * testsuite/ld-xtensa/relax-loc.s: New test source. * testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-03-26Revert earlier delta adding bfd_coff_get_internal_extra_pe_aouthdr() function.Nick Clifton1-5/+0
* cofflink.c (bfd_coff_get_internal_extra_pe_aouthdr): Delete. * libbfd-in.h (bfd_coff_get_internal_extra_pe_aouthdr): Remove prototype. * libbfd.h: Regenerate.
2020-03-25Add a new function to the BFD library to allow users access to the COFF ↵Nick Clifton1-0/+5
internal_extra_pe_outhdr structure. * cofflink.c (bfd_coff_get_internal_extra_pe_aouthdr): New function. * libbfd-in.h (bfd_coff_get_internal_extra_pe_aouthdr): Prototype. * libbfd.h: Regenerate.
2020-03-24bfd: Add a bfd_boolean argument to bfd_get_symbol_version_stringH.J. Lu1-1/+1
We can't call _bfd_elf_get_symbol_version_name from nm.c since it isn't available for all target configurations. This patch add a bfd_boolean argument to bfd_get_symbol_version_string instead. bfd/ PR binutils/25708 * elf-bfd.h (_bfd_elf_get_symbol_version_name): Renamed to ... (_bfd_elf_get_symbol_version_string): This. * elf.c (_bfd_elf_get_symbol_version_name): Renamed to ... (_bfd_elf_get_symbol_version_string): This. (bfd_elf_print_symbol): Pass TRUE to _bfd_elf_get_symbol_version_string. * libbfd-in.h (_bfd_nosymbols_get_symbol_version_string): Add a bfd_boolean argument. * syms.c (_bfd_nosymbols_get_symbol_version_string): Likewise. * targets.c (_bfd_get_symbol_version_string): Likewise. (bfd_get_symbol_version_string): Likewise. * bfd-in2.h: Regenerated. binutils/ PR binutils/25708 * nm.c (print_symname): Replace _bfd_elf_get_symbol_version_name with bfd_get_symbol_version_string. (print_symbo): Pass TRUE to bfd_get_symbol_version_string. * objdump.c (objdump_print_symname): Likewise.
2020-03-02bfd_cleanup for object_pAlan Modra1-4/+5
The object_p (and archive_p, core_file_p) functions are not supposed to have any target specific malloc'd memory attached to the bfd on their return. This should be obvious on a failure return, but it's also true for a successful return. The reason is that even though the object_p recognises the file, that particular target may not be used and thus the bfd won't be closed calling close_and_cleanup for the target that allocated the memory. It turns out that the object_p bfd_target* return value isn't needed. In all cases except ld/plugin.c the target is abfd->xvec and with ld/plugin.c the target isn't used. So this patch returns a cleanup function from object_p instead, called in bfd_check_format_matches to tidy the bfd before trying a different target match. The only cleanup that does anything at this stage is the alpha-vms one. bfd/ * targets.c (bfd_cleanup): New typedef. (struct bfd <_bfd_check_format>): Return a bfd_cleanup. * libbfd-in.h (_bfd_no_cleanup): Define. * format.c (bfd_reinit): Add cleanup parameter, call it. (bfd_check_format_matches): Set cleanup from _bfd_check_format call and pass to bfd_reinit. Delete temp, use abfd->xvec instead. * aout-target.h (callback, object_p): Return bfd_cleanup. * aout-tic30.c (tic30_aout_callback, tic30_aout_object_p): Likewise. * archive.c (bfd_generic_archive_p): Likewise. * binary.c (binary_object_p): Likewise. * coff-alpha.c (alpha_ecoff_object_p): Likewise. * coff-ia64.c (ia64coff_object_p): Likewise. * coff-rs6000.c (_bfd_xcoff_archive_p, rs6000coff_core_p): Likewise. * coff-sh.c (coff_small_object_p): Likewise. * coff-stgo32.c (go32_check_format): Likewise. * coff64-rs6000.c (xcoff64_archive_p, rs6000coff_core_p), (xcoff64_core_p): Likewise. * coffgen.c (coff_real_object_p, coff_object_p): Likewise. * elf-bfd.h (bfd_elf32_object_p, bfd_elf32_core_file_p), (bfd_elf64_object_p, bfd_elf64_core_file_p): Likewise. * elfcode.h (elf_object_p): Likewise. * elfcore.h (elf_core_file_p): Likewise. * i386msdos.c (msdos_object_p): Likewise. * ihex.c (ihex_object_p): Likewise. * libaout.h (some_aout_object_p): Likewise. * libbfd-in.h (bfd_generic_archive_p, _bfd_dummy_target), (_bfd_vms_lib_alpha_archive_p, _bfd_vms_lib_ia64_archive_p): Likewise. * libbfd.c (_bfd_dummy_target): Likewise. * libcoff-in.h (coff_object_p): Likewise. * mach-o-aarch64.c (bfd_mach_o_arm64_object_p), (bfd_mach_o_arm64_core_p): Likewise. * mach-o-arm.c (bfd_mach_o_arm_object_p), (bfd_mach_o_arm_core_p): Likewise. * mach-o-i386.c (bfd_mach_o_i386_object_p), (bfd_mach_o_i386_core_p): Likewise. * mach-o-x86-64.c (bfd_mach_o_x86_64_object_p), (bfd_mach_o_x86_64_core_p): Likewise. * mach-o.c (bfd_mach_o_header_p, bfd_mach_o_gen_object_p), (bfd_mach_o_gen_core_p, bfd_mach_o_fat_archive_p): Likewise. * mach-o.h (bfd_mach_o_object_p, bfd_mach_o_core_p), (bfd_mach_o_fat_archive_p, bfd_mach_o_header_p): Likewise. * mmo.c (mmo_object_p): Likewise. * pef.c (bfd_pef_object_p, bfd_pef_xlib_object_p): Likewise. * peicode.h (coff_real_object_p, pe_ILF_object_p), (pe_bfd_object_p): Likewise. * plugin.c (ld_plugin_object_p, bfd_plugin_object_p): Likewise. * ppcboot.c (ppcboot_object_p): Likewise. * rs6000-core.c (rs6000coff_core_p): Likewise. * som.c (som_object_setup, som_object_p): Likewise. * srec.c (srec_object_p, symbolsrec_object_p): Likewise. * tekhex.c (tekhex_object_p): Likewise. * vms-alpha.c (alpha_vms_object_p): Likewise. * vms-lib.c (_bfd_vms_lib_archive_p, _bfd_vms_lib_alpha_archive_p), (_bfd_vms_lib_ia64_archive_p, _bfd_vms_lib_txt_archive_p): Likewise. * wasm-module.c (wasm_object_p): Likewise. * xsym.c (bfd_sym_object_p): Likewise. * xsym.h (bfd_sym_object_p): Likewise. * aoutx.h (some_aout_object_p): Likewise, and callback parameter return type. * pdp11.c (some_aout_object_p): Likewise. * plugin.c (register_ld_plugin_object_p): Update object_p parameter type. * plugin.h (register_ld_plugin_object_p): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate. ld/ * plugin.c (plugin_object_p): Return a bfd_cleanup. (plugin_cleanup): New function.
2020-02-19file size check in _bfd_alloc_and_readAlan Modra1-2/+28
* coffgen.c (_bfd_coff_get_external_symbols): Remove file size check. * elf.c (bfd_elf_get_str_section): Likewise. (_bfd_elf_slurp_version_tables): Likewise. * libbfd-in.h (_bfd_constant_p): Define. (_bfd_alloc_and_read, _bfd_malloc_and_read): Check read size against file size before allocating memory. * libbfd.h: Regenerate.
2020-02-19_bfd_alloc_and_readAlan Modra1-0/+26
This patch provides two new inline functions that are then used in places that allocate memory, read from file, and then deallocate on a read failure. * libbfd-in.h (_bfd_alloc_and_read, _bfd_malloc_and_read): New. * aoutx.h (aout_get_external_symbols): Replace calls to bfd_[m]alloc and bfd_bread with call to _bfd_[m]alloc_and_read. (slurp_reloc_table): Likewise. * archive.c (do_slurp_bsd_armap): Likewise. (do_slurp_coff_armap): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * coff-rs6000.c (_bfd_xcoff_slurp_armap): Likewise. * coff64-rs6000.c (xcoff64_slurp_armap): Likewise. * coffcode.h (coff_set_arch_mach_hook, buy_and_read): Likewise. * coffgen.c (coff_real_object_p, coff_object_p, build_debug_section), (_bfd_coff_get_external_symbols): Likewise. * ecoff.c (ecoff_slurp_symbolic_header), (_bfd_ecoff_slurp_symbolic_info, ecoff_slurp_reloc_table), (_bfd_ecoff_slurp_armap, ecoff_link_add_object_symbols, READ), (ecoff_indirect_link_order): Likewise. * elf.c (bfd_elf_get_str_section, setup_group, elf_read_notes), (_bfd_elf_slurp_version_tables): Likewise. * elf32-m32c.c (m32c_elf_relax_section): Likewise. * elf32-rl78.c (rl78_elf_relax_section): Likewise. * elf32-rx.c (elf32_rx_relax_section): Likewise. * elf64-alpha.c (READ): Likewise. * elf64-mips.c (mips_elf64_slurp_one_reloc_table): Likewise. * elf64-sparc.c (elf64_sparc_slurp_one_reloc_table): Likewise. * elfcode.h (elf_slurp_symbol_table), (elf_slurp_reloc_table_from_section): Likewise. * elflink.c (elf_link_add_object_symbols), (elf_link_check_versioned_symbol): Likewise. * elfxx-mips.c (READ): Likewise. * i386lynx.c (slurp_reloc_table): Likewise. * lynx-core.c (lynx_core_file_p): Likewise. * mach-o.c (bfd_mach_o_canonicalize_relocs), (bfd_mach_o_read_symtab_strtab, bfd_mach_o_alloc_and_read), (bfd_mach_o_read_prebound_dylib, bfd_mach_o_read_dyld_content * pdp11.c (aout_get_external_symbols, slurp_reloc_table * pef.c (bfd_pef_print_loader_section, bfd_pef_scan_start_address), (bfd_pef_parse_symbols): Likewise. * peicode.h (pe_ILF_object_p, pe_bfd_object_p * som.c (setup_sections, som_slurp_string_table), (som_slurp_reloc_table, som_bfd_count_ar_symbols), (som_bfd_fill_in_ar_symbols): Likewise. * vms-alpha.c (module_find_nearest_line, evax_bfd_print_dst), (evax_bfd_print_image): Likewise. * vms-lib.c (_bfd_vms_lib_archive_p): Likewise. * wasm-module.c (wasm_scan): Likewise. * xcofflink.c (xcoff_link_add_symbols): Likewise. * xsym.c (bfd_sym_read_name_table), (bfd_sym_print_type_information_table_entry): Likewise. * libbfd.h: Regenerate.
2020-02-19_bfd_mul_overflowAlan Modra1-10/+8
This patch removes the bfd_alloc2 series of memory allocation functions, replacing them with __builtin_mul_overflow followed by bfd_alloc. Why do that? Well, a followup patch will implement _bfd_alloc_and_read and I don't want to implement alloc2 variants as well. * coffcode.h (buy_and_read, coff_slurp_line_table), (coff_slurp_symbol_table, coff_slurp_reloc_table): Replace bfd_[z][m]alloc2 calls with _bfd_mul_overflow followed by the corresponding bfd_alloc call. Adjust variables to suit. * coffgen.c (_bfd_coff_get_external_symbols): Likewise. * ecoff.c (_bfd_ecoff_slurp_symbolic_info), (_bfd_ecoff_slurp_symbol_table, READ): Likewise. * elf.c (bfd_elf_get_elf_syms, setup_group, bfd_section_from_shdr), (swap_out_syms, _bfd_elf_slurp_version_tables): Likewise. * elf32-m32c.c (m32c_elf_relax_section): Likewise. * elf32-rl78.c (rl78_elf_relax_section): Likewise. * elf32-rx.c (elf32_rx_relax_section): Likewise. * elf64-alpha.c (READ): Likewise. * elfcode.h (elf_object_p, elf_write_relocs, elf_write_shdrs_and_ehdr), (elf_slurp_symbol_table, elf_slurp_reloc_table), (bfd_from_remote_memory): Likewise. * elfcore.h (core_find_build_id): Likewise. * elfxx-mips.c (READ): Likewise. * mach-o.c (bfd_mach_o_mangle_sections), (bfd_mach_o_read_symtab_symbols, bfd_mach_o_read_thread), (bfd_mach_o_read_dysymtab, bfd_mach_o_flatten_sections), (bfd_mach_o_scan, bfd_mach_o_fat_archive_p): Likewise. * som.c (setup_sections, som_prep_for_fixups) (som_build_and_write_symbol_table, som_slurp_symbol_table), (som_slurp_reloc_table, som_bfd_count_ar_symbols), (som_bfd_fill_in_ar_symbols, som_slurp_armap), (som_bfd_ar_write_symbol_stuff): Likewise. * vms-alpha.c (vector_grow1): Likewise. * vms-lib.c (vms_add_index): Likewise. * wasm-module.c (wasm_scan_name_function_section): Likewise. * libbfd.c (bfd_malloc2, bfd_realloc2, bfd_zmalloc2): Delete. * opncls.c (bfd_alloc2, bfd_zalloc2): Delete. * libbfd-in.h (bfd_malloc2, bfd_realloc2, bfd_zmalloc2), (bfd_alloc2, bfd_zalloc2): Delete. (_bfd_mul_overflow): Define. * libbfd.h: Regenerate.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov1-0/+1
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov1-0/+6
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-27PR23652, Use symbols from debug bfd for _bfd_elf_find_function properlyAlan Modra1-1/+1
There were a number of problems with the previous patch. Firstly, _bfd_dwarf2_stash_syms didn't do anything when the original file had dynamic symbols, and secondly, info found by the symbol search didn't make it out of _bfd_elf_find_nearest_line except in the case of DWARF functions without external linkage. PR 23652 * dwarf2.c (_bfd_dwarf2_stash_syms): Break out of loop on finding matching section. (_bfd_dwarf2_find_nearest_line): Return an int, with value 2 when returning info from the symbol table. Do the _bfd_elf_find_function search also when !found. Call _bfd_dwarf2_stash_syms regardless of symbols. * elf64-alpha.c (elf64_alpha_find_nearest_line): Accept dwarf2 result of 1 only. * elfxx-mips.c (_bfd_mips_elf_find_nearest_line): Likewise. * libbfd-in.h (_bfd_dwarf2_find_nearest_line): Update prototype. * libbfd.h: Regenerate.
2019-11-07Remove CR16C supportAlan Modra1-40/+0
I think it is past time to remove CR16C support. CR16C was added in 2004, and only for ld. gas and binutils support is lacking, and there have been no commits to bfd/elf32-cr16c.c other than warning fixes or global maintainers making changes to all targets. I see no maintainer listed for CR16C, and no commits from anyone at NSC supporting the target. Furthermore, at the time the CR16 support was added in 2007, config.sub was changed upstream to no longer recognise cr16c as a valid cpu. That means the CR16C ld support is only available as a secondary target by configuring with, for example, --enable-targets=all or --enable-targets=cr16c-unknown-elf. No testing of the CR16C target is possible. include/ * elf/cr16c.h: Delete. bfd/ * cpu-cr16c.c: Delete. * elf32-cr16c.c: Delete. * Makefile.am, * archures.c, * config.bfd, * configure.ac, * reloc.c, * targets.c: Remove cr16c support. * Makefile.in, * bfd-in2.h, * configure, * libbfd.h, * po/SRC-POTFILES.in: Regenerate. ld/ * emulparams/elf32cr16c.sh: Delete. * scripttempl/elf32cr16c.sc: Delete. * Makefile.am, * configure.tgt: Remove cr16c support. * NEWS: Mention removal of cr16c. * Makefile.in, * po/BLD-POTFILES.in: Regenerate.
2019-09-11Tidy ld/ldmisc.cAlan Modra1-0/+2
The idea here is to not use elf-bfd.h and coff-bfd.h in generic linker code. bfd/ * targets.c (struct bfd_target): Add _bfd_group_name. (BFD_JUMP_TABLE): Likewise. * coffgen.c (bfd_coff_group_name): New function. * elf.c (bfd_elf_group_name): New function. * linker.c (_bfd_nolink_bfd_group_name): New function. * section.c (bfd_generic_group_name): New function. * elf-bfd.h (bfd_elf_group_name): Declare. * libbfd-in.h (_bfd_nolink_bfd_group_name): Declare. * libcoff-in.h (bfd_coff_group_name): Declare. * aout-target.h (MY_bfd_group_name): Define. * aout-tic30.c (MY_bfd_group_name): Define. * bfd.c (bfd_group_name): Define. * binary.c (binary_bfd_group_name): Define. * coff-alpha.c (_bfd_ecoff_bfd_group_name): Define. * coff-mips.c (_bfd_ecoff_bfd_group_name): Define. * coff-rs6000.c (_bfd_xcoff_bfd_group_name): Define. * coffcode.h (coff_bfd_group_name): Define. * elfxx-target.h (bfd_elfNN_bfd_group_name): Define. * i386msdos.c (msdos_bfd_group_name): Define. * ihex.c (ihex_bfd_group_name): Define. * mach-o-target.c (bfd_mach_o_bfd_group_name): Define. * mmo.c (mmo_bfd_group_name): Define. * pef.c (bfd_pef_bfd_group_name): Define. * plugin.c (bfd_plugin_bfd_group_name): Define. * ppcboot.c (ppcboot_bfd_group_name): Define. * som.c (som_bfd_group_name): Define. * srec.c (srec_bfd_group_name): Define. * tekhex.c (tekhex_bfd_group_name): Define. * verilog.c (verilog_bfd_group_name): Define. * vms-alpha.c (vms_bfd_group_name, alpha_vms_bfd_group_name): Define. * xsym.c (bfd_sym_bfd_group_name): Define. * coff64-rs6000.c (rs6000_xcoff64_vec): Init new field. (rs6000_xcoff64_aix_vec): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate. ld/ * ldmisc.c: Don't #include elf-bfd.h or coff-bfd.h. (vfinfo): Use bfd_group_name.
2019-09-05PR24955, libbfd terminating program on out of memoryAlan Modra1-0/+9
This patch fixes the worst of the cases where libbfd might terminate a program due to calling xstrdup or xmalloc. I've also fixed some error paths that didn't clean up properly. PR 24955 * libbfd-in.h (bfd_strdup): New inline function. * archive.c (_bfd_get_elt_at_filepos): Use bfd_strdup. Close bfd on error. * elfcode.h (_bfd_elf_bfd_from_remote_memory): Use bfd_strdup. * opncls.c (bfd_fopen): Use bfd_strdup. Close fd and stream on error. (bfd_openstreamr): Use bfd_strdup. (bfd_openr_iovec, bfd_openw, bfd_create): Likewise. * plugin.c (try_load_plugin): Use bfd_malloc. * libbfd.h: Regenerate.
2019-08-14Remove _bfd_dwarf2_find_nearest_line addr_size parameterAlan Modra1-1/+1
This parameter might appear to be used to set up offset_size, but since git commit 024b2372f5 offset_size is either set from the debug_info data or is set to 4. * dwarf2.c (_bfd_dwarf2_find_nearest_line): Remove addr_size parameter. * libbfd-in.h (_bfd_dwarf2_find_nearest_line): Update prototype. * coffgen.c (coff_find_nearest_line_with_names): Adjust _bfd_dwarf2_find_nearest_line calls. * elf.c (_bfd_elf_find_nearest_line, _bfd_elf_find_line): Likewise. * elf32-arm.c (elf32_arm_find_nearest_line): Likewise. * elf64-alpha.c (elf64_alpha_find_nearest_line): Likewise. * elfnn-aarch64.c (elfNN_aarch64_find_nearest_line): Likewise. * elfxx-mips.c (_bfd_mips_elf_find_nearest_line): Likewise. * mach-o.c (bfd_mach_o_find_nearest_line): Likewise. * libbfd.h: Regenerate.
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-0/+7
This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2019-05-24PowerPC relocations for prefix insnsAlan Modra1-0/+17
include/ * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), (R_PPC64_D28, R_PPC64_PCREL28): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO), (BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30), (BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34), (BFD_RELOC_PPC64_PLT_PCREL34), (BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34), (BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34), (BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34), (BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34), (BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums. * elf64-ppc.c (PNOP): Define. (ppc64_elf_howto_raw): Add reloc howtos for new relocations. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers. (ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34 relocs. (ppc64_elf_prefix_reloc): New function. (struct ppc_link_hash_table): Add notoc_plt. (is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC. (is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle possible need for dynamic relocs on non-pcrel powerxx relocs. (dec_dynrel_count): Handle non-pcrel powerxx relocs. (ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_relocate_section): Handle new powerxx relocs. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel, @plt@pcrel, @higher34, @highera34, @highest34, and @highesta34. (fixup_size): Handle new powerxx relocs. (md_assemble): Warn for @pcrel on non-prefix insns. Accept @l, @h and @ha on prefix insns, and infer reloc without any @ suffix. Translate powerxx relocs to suit DQ and DS field instructions. Include operand tests as well as opcode test to translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA. (ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs. (md_apply_fix): Handle new powerxx relocs. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34, BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34, BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28. * testsuite/gas/ppc/prefix-reloc.d, * testsuite/gas/ppc/prefix-reloc.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-23bfd: add support for eBPFJose E. Marchesi1-0/+5
This patch adds support to BFD for elf64-bpf, in both little-endian and big-endian variants. bfd/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac: Add bpf_elf64_le_vec and bpf_elf64_be_vec. * configure: Regenerated. * Makefile.am (ALL_MACHINES): Add cpu-bpf.lo. (ALL_MACHINES_CFILES): Add cpu-bpf.c. (BFD64_BACKENDS): Add elf64-bpf.lo. (BFD64_BACKENDS_CFILES): Add elf64-bpf.c. * Makefile.in (SOURCE_HFILES): Regenerate. * config.bfd (targ_cpu): Handle bpf-*-* targets. * cpu-bpf.c: New file. * elf64-bpf.c: Likewise. * targets.c (_bfd_target_vector): Add bpf_elf64_be_vec and bpf_elf64_le_vec. * archures.c: Define architecture bfd_arch_bpf and machine bfd_arch_bpf. * reloc.c: Define BFD relocations used by the BPF target. * bfd-in2.h: Regenerated. * libbfd.h: Likewise.
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra1-4/+4
GOT and PLT relocs shouldn't have their symbols replaced with a section symbol plus added. Nor should the HIGHA TLS relocations, which failed to be caught by the range test in ppc_fix_adjustable. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA), (BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry. gas/ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT relocs, and VLE sdarel relocs. * testsuite/gas/ppc/power4.d: Adjust.
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira1-0/+1
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M ↵Andre Vieira1-0/+1
Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira1-0/+1
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc ↵Andre Vieira1-0/+1
R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira1-0/+1
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc ↵Andre Vieira1-0/+1
R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real ↵Andre Vieira1-0/+1
for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
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