| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Do not report the warning
when the version of input or output is RISCV_UNKNOWN_VERSION, since
the extension is added implicitly.
* elfxx-riscv.c: Updated the obsolete comments.
(RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h.
* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
|
|
g-ext.
Fix the wrong version of i-ext when expanding g-ext. This was changed by
the previous patch accidently.
bfd/
* elfxx-riscv.c (riscv_parse_std_ext): Fixed the wrong versions of
i-ext when expanding g-ext.
|
|
The linker does not care the default versions of the extensions, since
it does not have the default ISA spec setting. Therefore, linker won't
insert the implicit extensions for the input objects. But we used to
insert the i-ext as the explicit extension, even if the e-ext is set.
This causes linker to report "cannot find default versions of the ISA
extension `i'" errors when linking the input objects with e-ext.
This patch fixes the above linker problem, and also remove the confused
riscv_ext_dont_care_version function. Unless these "dont care" extensions
are set in the input architecture explicitly, otherwise we always insert
them as the implicit ones. Afterwards, let riscv_arch_str1 surpress them
not to output to the architecture string if their versions are
RISCV_UNKNOWN_VERSION.
bfd/
* elfxx-riscv.c (riscv_ext_dont_care_version): Removed.
(riscv_parse_add_subset): Always add the implicit extensions, even if
their versions are RISCV_UNKNOWN_VERSION.
(riscv_parse_std_ext): Delay to add i-ext as the implicit extension
in the riscv_parse_add_implicit_subsets. Besides, add g-ext as the
implicit extension after it has been expanded.
(riscv_parse_add_implicit_subsets): Updated.
|
|
The original discussion is as follows,
https://github.com/riscv/riscv-isa-manual/issues/637
I never considered the prefixes may have multiple letters, like zxm.
But the ISA spec has been updated for a long time that I haven't noticed.
This patch rewrites the part of architecture parser to support parsing
the multi-letter prefixes. Besides, I also improve the parser to report
errors in details. One of the most obvious improvement is - Do not parse
the prefixed extensions according to the orders in the parse_config.
If we do so, then we used to get "unexpected ISA string at end" errors,
but the message is a little bit hard to know what is happening. I Remove
the confused message, and let riscv_parse_prefixed_ext to report the details.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward.
(riscv_std_s_ext_strtab): Likewise.
(riscv_std_h_ext_strtab): Likewise.
(riscv_std_zxm_ext_strtab): Added for the zxm prefix.
(enum riscv_prefix_ext_class): Moved forward and renamed from
riscv_isa_ext_class. Reorder them according to the parsing order,
since the enum values are used to check the orders in the
riscv_compare_subsets.
(struct riscv_parse_prefix_config): Moved forward and renamed from
riscv_parse_config_t. Also removed the ext_valid_p field, the
related functions are replaced by riscv_valid_prefixed_ext.
(parse_config): Moved forward and updated. The more letters of the
prefix string, the more forward it must be defined. Otherwise, we
will get the wrong mapping when using strncmp in riscv_get_prefix_class.
(riscv_get_prefix_class): Moved forward. Support to parse the
multi-letter prefix, like zxm.
(riscv_known_prefixed_ext): New function, check if the prefixed
extension is supported according to the right riscv_std_*_ext_strtab.
(riscv_valid_prefixed_ext): New function, used to replace the
riscv_ext_*_valid_p functions.
(riscv_init_ext_order): Do not set the values for prefix keywords
since they may have multiple letters for now.
(riscv_compare_subsets): Set the order values of prefix keywords
to negative numbers according to the riscv_prefix_ext_class.
(riscv_parse_std_ext): Call riscv_get_prefix_class to see if we
have parsed the prefixed extensions.
(riscv_parse_prefixed_ext): Updated and removed the parameter config.
Report error when the prefix is unknown.
(riscv_parse_subset): Do not parse the prefixed extensions according
to the orders in the parse_config. Remove the confused message and
let riscv_parse_prefixed_ext to report the details.
* elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c.
(riscv_get_prefix_class): Removed to static.
gas/
* testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from
march-fail-porder-x-std.d.
* testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from
march-fail-porder-z-std.d.
* testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from
march-fail-porder-x-z.d.
* testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace
march-fail-porder.l.
* testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Updated.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from
march-fail-single-char-h.d.
* testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from
march-fail-single-char-s.d.
* testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from
march-fail-single-char-x.d.
* testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from
march-fail-single-char-z.d.
* testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added.
* testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace
march-fail-single-prefix.l.
* testsuite/gas/riscv/march-fail-unknown-zxm.d: Added.
* testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
|
|
bfd/ChangeLog:
* elf-bfd.h (bfd_section_is_ctf): Use startswith function.
* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
(elf_get_reloc_section): Likewise.
* elf32-arc.c (elf_arc_size_dynamic_sections): Likewise.
* elf32-m32r.c (m32r_elf_section_flags): Likewise.
* elf32-microblaze.c (microblaze_elf_size_dynamic_sections): Likewise.
* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
(nds32_elf_relocate_section): Likewise.
(nds32_elf_action_discarded): Likewise.
(nds32_elf_check_relocs): Likewise.
(nds32_elf_section_flags): Likewise.
* elf32-or1k.c (or1k_elf_check_relocs): Likewise.
* elf32-ppc.c (ppc_elf_section_from_shdr): Likewise.
* elf32-rx.c (rx_table_find): Likewise.
(rx_table_map): Likewise.
* elf32-spu.c (spu_elf_backend_symbol_processing): Likewise.
(spu_elf_find_overlays): Likewise.
(needs_ovl_stub): Likewise.
(allocate_spuear_stubs): Likewise.
(build_spuear_stubs): Likewise.
(mark_overlay_section): Likewise.
(spu_elf_auto_overlay): Likewise.
(spu_elf_output_symbol_hook): Likewise.
* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
* elf32-xtensa.c (xtensa_property_section_name): Likewise.
* elf64-ppc.c (ppc64_elf_section_flags): Likewise.
(ppc64_elf_relocate_section): Likewise.
* elflink.c (resolve_section): Likewise.
(UNARY_OP): Likewise.
(BINARY_OP_HEAD): Likewise.
(elf_link_input_bfd): Likewise.
* elfnn-riscv.c (riscv_elf_size_dynamic_sections): Likewise.
* elfxx-riscv.c (riscv_parse_subset): Likewise.
* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
* opncls.c (get_build_id): Likewise.
binutils/ChangeLog:
* dllwrap.c: Use startswith function.
* objcopy.c (is_dwo_section): Likewise.
(handle_remove_section_option): Likewise.
(copy_main): Likewise.
* objdump.c (is_significant_symbol_name): Likewise.
|
|
* sysdep.h: POISON_BFD_BOOLEAN: Define.
* aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h,
* aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c,
* bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c,
* coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c,
* coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c,
* coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c,
* coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
* coffcode.h, * coffgen.c, * cofflink.c, * compress.c,
* corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c,
* cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c,
* cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c,
* cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c,
* cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c,
* cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c,
* cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c,
* cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c,
* cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c,
* cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c,
* cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c,
* cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c,
* cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c,
* cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c,
* cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c,
* cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c,
* cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c,
* cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c,
* cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c,
* cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c,
* cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c,
* dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c,
* elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c,
* elf-nacl.h, * elf-properties.c, * elf-s390-common.c,
* elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h,
* elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c,
* elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c,
* elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c,
* elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c,
* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
* elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
* elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c,
* elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
* elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c,
* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
* elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c,
* elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h,
* elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h,
* elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h,
* elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
* elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c,
* elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c,
* elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c,
* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
* elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c,
* elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h,
* elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c,
* elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c,
* elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h,
* elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h,
* elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h,
* elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h,
* format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c,
* i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h,
* libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h,
* libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c,
* mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h,
* merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c,
* pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c,
* pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c,
* pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c,
* peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c,
* reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c,
* som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c,
* verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h,
* wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c,
* xsym.h: Replace bfd_boolean with bool, FALSE with false, and
TRUE with true throughout.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* libcoff.h: Regenerate.
|
|
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
gas/
* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext.d: Likewise.
include/
* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
|
|
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM: Renamed from SBTYPE_IMM.
JTYPE_IMM: Renamed from UJTYPE_IMM.
CITYPE_IMM: Renamed from RVC_IMM.
CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM: Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM: Added for .insn without special encoding.
CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
CLTYPE_IMM: Added for .insn without special encoding.
CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
RVC_SIMM3: Unused and removed.
CBTYPE_IMM: Renamed from RVC_B_IMM.
CJTYPE_IMM: Renamed from RVC_J_IMM.
* Added new operands and removed the unused ones,
C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.
bfd/
PR 27158
* elfnn-riscv.c (perform_relocation): Updated encoding macros.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
gas/
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
gdb/
PR 27158
* riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
(decode_j_type_insn): Likewise.
(decode_cj_type_insn): Likewise.
(decode_b_type_insn): Likewise.
(decode): Likewise.
include/
PR 27158
* opcode/riscv.h: Updated encoding macros.
opcodes/
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
sim/
PR 27158
* riscv/sim-main.c (execute_i): Updated encoding macros.
|
|
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use. To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.
bfd/
* Makefile.am: Added cpu-riscv.h.
* Makefile.in: Regenerated.
* po/SRC-POTFILES.in: Regenerated.
* cpu-riscv.h: Added to support spec versions controlling.
Also added extern arrays and functions for cpu-riscv.c.
(enum riscv_spec_class): Define all spec classes here uniformly.
(struct riscv_spec): Added for all specs.
(RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
(RISCV_GET_SPEC_NAME): Likewise.
(RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
(RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
(RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
* cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
(riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
(riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
(riscv_priv_specs): Moved below.
(riscv_get_priv_spec_class_from_numbers): Likewise, updated.
(riscv_isa_specs): Moved from include/opcode/riscv.h.
* elfnn-riscv.c: Included cpu-riscv.h.
(riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
* elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
(RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
* elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
* config/tc-riscv.c: Included cpu-riscv.h.
(enum riscv_csr_clas): Moved from include/opcode/riscv.h.
(struct riscv_csr_extra): Likewise.
(struct riscv_ext_version): Likewise.
(ext_version_table): Moved from opcodes/riscv-opc.c.
(default_isa_spec): Updated type to riscv_spec_class.
(default_priv_spec): Likewise.
(riscv_set_default_isa_spec): Updated.
(init_ext_version_hash): Likewise.
(riscv_init_csr_hash): Likewise, also fixed indent.
include/
* opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
|
|
bfd/
* elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Removed
INSN_CLASS_ZB*.
* testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
* testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
* testsuite/gas/riscv/bitmanip-insns.s: Removed.
include/
* opcode/riscv-opc.h: Removed macros for zb* extensions.
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (MASK_RVB_IMM): Removed.
(riscv_opcodes): Removed zb* instructions.
(riscv_ext_version_table): Removed versions for zb*.
|
|
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces. But sometimes it should be more
cleaner when the comments only include a word or codes. Therefore, I made
the following changes after referring to other target/generic codes,
* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.
Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.
bfd/
* elfnn-riscv.c: Comments tidy and improvement.
* elfxx-riscv.c: Likewise.
* elfxx-riscv.h: Likewise.
gas/
* config/tc-riscv.c: Comments tidy and improvement. Also update
comment "fallthru" to "Fall through" that end with a period and
two spaces.
include/
* elf/riscv.h: Comments tidy and improvement.
* opcode/riscv-opc.h: Likewise.
* opcode/riscv.h: Likewise.
opcodes/
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
|
|
Add support for the pause hint instruction, as specified in the
Zihintpause extension. The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set). The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Added
INSN_CLASS_ZIHINTPAUSE.
* testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
the pause hint instruction.
* testsuite/gas/riscv/pause.s: Likewise.
include/
* opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
for pause hint instruction.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
|
|
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them. Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.
This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
(enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
frozen extensions.
opcodes/
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
|
|
Similar to the commit 6729e2c2af2bd94408430734316597843718a484,
we have to check the first char of the Z* extensions, to make
sure that they follow the order of the standard extensions.
bfd/
* elfxx-riscv.c (riscv_compare_subsets): Removed static.
* elfxx-riscv.h: Add declaration.
* elfnn-riscv.c (riscv_merge_multi_letter_ext): Use
riscv_compare_subsets to check the orders.
(riscv_skip_prefix): Removed.
(riscv_prefix_cmp): Removed.
|
|
ISO/IEC 9899:1999 C standard "J.2 Undefined behavior" says the
following is undefined behaviour:
"The value of a pointer that refers to space deallocated by a call to
the free or realloc function is used (7.20.3)."
PR 26741
* elfxx-riscv.c (riscv_parse_prefixed_ext): Free subset after
calculating subset version length.
|
|
|
|
bfd/
* elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return
TRUE if we don't care the versions of the extensions. These extensions
are added to the subset list for special purposes, with the explicit
versions or the RISCV_UNKNOWN_VERSION versions.
(riscv_parse_add_subset): If we do care the versions of the extension,
and the versions are unknown, then report errors for the non-implicit
extensions, and return directly for the implicit one.
(riscv_arch_str1): Do not output i extension after e, and the extensions
which versions are unknown.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
and INSN_CLASS_ZIFENCEI.
* testsuite/gas/riscv/march-imply-i.s: New testcase.
* testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version
of i is less than 2.1, and zi* are supported in the chosen spec, so
enable the fence.i and csr instructions, also output the implicit zi* to
the arch string.
* testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
not supported in the spec 2.2. Enable the related instructions since
i's version is less than 2.1, but do not output them.
* testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version
of i is 2.1, so don't add it's implicit zi*, and disable the related
instructions.
* testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
explicitly, so enable the related instructions.
* testsuite/gas/riscv/march-imply-i2p0.d: Removed.
* testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
* opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
* riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
zifencei and zicsr.
|
|
We have to check the first char of the Z* extensions, to make sure that
they follow the order of the standard extensions. But we can not have
the testcases for this patch, since we only support the zicsr and zifencei
so far, both of them are the sub extensions of i.
bfd/
* elfxx-riscv.c (riscv_parse_prefixed_ext): Use riscv_compare_subsets
to check the Z* extensions' order.
|
|
G is a special case, consider the ISA spec github issue as follows,
https://github.com/riscv/riscv-isa-manual/issues/575
My understand is that - i, m, a, f and d extensions are not g's implicit
extensions, they are g's expansions. The zifencei is the implicit extension
of g, and so is zicsr, since it is implicited by f (or i2p1). However,
we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
will not output to the arch string, it is only used to check what implicit
extensions are need to be added.
bfd/
* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
RISCV_UNKNOWN_VERSION versions.
(riscv_parse_std_ext): Add g to the subset list, we only use it
to add the implicit extensions, but won't output it to arch string.
(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
for g extension.
(riscv_arch_str1): Do not output g to the arch string.
* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.
gas/
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
are not supported in the ISA spec v2.2, so don't add and output them.
include/
* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
|
|
We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions. That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions. For now we
follow the following rules to add the implicit extensions,
* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.
Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.
bfd/
* elfnn-riscv.c (riscv_merge_std_ext): Updated since
riscv_lookup_subset is changed.
* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
extensions' order quickly.
(riscv_init_ext_order): New function. Init the riscv_ext_order
according to the riscv_supported_std_ext and parse_config[i].class
automatically.
(riscv_compare_subsets): New function. Similar to the strcmp, but
compare the subsets with the specific order.
(riscv_lookup_subset): Return TRUE and set `current` to the subset
if it is found. Otherwise, return FALSE and set `current` to the
place where we should insert the subset.
(riscv_add_implicit_subset): New function. Search the list first,
and then find the right place to add the implicit_subset.
(riscv_parse_add_subset): Since We have to add all arch string
extensions first, and then start to add their implicit extensions.
We can add arch string extensions in order by the original
riscv_add_subset, and then add the implicit subsets by the
riscv_add_implicit_subset. Besides, do not add the implicit
extensions if we failed to find their default versions.
(riscv_parse_std_ext): Updated.
(riscv_parse_add_implicit_subsets): New function. Add all implicit
extensions according to the arch string extensions.
(riscv_parse_subset): Call riscv_init_ext_order and
riscv_parse_add_implicit_subsets, before and after parsing the
arch string. Remove parts of the ISA conflict checking since
the implicit extensions are added.
* elfxx-riscv.h (riscv_lookup_subset): Updated.
gas/
* config/tc-riscv.c (riscv_subset_supports): Updated.
* testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to
add the implicit zicsr and zifencei when i's version less than 2.1.
* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
* testsuite/gas/riscv/march-imply-d.d: Likewise.
* testsuite/gas/riscv/march-imply-f.d: Likewise.
* testsuite/gas/riscv/march-imply-q.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
|
|
Keep the riscv_add_subset to do the same thing, and use a new
function, riscv_parse_add_subset, to cover most of the things
when parsing, including find the default versions for extensions,
and check whether the versions are valid. The version 0p0 should
be an invalid version, that is the mistake I made before. This
patch clarify the version rules as follows,
* We accept any version of extensions set by users, except 0p0.
* The non-standard x extensions must be set with versions in arch string.
* If user don't set the versions, or set 0p0 for the extensions, then try
to find the supported versions according to the chosen ISA spec.
Otherwise, report errors rather than output 0p0 for them.
Besides, we use as_bad rather than as_fatal to report more errors
for assembler.
bfd/
* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
(riscv_add_subset): Likewise.
(riscv_release_subset_list): Likewise.
(riscv_parse_add_subset): New function. Find and check the
versions before adding them by riscv_add_subset.
(riscv_parsing_subset_version): Remove use_default_version
and change the version type from unsigned to int. Set the
versions to RISCV_UNKNOWN_VERSION if we can not find them
in the arch string.
(riscv_parse_std_ext): Updated.
(riscv_parse_prefixed_ext): Updated. Since we use as_bad
rather than as_fatal to report more errors, return NULL
string if the parsed end_of_version is NULL, too.
(riscv_parse_subset): Use a new boolean, no_conflict, to
report more errors when we have more than one ISA conflicts.
* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
RISCV_UNKNOWN_VERSION.
(riscv_lookup_subset_version): Removed.
(riscv_parse_subset_t): Updated.
gas/
* config/tc-riscv.c (riscv_get_default_ext_version):
Change the version type from unsigned to int.
(riscv_set_arch): Use as_bad rather than as_fatal to
report more errors.
* testsuite/gas/riscv/attribute-02.d: Updated since x must be
set with versions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
in the spec 2.2, so choose the newer spec.
* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-porder.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.
include/
* opcode/riscv.h (riscv_ext_version):
Change the version type from unsigned to int.
|
|
bfd/
* elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard
extensions when parsed h keyword.
(riscv_get_prefix_class): Support prefixed h class.
(riscv_std_h_ext_strtab): Likewise.
(riscv_ext_h_valid_p): Likewise.
(parse_config): Likewise.
(riscv_std_z_ext_strtab): Add zifencei.
* elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H.
gas/
* testsuite/gas/riscv/march-fail-order-z.d: New testcase, check
orders of prefixed z extensions.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char-h.d: New testcase.
* testsuite/gas/riscv/march-fail-single-char.l: Updated.
* testsuite/gas/riscv/march-fail-unknown-h.d: New testcase.
* testsuite/gas/riscv/march-fail-unknown.l: Updated.
opcodes/
* riscv-opc.c (riscv_ext_version_table): Add zifencei.
|
|
Although I cannot find any RISC-V specs said that uppercases are not
allowed in the arhc string, but seems like it is an established fact
both for GNU and LLVM. Therefore, we shouldn't allow the uppercases
for the non-standard x extensions, too.
bfd/
* elfxx-riscv.c (riscv_parse_subset): ISA string cannot contain
any uppercase letter.
gas/
* testsuite/gas/riscv/march-fail-uppercase-base.d: Updated.
* testsuite/gas/riscv/march-fail-uppercase.l: Updated.
* testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase.
|
|
Re-indent the related codes, unify and improve the related error messages
and comments. Besies, also re-write the testcases to cover more cases.
bfd/
* elfxx-riscv.c: Re-indent codes, unify and improve the error
messages and comments.
(riscv_parse_prefixed_ext): Stop parsing the prefixed class
extensions if the class is RV_ISA_CLASS_UNKNOWN, I get internal
errors before adding this check for march-fail-porder* testcases.
(riscv_parse_subset): Move the rv32 with q checking in front.
* elfxx-riscv.h: Likewise.
gas/
(These are new testcases that cover more cases)
* testsuite/gas/riscv/march-fail-base-01.d: The first extension must
be e, i or g.
* testsuite/gas/riscv/march-fail-base-01.l: Likewise.
* testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA.
* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
* testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard
extensions.
* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed
x extensions.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when
standard and prefixed extensions are set at the same time.
* testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise.
* testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise.
* testsuite/gas/riscv/march-fail-porder.l: Likewise.
* testsuite/gas/riscv/march-fail-single-char-s.d: Only standard
extensions can use single char.
* testsuite/gas/riscv/march-fail-single-char-x.d: Likewise.
* testsuite/gas/riscv/march-fail-single-char-z.d: Likewise.
* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-s.d: All extensions
should be known, except the non-standard x extensions.
* testsuite/gas/riscv/march-fail-unknown-std.d: Likewise.
* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-z.d: Likewise.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
* testsuite/gas/riscv/march-fail-uppercase-base.d: Do not
allow any uppercase in the arch string.
* testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise.
* testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise.
* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
* testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions.
* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ef.l: Updated.
* testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext.
* testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
(The following testcases are removed and covered by new testcases)
* testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base.
* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std.
* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std.
* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x.
* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std.
* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std.
* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02.
* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
* testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-s-with-version.l: Likewise.
* testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-s.l: Likewise.
* testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s.
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
|
|
Generally, glibc dynamic linker should have two ways to deal with ifunc
- one is to handle the IRELATIVE relocations for the non-preemtive ifunc
symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT
relocations with the STT_IFUNC preemtive symbols. No matter which method
is used, both of them should get the resolved ifunc symbols at runtime.
Therefore, linker needs to generate the correct dynamic relocations for
ifunc to make sure the the dynamic linker works well. For now, there are
thirteen relocations are supported for ifunc in GNU ld,
* R_RISCV_CALL and R_RISCV_CALL_PLT:
The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an
ifunc. Besides, we disable the relaxations for the relocation referenced
to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be
enough. Linker should generate a .plt entry and a .got.plt entry for it,
and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or
insert a R_RISCV_JUMP_SLOT when generating shared library.
* R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S:
LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol.
The PC-relative relocation. The current linker will deal with them in
the same way as R_RISCV_CALL_PLT.
* R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S:
LA pattern with global PIC ifunc symbol. Linker should insert a dynamic
IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating
shared library.
* R_RISCV_32 and R_RISCV_64:
Store the ifunc symbol into the data section. Linker should insert a
dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when
generating shared library.
* R_RISCV_HI20 and R_RISCV_LO12_I/S:
The LUI + ADDI/LW/SW patterns. The absolute access relocation. The
medlow model without the -fPIC compiler option should generate them.
The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the
relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler
support.
However, we also made some optimizations with reference to x86,
* If GOT and PLT relocations refer to the same ifunc symbol when generating
pie, then they can actually share a .got entry without creating two entries
to store the same value and relocation.
* If GOT, PLT and DATA relocations refer to the same ifunc symbol when
generating position dependency executable, then linker will fill the address
of .plt entry into the corresponding .got entry and data section, without
insert any dynamic relocations for the GOT and DATA relocations.
For the ifunc testcases, there are three types of them,
1. ifunc-reloc-*: Only check the single type of relocation refers to
ifunc symbol.
* ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT.
* ifunc-reloc-data: R_RISCV_32 and R_RISCV_64.
* ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S.
* ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S.
2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to
create the PLT and it's .plt entries.
* ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64.
* ifunc-plt: Combine all ifunc relocations.
3. ifunc-seperate-*: If we link the ifunc caller and resolver into the
same module (link the objects), then the results are the same as the
ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that
the ifunc callers and resolver are in the different modules, that is, we
compile the ifunc resolver to the shared library first, and then link it
with the ifunc callers. The output of ifunc callers should be the same as
the normal STT_FUNC cases, and the shared ifunc resolver should define the
symbols as STT_IFUNC.
The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved
locally, so if the ifunc resolver is defined in other modules (other shared
libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should
issue an unresolvable reloc error.
bfd/
* elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc.
(riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory
for local STT_GNU_IFUNC symbols.
(riscv_elf_got_plt_val): Removed.
(riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions.
Use to compare local hash entries.
(riscv_elf_get_local_sym_hash): New function. Find a hash entry for
local symbol, and create a new one if needed.
(riscv_elf_link_hash_table_free): New function. Destroy an riscv
elf linker hash table.
(riscv_elf_link_hash_table_create): Create hash table for local ifunc.
(riscv_elf_check_relocs): Create a fake global symbol to track the
local ifunc symbol. Add support to check and handle the relocations
reference to ifunc symbols.
(allocate_dynrelocs): Let allocate_ifunc_dynrelocs and
allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they
are defined and referenced in a non-shared object.
(allocate_ifunc_dynrelocs): New function. Allocate space in .plt,
.got and associated reloc sections for ifunc dynamic relocs.
(allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc
dynamic relocs.
(riscv_elf_relocate_section): Add support to handle the relocation
referenced to ifunc symbols.
(riscv_elf_size_dynamic_sections): Updated.
(riscv_elf_adjust_dynamic_symbol): Updated.
(riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling,
including fill the PLT and GOT entries for ifunc symbols.
(riscv_elf_finish_local_dynamic_symbol): New function. Called by
riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols.
(_bfd_riscv_relax_section): Don't do the relaxation for ifunc.
* elfxx-riscv.c: Add R_RISCV_IRELATIVE.
* configure.ac: Link elf-ifunc.lo to use the generic ifunc support.
* configure: Regenerated.
include/
* elf/riscv.h: Add R_RISCV_IRELATIVE to 58.
ld/
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
New dump test for ifunc. There are two arguments, 'target` and
`output`. The `target` is rv32 or rv64, and the `output` is used
to choose which output you want to test (exe, pie or .so).
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
|
|
This patch corrects "size" and "bitsize" in R_RISCV_RVC_* reloc howtos
so that elfnn-riscv.c:perform_relocation doesn't access past the end
of a section. I've also corrected "size" in the R_RISCV_CALL* reloc
howtos since these relocs apply to two consecutive instructions. That
caused fallout in the assembler with complaints about "fixup not
contained within frag" due to tc-riscv.c:append_insn finishing off a
frag after the auipc insn making up a "call" macro. Which is a little
rude since the CALL reloc also relocates the following jalr. Fixed by
changing the frag handling a little.
I've also changed R_RISCV_ALIGN and R_RISCV_TPREL_ADD marker reloc
howtos to look like R_RISCV_NONE, and corrected dst_mask for numerous
relocs, not that it matters very much.
bfd/
PR 26569
* elfxx-riscv.c (howto_table): Correct size and bitsize of
R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, and R_RISCV_RVC_LUI.
Correct size for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPREL32,
R_RISCV_CALL, and R_RISCV_CALL_PLT. Make R_RISCV_TPREL_ADD and
R_RISCV_ALIGN like R_RISCV_NONE. Correct dst_mask many relocs.
gas/
* config/tc-riscv.c (append_insn): Don't tie off frags at CALL
relocs.
(riscv_call): Tie them off after the jalr.
(md_apply_fix): Zero fx_size of RELAX fixup.
|
|
Consider the updated attr-merge-arch-failed-01.d testcase. Extension
A's version are mis-matched between attr-merge-arch-failed-01a.s and
attr-merge-arch-failed-01b.s. But the old binutils reports that the
mis-matched extension is M rather than A. This commit is used to fix
the wrong mis-matched error message.
Besides, when parsing the arch string in the riscv_parse_subset, it
shouldn't be NULL or empty. However, it might be empty when we failed
to merge the arch string in the riscv_merge_attributes. Since we should
already issue the correct error message in another side, and the message
- ISA string must begin with rv32 or rv64 - is meaninglesss when the arch
string is empty, so do not issue it.
bfd/
* elfnn-riscv.c (riscv_merge_std_ext): Fix to report the correct
error message when the versions of extension are mis-matched.
* elfxx-riscv.c (riscv_parse_subset): Don't issue the error when
the string is empty.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise.
|
|
By the look of it, git commit 39ff0b812324 broke 32-bit host
--enable-targets=all binutils builds.
/usr/local/bin/ld: ../opcodes/.libs/libopcodes.a(riscv-dis.o): in function `parse_riscv_dis_option':
/home/alan/src/binutils-gdb/opcodes/riscv-dis.c:102: undefined reference to `riscv_get_priv_spec_class'
collect2: error: ld returned 1 exit status
Makefile:925: recipe for target 'objdump' failed
The problem is that elfxx-riscv.c is not built for a 32-bit host
without --enable-64-bit-bfd or unless RISCV is given specifically as a
target. No such trimming of 64-bit only targets is done in opcodes.
One solution is to move these support functions to cpu-riscv.c, which
runs into "error: implicit declaration of function ‘xmalloc’". Now,
xmalloc is not supposed to be used in libbfd or libopcodes - it's rude
to crash out of an application that calls libbfd or libopcodes
functions without giving it a chance to deal with out-of-memory
itself. So I removed the xmalloc and instead used a fixed size
buffer. If you are worried about adding 36 bytes for the buffer to
the riscv_get_priv_spec_class_from_numbers stack frame size, then you
have no idea of the likely xmalloc + malloc stack frame size! Trying
to reduce memory usage is commendable, but in this instance
riscv_estimate_digit and malloc for a temp buffer uses a lot more
memory than a fixed max-size buffer.
* elfxx-riscv.c (struct priv_spec_t, priv_specs),
(riscv_get_priv_spec_class, riscv_get_priv_spec_class_from_numbers),
(riscv_get_priv_spec_name): Move to..
* cpu-riscv.c: ..here.
(riscv_get_priv_spec_class_from_numbers): Don't xmalloc temp buffer.
Use %u to print unsigned numbers.
|
|
We do know some conflicts among different privileged specs. For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts. But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems. But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs. But the option
is still under discussion.
Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs. This not only makes the linker more flexible,
but also warns people that the conflicts may happen. We also need to update
the output priv spec version once the input priv spec is newer.
bfd/
* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
(riscv_get_priv_spec_class): Likewise.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New function, convert
the version numbers into string, then call riscv_get_priv_spec_class
to get the priv spec class.
* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
from include/opcode/riscv.h to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New forward declaration.
(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
* elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes
of input and output objects form their priv spec attributes by
riscv_get_priv_spec_class_from_numbers. Report warning rather than
errors when linking objects with differnet priv spec versions. We do
know v1.9.1 may have conflicts to other versions, so report the
warning, too. After that, update the output priv spec version to the
newest one so far.
gas/
* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
(riscv_set_default_priv_spec): Get the priv spec version from the
priv spec attributes by riscv_get_priv_spec_class_from_numbers.
include/
* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
forward declarations to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
opcodes/
* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
* riscv-dis.c: Include elfxx-riscv.h.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
|
|
extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
|
|
Similar to 2d0e121701a95e0f37af02bc622393b1ccd88c76.
bfd/
* elfxx-riscv.c (riscv_parse_subset): Don't use C99.
|
|
We can't use c99 without enabling c99 support for older compilers
that don't enable c99 by default. So if you want to use c99 contructs
in binutils you'll need to first arrange for -std=c99 to be passed to
older compilers.
* elfxx-riscv.c (riscv_multi_letter_ext_valid_p): Don't use C99.
|
|
Looking at older versions of the patch, I confirmed that the odd comment
I referred to earlier was indeed from the removal of the sx support. It
also explains an oddly formatted switch statement. This patch fixes both
minor problems.
bfd/
* elfxx-riscv.c (riscv_get_prefix_class): Format s case like others.
(riscv_parse_prefixed_ext): Fix s extension comment and reword to
avoid over long line.
Change-Id: I1cb62e4a16188270f029b6376e4b1684000d6c7a
|
|
bfd/
2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
* bfd/elfnn-riscv.c (riscv_skip_prefix): New.
(riscv_prefix_cmp): Likewise.
(riscv_non_std_ext_p): Deleted.
(riscv_std_sv_ext_p): Likewise.
(riscv_non_std_sv_ext_p): Likewise.
(riscv_merge_non_std_and_sv_ext): Rename to...
(riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp.
(riscv_merge_arch_attr_info): Replace 3 calls to
riscv_merge_non_std_and_sv_ext with single call to
riscv_merge_multi_letter_ext.
* bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we
encounter a 'z' prefix.
(riscv_get_prefix_class): New function, return prefix class based
on first few characters of input string.
(riscv_parse_config): New structure to factor out minor differences
in extension class parsing behaviour.
(riscv_parse_sv_or_non_std_ext): Rename to...
(riscv_parse_prefixed_ext): and parameterise with
riscv_parse_config.
(riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New.
(riscv_multi_letter_ext_valid_p): New.
(riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New.
(riscv_parse_subset): Delegate all non-single-letter parsing work
to riscv_parse_prefixed_ext.
* bfd/elfxx-riscv.h (riscv_isa_ext_class): New type.
(riscv_get_prefix_class): Declare.
gas/
2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
s exts must be known, so rename *ok* to *fail*.
* testsuite/gas/riscv/march-ok-sx.d: Likewise.
* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
above change.
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.
Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
|
|
seperate -> separate
bfd/ChangeLog:
2020-01-17 Christian Biesinger <cbiesinger@google.com>
* coff-arm.c: Fix spelling error (seperate).
* elfxx-riscv.c (riscv_parse_sv_or_non_std_ext): Fix spelling
error (seperate).
* sysdep.h (strnlen): Fix spelling error (seperate).
opcodes/ChangeLog:
2020-01-17 Christian Biesinger <cbiesinger@google.com>
* opintl.h: Fix spelling error (seperate).
sim/arm/ChangeLog:
2020-01-17 Christian Biesinger <cbiesinger@google.com>
* iwmmxt.c: Fix spelling error (seperate).
Change-Id: I55e5f47bcf3cf3533d2acb7ad338f1be0d5f30f9
|
|
|
|
* coff-i386.c, * coff-x86_64.c, * coffgen.c, * dwarf2.c,
* elf-m10200.c, * elf.c, * elf32-arm.c, * elf32-bfin.c,
* elf32-csky.c, * elf32-m32r.c, * elf32-microblaze.c, * elf32-pru.c,
* elf32-rx.c, * elf32-xgate.c, * elf64-sparc.c, * elfnn-ia64.c,
* elfxx-riscv.c, * elfxx-sparc.c, * linker.c, * mach-o.c,
* pe-x86_64.c, * pei-x86_64.c, * plugin.c: Whitespace fixes.
|
|
2019-01-16 Kito Cheng <kito@andestech.com>
Nelson Chu <nelson@andestech.com>
bfd/
* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Define as
riscv_elf_obj_attrs_arg_type.
* elfxx-riscv.c (riscv_estimate_digit): New.
(riscv_estimate_arch_strlen1): Likewise.
(riscv_estimate_arch_strlen): Likewise.
(riscv_arch_str1): Likewise.
(riscv_arch_str): Likewise.
* elfxx-riscv.h (riscv_arch_str): Declare.
binutils/
* readelf.c (get_riscv_section_type_name): New function.
(get_section_type_name): Add handler for RISC-V.
(riscv_attr_tag_t): Declare.
(riscv_attr_tag): New.
(display_riscv_attribute): New function.
(process_attributes): Add handler for RISC-V.
* testsuite/binutils-all/strip-3.d: Remove .riscv.attribute
section.
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
(riscv_set_options): Add `arch_attr` field.
(riscv_opts): Set default value for arch_attr.
(riscv_write_out_arch_attr): New.
(riscv_set_public_attributes): Likewise.
(riscv_md_end): Likewise.
(riscv_convert_symbolic_attribute): Likewise.
(s_riscv_attribute): Likewise.
(explicit_arch_attr): Likewise.
(riscv_pseudo_table): Add .attribute to the table.
(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
enumeration constants.
(md_longopts): Add `march-attr' and `mno-arch-attr' options.
(md_parse_option): Handle the new options.
(md_show_usage): Document the `march-attr' option.
* config/tc-riscv.h (md_end): Define as riscv_md_end
(riscv_md_end): Declare.
(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
riscv_convert_symbolic_attribute.
(riscv_convert_symbolic_attribute): Declare.
(start_assemble): Declare.
* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
* testsuite/gas/elf/section2.e-riscv: New.
* testsuite/gas/riscv/attribute-01.d: New test
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-04.s: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-06.s: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-07.s: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-08.s: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.s: Likewise.
* testsuite/gas/riscv/empty.l: Likewise.
* doc/c-riscv.texi (.attribute): Add documentation.
* configure.ac (--enable-default-riscv-attribute): New options.
* configure: Re-generate.
* config.in: Re-generate.
include/
* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
(Tag_RISCV_arch): Likewise.
(Tag_RISCV_priv_spec): Likewise.
(Tag_RISCV_priv_spec_minor): Likewise.
(Tag_RISCV_priv_spec_revision): Likewise.
(Tag_RISCV_unaligned_access): Likewise.
(Tag_RISCV_stack_align): Likewise.
|
|
|
|
This patch adds bfd_stdint.h to bfd.h, so that BFD can use size_t
where appropriate in function parameters and return values. I also
tidy a few other cases where headers are included twice.
bfd/
* Makefile.am (bfdinclude_HEADERS): Add bfd_stdint.h.
(BFD_H_DEPS): Add include/diagnostics.h.
(LOCAL_H_DEPS): Add bfd_stdint.h.
* bfd-in.h: Include bfd_stdint.h.
* arc-plt.h: Don't include stdint.h.
* coff-rs6000.c: Likewise.
* coff64-rs6000.c: Likewise.
* elfxx-riscv.c: Likewise.
* cache.c: Don't include bfd_stdint.h.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-rx.c: Likewise.
* elf32-wasm32.c: Likewise.
* elf64-nfp.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfxx-ia64.c: Likewise.
* elfxx-x86.h: Likewise.
* wasm-module.c: Likewise, and don't include sysdep.h twice.
* elf-nacl.h: Don't include bfd.h.
* mach-o.h: Likewise.
* elfxx-aarch64.c: Include bfd.h and elf-bfd.h.
* elfxx-aarch64.h: Don't include bfd.h, elf-bfd.h or stdint.h.
* mach-o-aarch64.c: Include mach-o.h later.
* mach-o-arm.c: Likewise.
* mach-o-i386.c: Likewise.
* mach-o-x86-64.c: Likewise.
* mach-o.c: Likewise.
* sysdep.h: Don't include ansidecl.h or sys/stat.h.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
opcodes/
* arm-dis.c: Include bfd.h.
* aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
* csky-dis.c: Likewise.
* nds32-asm.c: Likewise.
* riscv-dis.c: Likewise.
* s12z-dis.c: Likewise.
* wasm32-dis.c: Likewise.
|
|
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.
bfd/
* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
(struct riscv_subset_t): New structure.
(riscv_subset_t): New typedef.
(riscv_subset_list_t): New structure.
(riscv_release_subset_list): New prototype.
(riscv_add_subset): Likewise.
(riscv_lookup_subset): Likewise.
(riscv_lookup_subset_version): Likewise.
(riscv_release_subset_list): Likewise.
* elfxx-riscv.c: Include safe-ctype.h.
(riscv_parsing_subset_version): New function.
(riscv_supported_std_ext): Likewise.
(riscv_parse_std_ext): Likewise.
(riscv_parse_sv_or_non_std_ext): Likewise.
(riscv_parse_subset): Likewise.
(riscv_add_subset): Likewise.
(riscv_lookup_subset): Likewise.
(riscv_lookup_subset_version): Likewise.
(riscv_release_subset_list): Likewise.
gas/
* config/tc-riscv.c: Include elfxx-riscv.h.
(struct riscv_subset): Removed.
(riscv_subsets): Change type to riscv_subset_list_t.
(riscv_subset_supports): Removed argument: xlen_required and move
logic into libbfd.
(riscv_multi_subset_supports): Removed argument: xlen_required.
(riscv_clear_subsets): Removed.
(riscv_add_subset): Ditto.
(riscv_set_arch): Extract parsing logic into libbfd.
(riscv_ip): Update argument for riscv_multi_subset_supports and
riscv_subset_supports. Update riscv_subsets due to struct definition
changed.
(riscv_after_parse_args): Update riscv_subsets due to struct
definition changed, update and argument for riscv_subset_supports.
* testsuite/gas/riscv/empty.s: New.
* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
* testsuite/gas/riscv/march-ok-g2.d: Likewise.
* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
* testsuite/gas/riscv/march-ok-s.d: Likewise.
* testsuite/gas/riscv/march-ok-sx.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
include/
* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
unsigned.
opcodes/
* riscv-opc.c: Change the type of xlen, because type of
xlen_requirement changed.
|
|
It must get boring translating all the variants we have of
unrecognized/unsupported/invalid/unexpected reloc number. This patch
cuts down on the number of variations.
* aoutx.h, * coff-alpha.c, * coff-i860.c, * coff-m68k.c,
* coff-mcore.c, * coff-ppc.c, * coff-rs6000.c, * coff-sh.c,
* coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c, * coff-w65.c,
* elf-bfd.h, * elf-m10300.c, * elf.c, * elf32-avr.c, * elf32-bfin.c,
* elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c,
* elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
* elf32-fr30.c, * elf32-frv.c, * elf32-i370.c, * elf32-i386.c,
* elf32-i960.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c,
* elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
* elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
* elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c,
* elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-or1k.c,
* elf32-pj.c, * elf32-ppc.c, * elf32-rl78.c, * elf32-rx.c,
* elf32-s390.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
* elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
* elf32-xgate.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
* elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c,
* elfnn-riscv.c, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-riscv.h,
* elfxx-sparc.c, * elfxx-sparc.h, * reloc.c: Standardize
unrecognized/unsupported reloc message.
|
|
|
|
Binutils is supposed to use tabs. In my git config I have
whitespace = indent-with-non-tab,space-before-tab,trailing-space
and I got annoyed enough seeing red in "git diff" output to fix
the problems.
* doc/header.sed: Trim trailing space when splitting lines.
* aix386-core.c, * aout-adobe.c, * aout-arm.c, * aout-cris.c,
* aout-ns32k.c, * aout-target.h, * aout-tic30.c, * aoutf1.h, * aoutx.h,
* arc-got.h, * arc-plt.def, * arc-plt.h, * archive.c, * archive64.c,
* archures.c, * armnetbsd.c, * bfd-in.h, * bfd.c, * bfdio.c, * binary.c,
* bout.c, * cache.c, * cisco-core.c, * coff-alpha.c, * coff-apollo.c,
* coff-arm.c, * coff-h8300.c, * coff-i386.c, * coff-i860.c,
* coff-i960.c, * coff-m68k.c, * coff-m88k.c, * coff-mcore.c,
* coff-mips.c, * coff-ppc.c, * coff-rs6000.c, * coff-sh.c,
* coff-stgo32.c, * coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c,
* coff-we32k.c, * coff-x86_64.c, * coff-z80.c, * coff-z8k.c,
* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
* coffswap.h, * compress.c, * corefile.c, * cpu-alpha.c, * cpu-arm.c,
* cpu-avr.c, * cpu-bfin.c, * cpu-cr16.c, * cpu-cr16c.c, * cpu-crx.c,
* cpu-d10v.c, * cpu-frv.c, * cpu-ft32.c, * cpu-i370.c, * cpu-i960.c,
* cpu-ia64-opc.c, * cpu-ip2k.c, * cpu-lm32.c, * cpu-m32r.c,
* cpu-mcore.c, * cpu-microblaze.c, * cpu-mips.c, * cpu-moxie.c,
* cpu-mt.c, * cpu-nios2.c, * cpu-ns32k.c, * cpu-or1k.c, * cpu-powerpc.c,
* cpu-pru.c, * cpu-sh.c, * cpu-spu.c, * cpu-v850.c, * cpu-v850_rh850.c,
* cpu-xgate.c, * cpu-z80.c, * dwarf1.c, * dwarf2.c, * ecoff.c,
* ecofflink.c, * ecoffswap.h, * elf-bfd.h, * elf-eh-frame.c,
* elf-hppa.h, * elf-m10200.c, * elf-m10300.c, * elf-s390-common.c,
* elf-strtab.c, * elf-vxworks.c, * elf.c, * elf32-am33lin.c,
* elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-avr.h,
* elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c,
* elf32-crx.c, * elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c,
* elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c,
* elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-i860.c,
* elf32-i960.c, * elf32-ip2k.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c, * elf32-m68hc1x.c,
* elf32-m68hc1x.h, * elf32-m68k.c, * elf32-m88k.c, * elf32-mcore.c,
* elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nds32.h, * elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c,
* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
* elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score.h,
* elf32-score7.c, * elf32-sh-symbian.c, * elf32-sh.c, * elf32-sh64.c,
* elf32-sparc.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilegx.c,
* elf32-tilegx.h, * elf32-tilepro.c, * elf32-tilepro.h, * elf32-v850.c,
* elf32-vax.c, * elf32-wasm32.c, * elf32-xc16x.c, * elf32-xgate.c,
* elf32-xgate.h, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sh64.c, * elf64-sparc.c,
* elf64-tilegx.c, * elf64-tilegx.h, * elf64-x86-64.c, * elfcore.h,
* elflink.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c,
* elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-aarch64.h, * elfxx-ia64.c,
* elfxx-ia64.h, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * elfxx-x86.c, * elfxx-x86.h, * freebsd.h, * hash.c,
* host-aout.c, * hp300hpux.c, * hppabsd-core.c, * hpux-core.c,
* i386aout.c, * i386linux.c, * i386lynx.c, * i386mach3.c, * i386msdos.c,
* i386netbsd.c, * ieee.c, * ihex.c, * irix-core.c, * libaout.h,
* libbfd-in.h, * libbfd.c, * libcoff-in.h, * libnlm.h, * libpei.h,
* libxcoff.h, * linker.c, * lynx-core.c, * m68k4knetbsd.c,
* m68klinux.c, * m68knetbsd.c, * m88kmach3.c, * mach-o-aarch64.c,
* mach-o-arm.c, * mach-o-i386.c, * mach-o-target.c, * mach-o-x86-64.c,
* mach-o.c, * mach-o.h, * merge.c, * mipsbsd.c, * mmo.c, * netbsd.h,
* netbsd-core.c, * newsos3.c, * nlm-target.h, * nlm32-ppc.c,
* nlm32-sparc.c, * nlmcode.h, * ns32k.h, * ns32knetbsd.c, * oasys.c,
* opncls.c, * pc532-mach.c, * pdp11.c, * pe-arm.c, * pe-i386.c,
* pe-mcore.c, * pe-mips.c, * pe-x86_64.c, * peXXigen.c, * pef.c,
* pef.h, * pei-arm.c, * pei-i386.c, * pei-mcore.c, * pei-x86_64.c,
* peicode.h, * plugin.c, * ppcboot.c, * ptrace-core.c, * reloc.c,
* riscix.c, * rs6000-core.c, * section.c, * som.c, * som.h,
* sparclinux.c, * sparcnetbsd.c, * srec.c, * stabs.c, * sunos.c,
* syms.c, * targets.c, * tekhex.c, * trad-core.c, * vax1knetbsd.c,
* vaxnetbsd.c, * verilog.c, * versados.c, * vms-alpha.c, * vms-lib.c,
* vms-misc.c, * wasm-module.c, * wasm-module.h, * xcofflink.c,
* xsym.c, * xsym.h: Whitespace fixes.
* bfd-in2.h, * libbfd.h, * libcoff.h: Regenerate.
|
|
* elfxx-riscv.c (riscv_elf_add_sub_reloc): New function.
* (howto_table) [R_RISCV_ADD8]: Use riscv_elf_add_sub_reloc.
[R_RISCV_ADD16]: Likewise.
[R_RISCV_ADD32]: Likewise.
[R_RISCV_ADD64]: Likewise.
[R_RISCV_SUB6]: Likewise.
[R_RISCV_SUB8]: Likewise.
[R_RISCV_SUB16]: Likewise.
[R_RISCV_SUB32]: Likewise.
[R_RISCV_SUB64]: Likewise.
|
|
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
bfd/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elfnn-riscv.c (perform_relocation): Support the new
R_RISCV_32_PCREL relocation.
(riscv_elf_relocate_section): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
(riscv_reloc_map): Likewise.
* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
* libbfd.h: Regenerate.
gas/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
include/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elf/riscv.h (R_RISCV_32_PCREL): New.
|
|
|
|
Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them. This patch
significantly reworks how we handle linker relaxations:
* DWARF is now properly supported
* There is a ".option norelax" to disable relaxations, for when users
write assembly that can't be relaxed (if it's to be later patched up,
for example).
* There is an additional _RELAX relocation that specifies when previous
relocations can be relaxed.
We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).
Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!
include/
* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
(BFD_RELOC_RISCV_TPREL_S): Likewise.
(BFD_RELOC_RISCV_RELAX): Likewise.
(BFD_RELOC_RISCV_CFA): Likewise.
(BFD_RELOC_RISCV_SUB6): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET16): Likewise.
(BFD_RELOC_RISCV_SET32): Likewise.
* elfnn-riscv.c (perform_relocation): Handle the new
relocations.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Likewise.
(howto_table): Likewise.
(riscv_reloc_map): Likewise.
(relax_func_t): New type.
(_bfd_riscv_relax_call): Add reserve_size argument, which
controls the maximal offset pessimism. Correct type of max_alignment.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Compute the required reserve size
when relocating and use it to when calling relax_func.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
gas/
* config/tc-riscv.c (riscv_set_options): Add relax.
(riscv_opts): Likewise.
(s_riscv_option): Add relax and norelax.
(riscv_apply_const_reloc): New function.
(append_insn): Move constant relocation handling to
riscv_apply_const_reloc.
(md_pcrel_from): Likewise.
(parse_relocation): Skip BFD_RELOC_UNUSED.
(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
(md_apply_fix): Likewise.
(riscv_pre_output_hook): New function.
* config/tc-riscv.h (md_pre_output_hook): Define.
(riscv_pre_output_hook): Declare.
(DWARF_CIE_DATA_ALIGNMENT): Always -4.
|
|
This is a mixed bag of format changes:
* Replacing constants with macros (0xffffffff with MINUS_ONE, for
example). There's one technically functional change in here (some
MINUS_ONEs are changed to 0), but it only changes the behavior of an
otherwise-unused field.
* Using 0 instead of 0x0 in the relocation table.
* There were some missing spaces before parens, the spaces have been
added.
* A handful of comments are now more descriptive.
* A bunch of whitespace-only changes, mostly alignment and brace
newlines.
bfd/
* elfnn-riscv.c: Formatting and comment fixes throughout.
* elfxx-riscv.c: Likewise.
(howto_table): Change the src_mask field from MINUS_ONE to 0 for
R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
* riscv-opc.c: Formatting fixes.
gas/
* config/tc-riscv.c: Formatting and comment fixes throughout.
|
|
bfd/ChangeLog:
* bfd/elfxx-riscv.c (howto_table): Fix bitsize of R_RISCV_ADD8.
|
