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* elfxx-riscv.c (riscv_elf_add_sub_reloc): New function.
* (howto_table) [R_RISCV_ADD8]: Use riscv_elf_add_sub_reloc.
[R_RISCV_ADD16]: Likewise.
[R_RISCV_ADD32]: Likewise.
[R_RISCV_ADD64]: Likewise.
[R_RISCV_SUB6]: Likewise.
[R_RISCV_SUB8]: Likewise.
[R_RISCV_SUB16]: Likewise.
[R_RISCV_SUB32]: Likewise.
[R_RISCV_SUB64]: Likewise.
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The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
bfd/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elfnn-riscv.c (perform_relocation): Support the new
R_RISCV_32_PCREL relocation.
(riscv_elf_relocate_section): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
(riscv_reloc_map): Likewise.
* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
* libbfd.h: Regenerate.
gas/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
include/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elf/riscv.h (R_RISCV_32_PCREL): New.
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Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them. This patch
significantly reworks how we handle linker relaxations:
* DWARF is now properly supported
* There is a ".option norelax" to disable relaxations, for when users
write assembly that can't be relaxed (if it's to be later patched up,
for example).
* There is an additional _RELAX relocation that specifies when previous
relocations can be relaxed.
We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).
Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!
include/
* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
(BFD_RELOC_RISCV_TPREL_S): Likewise.
(BFD_RELOC_RISCV_RELAX): Likewise.
(BFD_RELOC_RISCV_CFA): Likewise.
(BFD_RELOC_RISCV_SUB6): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET16): Likewise.
(BFD_RELOC_RISCV_SET32): Likewise.
* elfnn-riscv.c (perform_relocation): Handle the new
relocations.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Likewise.
(howto_table): Likewise.
(riscv_reloc_map): Likewise.
(relax_func_t): New type.
(_bfd_riscv_relax_call): Add reserve_size argument, which
controls the maximal offset pessimism. Correct type of max_alignment.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Compute the required reserve size
when relocating and use it to when calling relax_func.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
gas/
* config/tc-riscv.c (riscv_set_options): Add relax.
(riscv_opts): Likewise.
(s_riscv_option): Add relax and norelax.
(riscv_apply_const_reloc): New function.
(append_insn): Move constant relocation handling to
riscv_apply_const_reloc.
(md_pcrel_from): Likewise.
(parse_relocation): Skip BFD_RELOC_UNUSED.
(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
(md_apply_fix): Likewise.
(riscv_pre_output_hook): New function.
* config/tc-riscv.h (md_pre_output_hook): Define.
(riscv_pre_output_hook): Declare.
(DWARF_CIE_DATA_ALIGNMENT): Always -4.
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This is a mixed bag of format changes:
* Replacing constants with macros (0xffffffff with MINUS_ONE, for
example). There's one technically functional change in here (some
MINUS_ONEs are changed to 0), but it only changes the behavior of an
otherwise-unused field.
* Using 0 instead of 0x0 in the relocation table.
* There were some missing spaces before parens, the spaces have been
added.
* A handful of comments are now more descriptive.
* A bunch of whitespace-only changes, mostly alignment and brace
newlines.
bfd/
* elfnn-riscv.c: Formatting and comment fixes throughout.
* elfxx-riscv.c: Likewise.
(howto_table): Change the src_mask field from MINUS_ONE to 0 for
R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
* riscv-opc.c: Formatting fixes.
gas/
* config/tc-riscv.c: Formatting and comment fixes throughout.
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bfd/ChangeLog:
* bfd/elfxx-riscv.c (howto_table): Fix bitsize of R_RISCV_ADD8.
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bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.
binutils* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.
gas * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.
ld * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this target.
* configure.tgt: Add riscv entries.
* emulparams/elf32lriscv-defs.sh: New file.
* emulparams/elf32lriscv.sh: New file.
* emulparams/elf64lriscv-defs.sh: New file.
* emulparams/elf64lriscv.sh: New file.
* emultempl/riscvelf.em: New file.
opcodes * configure.ac: Add entry for bfd_riscv_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add support for riscv.
(disassembler_usage): Likewise.
* riscv-dis.c: New file.
* riscv-opc.c: New file.
include * dis-asm.h: Add prototypes for print_insn_riscv and
print_riscv_disassembler_options.
* elf/riscv.h: New file.
* opcode/riscv-opc.h: New file.
* opcode/riscv.h: New file.
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