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Some early revisions of the Cortex-A53 have an erratum (843419). The
details of the erratum are quite complex and involve dynamic
conditions. For the purposes of the workaround we have simplified the
static conditions to an ADRP in the last two instructions of a 4KByte
page, followed within four instructions by a load/store dependent on
the ADRP.
This patch adds support to conservatively scan for and workaround
Cortex A53 erratum 843419. There are two different workaround
strategies used. The first is to rewrite ADRP instructions which form
part of an erratum sequence with an ADR instruction. In situations
where the ADR provides insufficient offset the dependent load or store
instruction from the sequence is moved to a stub section and branches
are inserted from the original sequence to the relocated instruction
and back again.
Stub section sizes are rounded up to a multiple of 4096 in order to
ensure that the act of inserting work around stubs does not create
more errata sequences.
Workaround stubs are always inserted into the stub section associated
with the input section containing the erratum sequence. This ensures
that the fully relocated form of the veneered load store instruction
is available at the point in time when the stub section is written.
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* elfxx-aarch64.c (stdarg.h): Include.
(string.h): Include.
(_bfd_aarch64_elf_grok_prstatus): Updated.
(_bfd_aarch64_elf_grok_psinfo): New function.
(_bfd_aarch64_elf_write_core_note): New function.
* elfxx-aarch64.h (elf_backend_grok_psinfo): Define.
(elf_backend_write_core_note): Define.
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bfd/
* Makefile.am (BFD64_BACKENDS): Add elfxx-aarch64.c.
(BFD64_BACKENDS_CFILES): Add elfxx-aarch64.lo.
* Makefile.in: Re-generated.
* configure.in (bfd_elf64_bigaarch64_vec): Add elfxx-aarch64.lo.
(bfd_elf64_littleaarch64_vec): Likewise.
(bfd_elf32_bigaarch64_vec): Likewise.
(bfd_elf32_littleaarch64_vec): Likewise.
* configure: Re-generated.
* elfxx-aarch64.c: New file; split from elf64-aarch64.c.
* elfxx-aarch64.h: New file.
* elfnn-aarch64.c: Include "elfxx-aarch64.h"; move the following
stuff to elfxx-aarch64.c.
(bfd_elf_aarch64_put_addend): Removed.
(PG_OFFSET, PG): Likewise.
(elfNN_aarch64_small_plt0_entry): Support ELF32.
(elfNN_aarch64_tlsdesc_small_plt_entry): Likewise.
(elf64_aarch64_grok_prstatus): Removed.
(elf_backend_grok_prstatus): Removed.
(insn32): Likewise.
(aarch64_unsigned_overflow): Likewise.
(aarch64_signed_overflow): Likewise.
(aarch64_resolve_relocation): Likewise.
(MASK): Likewise.
(decode_branch_ofs_26): Likewise.
(decode_cond_branch_ofs_19): Likewise.
(decode_ld_lit_ofs_19): Likewise.
(decode_tst_branch_ofs_14): Likewise.
(decode_movw_imm): Likewise.
(decode_adr_imm): Likewise.
(decode_add_imm): Likewise.
(reencode_branch_ofs_26): Likewise.
(reencode_cond_branch_ofs_19): Likewise.
(reencode_ld_lit_ofs_19): Likewise.
(reencode_tst_branch_ofs_14): Likewise.
(reencode_movw_imm): Likewise.
(reencode_adr_imm): Likewise.
(reencode_ldst_pos_imm): Likewise.
(reencode_add_imm): Likewise.
(reencode_movzn_to_movz): Likewise.
(reencode_movzn_to_movn): Likewise.
(aarch64_relocate): Update to call the new function names in
elfxx-aarch64.c.
(aarch64_calculate_got_entry_vma): Likewise.
(elfNN_aarch64_final_link_relocate): Likewise.
(elf64_aarch64_update_plt_entry): Likewise; change the type of the
parameter 'r_type' to bfd_reloc_code_real_type; rename to ...
(elf_aarch64_update_plt_entry): ... this.
(elfNN_aarch64_create_small_pltn_entry): Update.
(elfNN_aarch64_init_small_plt0_entry): Remove plt_got_base; add
bfd_vma plt_got_2nd_ent; update to call elf_aarch64_update_plt_entry.
(elfNN_aarch64_finish_dynamic_sections): Add plt_entry; update to
call elf_aarch64_update_plt_entry.
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