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This was originally reported by Hau Hsu <hau.hsu@sifive.com>.
Similar to commit 51a8a7c2e3cc0730831963651a55d23d1fae624d
We shouldn't use riscv_elf_append_rela to add dynamic relocs into .rela.iplt
in the riscv_elf_relocate_section when handling ifunc data reloc R_RISCV_32/64.
This just like what did in the riscv_elf_finish_dynamic_symbol.
bfd/
* elfnn-riscv.c (riscv_elf_relocate_section): We shouldn't use
riscv_elf_append_rela to add dynamic relocs into .rela.iplt in the
riscv_elf_relocate_section when handling ifunc data reloc.
ld/
* testsuite/ld-riscv-elf/ifunc-overwrite.s: Updated and renamed.
* testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-overwrite.d: Renamed.
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This was originally reported by Ard Biesheuvel <ardb@kernel.org>.
The followings are reproduce steps,
https://lore.kernel.org/all/202404260640.9GQVTmrw-lkp@intel.com/T/#u
The segment fault happens in the riscv_elf_finish_dynamic_sections when the
output got section is an ABS. Refer to MIPS code, they added an extra
bfd_is_abs_section check to avoid ABS got, so this seems the right and easier
way to go in the short-term.
bfd/
* elfnn-riscv.c (riscv_elf_finish_dynamic_sections): Set sh_entsize
and fill the got entries only when the got isn't an ABS section, and
the size of got is larger than zero. The similar goes for gotplt,
except we already reported error when the gotplt is an ABS.
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bfd/
PR 29823
* elfnn-riscv.c (riscv_elf_obj_attrs_handle_unknown): New function.
(elf_backend_obj_attrs_handle_unknown): Defined to
riscv_elf_obj_attrs_handle_unknown.
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This largely mechanical patch is preparation for a followup patch.
For quite some time I've thought that it would be useful to call
elf_backend_size_dynamic_sections even when no dynamic objects are
seen by the linker. That's what this patch does, with some renaming.
There are no functional changes to the linker, just a move of the
dynobj test in bfd_elf_size_dynamic_sections to target backend
functions, replacing the asserts/aborts already there. No doubt some
of the current always_size_sections functions could be moved to
size_dynamic_sections but I haven't made that change.
Because both hooks are now always called, I have renamed
always_size_sections to early_size_sections and size_dynamic_sections
to late_size_sections. I condisdered calling late_size_sections plain
size_sections, since this is the usual target dynamic section sizing
hook, but decided that searching the sources for "size_sections" would
then hit early_size_sections and other functions.
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Only relocation handling for now; relaxation is not implemented yet.
bfd/
* elfnn-riscv.c (riscv_elf_check_relocs): Record GOT reference and
paired relocation for TLSDESC_HI20.
(riscv_elf_adjust_dynamic_symbol): Allocate GOT and reloc slots for
TLSDESC symbols.
(riscv_elf_size_dynamic_sections): Likewise but for local symbols.
(tlsdescoff): New helper to determine static addend for R_TLSDESC.
(riscv_elf_relocate_section): Ignore TLSDESC_CALL reloc for now (it is
relaxation only).
Handle TLSDESC_{LOAD,ADD}_LO12 as paired pcrel relocs.
For TLS GOT slot generation, generalize the logic to handle any
combination of (GD, IE, TLSDESC).
Add TLSDESC Rela generation.
* ld/testsuite/ld-riscv-elf/tls*: Add TLSDESC instruction sequences
next to the existing GD and IE sequences. Update expectations.
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As the size calculation is split by global and local symbols, using a
shared constant definition for its size improves clarity.
bfd/
* elfnn-riscv.c: Add macros for sizes of a normal GOT entry, TLS GD and
TLS IE entry.
(allocate_dynrelocs): Replace GOT size expressions with the new
constants.
(riscv_elf_size_dynamic_sections): Likewise.
(riscv_elf_relocate_section): Likewise.
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The previous code did not account correctly for two cases:
* A TLS symbol can be referenced with multiple TLS types (although rare),
in which case it only allocated the maximum slot size among the types,
instead of the sum.
* TLS relocations are only needed for DLLs, unlike normal symbols which
requires relocations for all PIE code.
Modify the logic to account for the two cases, so this fixes the redundant
dynamic R_RISCV_NONE in .rela.dyn when using --no-pie for TLS GD and IE.
Passed the gcc/binutils regressions of riscv-gnu-toolchain.
bfd/
* elfnn-riscv.c (riscv_elf_size_dynamic_sections): Handle relocation
sizing for TLS and non-TLS symbols differently, with the former
requiring relocs on DLL while the latter requiring on PIE.
Allocate GOT slots and relocation slots for each TLS type separately,
accounting for the possibility of a TLS variable getting referenced by
multiple symbols.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/tls*: New testcase for TLS GD and IE, with
symbols referred by both types and global and local symbols.
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Returning false from elf_backend_finish_dynamic_symbol will not result
in an error being printed unless bfd_error is set but will result in
the linker exiting with a non-zero status. If just bfd_error is set
then a generic "final link failed" will result, which doesn't help a
user much. So elf_backend_finish_dynamic_symbol should print its own
error message whenever returning false, or use BFD_ASSERT or abort to
print assertion failures for conditions that shouldn't occur.
This patch does that, and removes unnecessary "htab != NULL" tests in
elf_backend_finish_dynamic_symbol. Such tests aren't needed in a
function only called via elf_backend_data.
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This fixes the ld "Handle no DWARF information" testcase. Which
currently fails on riscv because a local label name is assumed
to be the current function name.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_maybe_function_sym): Also check
_bfd_elf_is_local_label_name.
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Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
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* Problematic fix commit,
2029e13917d53d2289d3ebb390c4f40bd2112d21
RISC-V: Clarify the behaviors of SET/ADD/SUB relocations
* Bugzilla,
https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5
The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it
non-zero by accident in assembler before. This causes troubles by applying
the above commit, since the calculation is changed to support .reloc *SUB*
relocations with non-zero addend.
We encourage people to rebuild their stuff to get the non-zero addend of
SUB_ULEB128, but that might need some times, so report warnings to inform
people need to rebuild their stuff if --check-uleb128 is enabled.
Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use,
it may acceptable that stop supproting them until people rebuld their stuff,
maybe half-year or a year later. Or maybe we should teach people that don't
write the .reloc R_RISCV_SUB* with non-zero constant, and then report
warnings/errors in assembler.
bfd/
* elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of
R_RISCV_SUB_ULEB128.
(riscv_elf_relocate_section): Report warnings to inform people need
to rebuild their stuff if --check-uleb128 is enabled. So that can
get the right non-zero addend of R_RISCV_SUB_ULEB128.
* elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128.
ld/
* NEWS: Updated.
* emultempl/riscvelf.em: Added linker risc-v target options,
--[no-]check-uleb128, to enable/disable checking if the addend of
uleb128 is non-zero or not. So that people will know they need to
rebuild the objects with binutils 2.42 and up, to get the right zero
addend of SUB_ULEB128 relocation, or they may get troubles if using
.reloc.
* ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
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This was split over multiple lines and ended up missing a space.
Reported-by: David Abdurachmanov <davidlt@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Just the lightest modifications about this, without any further checks and
considering --emit-relocs. We will need to improve it in the future, but
first do this to avoid conflicts between linker internal relocations and the
new definition of psabi. For example, TLSDESC relocs.
Passed riscv-gnu-toolchain regressions, so should be safe enough to commit.
Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com>
bfd/
* reloc.c: Removed linker internal relocations.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elfnn-riscv.c: Defined R_RISCV_DELETE in include/elf/riscv.h.
* elfxx-riscv.c (howto_table, howto_table_internal): Moved linker
internal relocations from howto_table into howto_table_internal.
(riscv_reloc_map): Removed linker internal relocations mapping.
(riscv_elf_rtype_to_howto): Return howto of linker internal
relocations from howto_table_internal.
include/
* elf/riscv.h: Defined linker internal relocations after R_RISCV_max.
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We are used to generate these kinds of relocations by data directives.
Considering the following example,
.word (A + 3) - (B + 2)
The GAS will generate a pair of ADD/SUB for this,
R_RISCV_ADD, A + 1
R_RISCV_SUB, 0
The addend of R_RISCV_SUB will always be zero, and the summary of the
constants will be stored in the addend of R_RISCV_ADD/SET. Therefore,
we can always add the addend of these data relocations when doing relocations.
But unfortunately, I had heard that if we are using .reloc to generate
the data relocations will make the relocations failed. Refer to this,
.reloc offset, R_RISCV_ADD32, A + 3
.reloc offset, R_RISCV_SUB32, B + 2
.word 0
Then we can get the relocations as follows,
R_RISCV_ADD, A + 3
R_RISCV_SUB, B + 2
Then... Current LD does the relocation, B - A + 3 + 2, which is wrong
obviously...
So first of all, this patch fixes the wrong relocation behavior of
R_RISCV_SUB* relocations.
Afterwards, considering the uleb128 direcitve, we will get a pair of
SET_ULEB128/SUB_ULEB128 relocations for it for now,
.uleb128 (A + 3) - (B + 2)
R_RISCV_SET_ULEB128, A + 1
R_RISCV_SUB_ULEB128, B + 1
Which looks also wrong obviously, the summary of the constants should only
be stored into the addend of SET_ULEB128, and the addend of SUB_ULEB128 should
be zero like other SUB relocations. But the current LD will still get the right
relocation values since we only add the addend of SUB_ULEB128 by accident...
Anyway, this patch also fixes the behaviors above, to make sure that no matter
using .uleb128 or .reloc directives, we should always get the right values.
bfd/
* elfnn-riscv.c (perform_relocation): Clarify that SUB relocations
should substract the addend, rather than add.
(riscv_elf_relocate_section): Since SET_ULEB128 won't go into
perform_relocation, we should add it's addend here in advance.
gas/
* config/tc-riscv.c (riscv_insert_uleb128_fixes): Set the addend of
SUB_ULEB128 to zero since it should already be added into the addend
of SET_ULEB128.
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I get the following truncated errors recently when running riscv-gnu-toolchain
regressions,
/scratch/riscv-gnu-toolchain/regression/build/linux-rv32imafdc-ilp32d-medlow/build-glibc-linux-rv32imafdc-ilp32d/libc.a(libc-start.o): in function `elf_irela':
/scratch/riscv-gnu-toolchain/glibc/csu/../sysdeps/riscv/dl-irel.h:47:(.text+0x88): relocation truncated to fit: R_RISCV_GPREL_I against symbol `__ehdr_start' defined in .note.ABI-tag section in /scratch/riscv-gnu-toolchain/regression/build/linux-rv32imafdc-ilp32d-medlow/build-glibc-linux-rv32imafdc-ilp32d/elf/sln
The linker_def symbols like __ehdr_start that may be undefweak in early stages
of linking, including relax stage, but are guaranteed to be defined later.
Therefore, it seems like we shouldn't do the undefweak relaxations for these
kinds of symbols since they may be defined after relaxations.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_section): Don't do undefweak
relaxations for the linker_def symbols.
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A number of backends want to return bfd_reloc_dangerous messaqes from
relocation special_function, and construct the message using asprintf.
Such messages are not freed anywhere, leading to small memory leaks
inside libbfd. To limit the leaks, I'd implemented a static buffer in
the ppc backends that was freed before use in asprintf output. This
patch extends that scheme to other backends using a shared static
buffer and goes further in freeing the buffer on any bfd_close.
The patch also fixes a few other cases where asprintf output was not
freed after use.
bfd/
* bfd.c (_input_error_msg): Make global and rename to..
(_bfd_error_buf): ..this.
(bfd_asprintf): New function.
(bfd_errmsg): Use bfd_asprintf.
* opncls.c (bfd_close_all_done): Free _buf_error_buf.
* elf32-arm.c (find_thumb_glue, find_arm_glue): Use bfd_asprintf.
* elf32-nios2.c (nios2_elf32_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_unhandled_reloc): Likewise.
* elf64-ppc.c (ppc64_elf_unhandled_reloc): Likewise.
* elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Likewise.
(riscv_elf_relocate_section): Likewise.
* libbfd.h: Regenerate.
gas/
* read.c (read_end): Free current_name and current_label.
(do_s_func): Likewise on error path. strdup label.
ld/
* pe-dll.c (make_head, make_tail, make_one),
(make_singleton_name_thunk, make_import_fixup_entry),
(make_runtime_pseudo_reloc),
(pe_create_runtime_relocator_reference: Free oname after use.
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For TLS GD/IE, add the same condition with the relocate_section in the
allocate_dynrelocs, to make sure we won't reserve redundant spaces
for dynamic relocations since the conservative estimatation.
After applying this patch, ld seems no longer generate the spurious
R_RISCV_NONE for pr22263-1 test, and the test in pr24676.
bfd/
PR ld/22263
PR ld/24676
* elfnn-riscv.c (RISCV_TLS_GD_IE_NEED_DYN_RELOC): New defined.
Set NEED_RELOC to true if TLS GD/IE needs dynamic relocations,
and INDX will be the dynamic index.
(allocate_dynrelocs): Don't reserve extra spaces in the rela.got
if RISCV_TLS_GD_IE_NEED_DYN_RELOC set need_reloc to false. This
condition needs to be same as relocate_section.
(relocate_section): Likewise, use the same condition as
allocate_dynrelocs.
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Lots of targets already fixed the TEXTREL problem for TLS in PIE.
* For PR ld/25694,
In the check_reloc, refer to spare and loongarch, they don't need to reserve
any local dynamic reloc for TLS LE in pie/pde, and similar to other targets.
So it seems like riscv was too conservative to estimate the TLS LE before.
Just break and don't goto static_reloc for TLS LE in pie/pde can fix the
TEXTREL problem.
* For PR ld/22263,
The risc-v code for TLS GD/IE in the relocate_section seems same as MIPS port.
So similar to MIPS, pr22570, commits 9143e72c6d4d and 1cb83cac9a89, it seems
also the right way to do the same thing for risc-v.
On risc-v, fixes
FAIL: Build pr22263-1
RISC-V haven't supported the TLS transitions, so will need the same fix (use
bfd_link_dll) in the future.
bfd/
PR ld/22263
PR ld/25694
* elfnn-riscv.c (riscv_elf_check_relocs): Replace bfd_link_pic with
bfd_link_dll for TLS IE. Don't need to reserve the local dynamic
relocation for TLS LE in pie/pde, and report error in pic just like
before.
(riscv_elf_relocate_section): For TLS GD/IE, use bfd_link_dll rather
than !bfd_link_pic in determining the dynamic symbol index. Avoid
the index of -1.
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https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/96d6e190e9fc04a8517f9ff7fb9aed3e9876cbd6
There are some known limitations for now,
* Do not shrink the length of the uleb128 value, even if the value is reduced
after relaxations. Also reports error if the length grows up.
* The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the
R_RISCV_SUB_ULEB128.
bfd/
* bfd-in2.h: Regenerated.
* elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the
uleb128 value, and report error if the length grows up. Called the
generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128,
to encode the uleb128 into the section contents.
(riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128
must be paired with and be placed before the R_RISCV_SUB_ULEB128.
* elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128.
(riscv_reloc_map): Likewise.
(riscv_elf_ignore_reloc): New function.
* libbfd.h: Regenerated.
* reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128):
New relocations to support .uleb128 subtraction.
gas/
* config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128
and BFD_RELOC_RISCV_SUB_ULEB128.
(s_riscv_leb128): Updated to allow uleb128 subtraction.
(riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction
expressions and insert fixups for them.
(riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections.
include/
* elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction.
binutils/
* testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
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Let --no-relax-gp only disable the gp relaxation for lui and pcrel
relaxations, since x0 base and gp relaxations are different optimizations
in fact, but just use the same function to handle.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
set gp to zero when --no-relax-gp, then we should still keep the
x0 base relaxation.
(_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
--no-relax-gp, we will disable the gp relaxation in the
_bfd_riscv_relax_pc.
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bfd/
*elfnn-riscv.c (_bfd_riscv_relax_lui): For undefined weak symbol,
just relax the R_RISCV_LO12_I/S to R_RISCV_GPREL_I/S, and then don't
update the rs1 to zero until relocate_section.
(_bfd_riscv_relax_pc): Likewise, but for R_RISCV_PCREL_LO12_I/S.
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This should be the first related issue, which posted in riscv-gnu-toolchain,
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/497
If the output sections are not between gp and the symbol, then their alignments
shouldn't affect the gp relaxation. However, this patch improves this idea
even more, it limits the range to the gp+-2k, which means only the output
section which are in the [gp-2K, gp+2K) range need to be considered.
Even if the output section candidates may be different for each relax passes,
the symbol that can be relaxed ar this round will not be truncated at next
round. That is because this round you can do relaxation which means that the
section where the symbol is located is within the [gp-2K, gp+2K) range, so all
the output section alignments between them should be considered. In other
words, if the alignments between them may cause truncated, then we should
already preserve the size and won't do the gp relaxation this time.
This patch can resolve the github issue which mentioned above, and also passed
all gcc/binutils regressions of riscv-gnu-toolchain, so should be worth and
safe enough to commit.
Originally, this patch also do the same optimization for the call relaxations,
https://sourceware.org/pipermail/binutils/2022-October/123918.html
But just in case there is something that has not been considered, we only
deal with the gp relaxation at this time.
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Added new bfd_vma,
max_alignment_for_gp. It is used to record the maximum alignment of
the output sections, which are in the [gp-2K, gp+2k) range.
(riscv_elf_link_hash_table_create): Init max_alignment_for_gp to -1.
(_bfd_riscv_get_max_alignment): Added new parameter, gp. If gp is
zero, then all the output section alignments are possible candidates;
Otherwise, only the output sections which are in the [gp-2K, gp+2K)
range need to be considered.
(_bfd_riscv_relax_lui): Called _bfd_riscv_get_max_alignment with the
non-zero gp if the max_alignment_for_gp is -1.
(_bfd_riscv_relax_pc): Likewise.
(_bfd_riscv_relax_section): Record the first input section, so that
we can reset the max_alignment_for_gp for each repeated relax passes.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relax-max-align-gp.*: New testcase. It fails
without this patch.
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The non-preemptible SHN_ABS symbol with a pc-relative relocation should be
disallowed when generating shared object (pic and pie). Generally, the
following cases, which refer to pr25749, will cause a symbol be
non-preemptible,
* -pie, or -shared with -symbolic
* STV_HIDDEN, STV_INTERNAL, STV_PROTECTED
* Have dynamic symbol table, but without the symbol
* VER_NDX_LOCAL
However, PCREL_HI20/LO12 relocs are always bind locally when generating
shared object, so not only the non-preemptible absolute symbol need to
be disallowed, all absolute symbol references need but except that they
are defined in linker script. If we also disallow the absolute symbol
in linker script, then the glibc-linux toolchain build failed, so regard
them as pc-relative symbols, just like what x86 did.
Maybe we should add this check for all pc-relative relocations, rather
than just handle in R_RISCV_PCREL relocs. Ideally, since the value of
SHN_ABS symbol is a constant, only S - A relocations should be allowed
in the shared object, so only BFD_RELOC_8/16/32/64 are allowed, which
means R_RISCV_32/R_RISCV_64.
bfd/
PR 28789
* elfnn-riscv.c (riscv_elf_check_relocs): The absolute symbol cannot be
referneced with pc-relative relocation when generating shared object.
ld/
PR 28789
* ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* ld/testsuite/ld-riscv-elf/pcrel-reloc*: New testcases.
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There are two improvements, which are all referenced to aarch64,
* R_RISCV_32 with non ABS symbol cannot be used under RV64 when making
shard objects.
* Don't need dynamic relocation for R_RISCV_32/64 under RV32/RV64 when
making shared objects, if the referenced symbol is local ABS symbol.
However, considering this link,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/341
Seems like we should makes all R_RISCV_32/64 relocs with ABS symbol
that don't need any dynamic relocations when making the shared objects.
But anyway, I just sync the current behavior as aarch64 ld, in case
there are any unexpected behaviors happen.
Passed the gcc/binutils regressions in riscv-gnu-toolchain.
bfd/
* elfnn-riscv.c (riscv_elf_check_relocs): Only allow R_RISCV_32 with ABS
symbol under RV64.
(riscv_elf_relocate_section): R_RISCV_32/64 with local ABS symbol under
RV32/RV64 doesn't need any dynamic relocation when making shared objects.
I just make the implementations similar to other targets, so that will be
more easy to mainatain.
ld/
* testsuite/ld-riscv-elf/data-reloc*: New testcases.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added new data-reloc* testcases,
and need to make ifunc-seperate* testcases work for rv32.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-nonplt.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-plt.s: Likewise.
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These types of codes are different for each target, I am not sure what are the
best for RISC-V, so extract them out may be more easy to compare what's the
difference.
bfd/
* elfnn-riscv.c (RISCV_NEED_DYNAMIC_RELOC): New defined. Extracted
from riscv_elf_check_relocs, to see if dynamic reloc is needed for the
specific relocation.
(RISCV_GENERATE_DYNAMIC_RELOC): New defined. Extracted from
riscv_elf_relocate_section, to see if R_RISCV_32/64 need to generate
dynamic relocation.
(RISCV_COPY_INPUT_RELOC): New defined. Extracted from
riscv_elf_relocate_section, to see if R_RISCV_32/64 need to copy itslef
tp output file.
(RISCV_RESOLVED_LOCALLY): New defined. Extracted from
riscv_elf_relocate_section, to see if R_RISCV_GOT_HI20 can be resolved
locally.
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--relax enables all relaxations. --no-relax-gp disables GP relaxation to
allow measuring its effect.
The option can test effectiveness of GP relaxation and support some ABI
variants that use GP for other purposes.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/298
bfd/
* elfnn-riscv.c (struct riscv_elf_link_hash_table): Add params.
(riscv_elfNN_set_options): New.
(riscv_info_to_howto_rela): Check relax_gp.
(_bfd_riscv_relax_section): Likewise.
* elfxx-riscv.h (struct riscv_elf_params): New.
(riscv_elf32_set_options): New.
(riscv_elf64_set_options): New.
ld/
* emultempl/riscvelf.em: Add option parsing.
* testsuite/ld-riscv-elf/code-model-relax-medlow-01-norelaxgp.d: New.
* testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d: New.
* testsuite/ld-riscv-elf/pcgp-relax-02.d: Test --relax --relax-gp can be
used together.
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More places that generally expect instructions, so not zeros.
* coff-sh.c (sh_relax_section, sh_relax_delete_bytes): Exclude
sections without SEC_HAS_CONTENTS set.
* elf-m10200.c (mn10200_elf_relax_section): Likewise.
* elf32-arc.c (arc_elf_relax_section): Likewise.
* elf32-avr.c (elf32_avr_relax_section): Likewise.
* elf32-cr16.c (elf32_cr16_relax_section): Likewise.
* elf32-crx.c (elf32_crx_relax_section): Likewise.
* elf32-epiphany.c (epiphany_elf_relax_section): Likewise.
* elf32-ft32.c (ft32_elf_relax_section): Likewise.
* elf32-h8300.c (elf32_h8_relax_section): Likewise.
* elf32-ip2k.c (ip2k_elf_relax_section): Likewise.
* elf32-m32c.c (m32c_elf_relax_section): Likewise.
* elf32-m68hc11.c (m68hc11_elf_relax_section): Likewise.
* elf32-msp430.c (msp430_elf_relax_section): Likewise.
* elf32-pru.c (pru_elf32_relax_section): Likewise.
* elf32-rl78.c (rl78_elf_relax_section): Likewise.
* elf32-rx.c (elf32_rx_relax_section): Likewise.
* elf32-sh.c (sh_elf_relax_section): Likewise.
(sh_elf_relax_delete_bytes): Likewise.
* elf32-v850.c (v850_elf_relax_section): Likewise.
* elf64-alpha.c (elf64_alpha_relax_section): Likewise.
* elf64-ia64-vms.c (elf64_ia64_relax_section): Likewise.
* elfnn-ia64.c (elfNN_ia64_relax_section): Likewise.
* elfnn-riscv.c (_bfd_riscv_relax_section): Likewise.
* elfxx-mips.c (_bfd_mips_elf_relax_section): Likewise.
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Commit 43025f01a0c9 ("RISC-V: Improve link time complexity.") reduced the
time complexity of the linker relaxation but some code portions did not
reflect this change.
This commit fixes a comment describing each relaxation pass and reduces
actual number of passes for the RISC-V linker relaxation from 3 to 2.
Though it does not change the functionality, it marginally improves the
performance while linking large programs (with many relocations).
bfd/ChangeLog:
* elfnn-riscv.c (_bfd_riscv_relax_section): Fix a comment to
reflect current roles of each relaxation pass.
ld/ChangeLog:
* emultempl/riscvelf.em: Reduce the number of linker relaxation
passes from 3 to 2.
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The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
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Because riscv_merge_std_ext function did not merge the 'H' extension, linked
executables lacked 'H' extension when multiple objects are merged.
This issue is found while building OpenSBI with 'H' extension (resulting
ELF files did not contain "h1p0" in "Tag_RISCV_arch" even if *all* linked
object files contained it).
This commit adds 'h' to standard_exts variable to merge 'H' extension.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_merge_std_ext): Add 'H' extension merging.
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According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant
bits are valid, but since binutils implementation, we usually get 8 bits
field for it. That means, the high 2 bits could be other field and have
different purpose. Therefore, we should filter the 8 bits to 6 bits before
calculate, and then only encode the valid 6 bits back. By the way, we also
need the out-of-range check for R_RISCV_SUB6, and the overflow checks for
all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches.
Passing riscv-gnu-toolchain regressions.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
lower 6 bits as the significant bit.
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
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elfnn-riscv.c: In function ‘riscv_relax_resolve_delete_relocs’:
elfnn-riscv.c:4256:30: error: operand of ‘?:’ changes signedness from ‘int’ to ‘unsigned int’ due to unsignedness of other operand [-Werror=sign-compare]
So make the operands unsigned could resolve problem.
bfd/
* elfnn-riscv.c (riscv_relax_resolve_delete_relocs): Fixed build
failures for -Werror=sign-compare.
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The R_RISCV_DELETE relocations are no longer deleted at another relax pass,
so we should reset 'again' flag to true for _bfd_riscv_relax_pc, while the
deleted bytes are marked as R_RISCV_DELETE.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_pc): Set `again' to true while the
deleted bytes are marked as R_RISCV_DELETE.
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The riscv port does deletion and symbol table update for each relocation
while relaxing, so we are moving section bytes and scanning symbol table once
for each relocation. Compared to microblaze port, they record the relaxation
changes into a table, then do the deletion and symbol table update once per
section, rather than per relocation. Therefore, they should have better link
time complexity than us.
To improve the link time complexity, this patch try to make the deletion in
linear time. Compared to record the relaxation changes into a table, we
replace the unused relocation with R_RISCV_DELETE for the deleted bytes, and
then resolve them at the end of the section. Assuming the number of
R_RISCV_DELETE is m, and the number of symbols is n, the total link complexity
should be O(m) for moving section bytes, and O(m*n^2) for symbol table update.
If we record the relaxation changes into the table, and then sort the symbol
table by values, then probably can reduce the time complexity to O(m*n*log(n))
for updating symbol table, but it doesn't seem worth it for now.
bfd/
* elfnn-riscv.c (_riscv_relax_delete_bytes): Renamed from
riscv_relax_delete_bytes, updated to reduce the tiem complexity to O(m)
for memmove.
(typedef relax_delete_t): Function pointer declaration of delete functions.
(riscv_relax_delete_bytes): Can choose to use _riscv_relax_delete_piecewise
or _riscv_relax_delete_immediate for deletion.
(_riscv_relax_delete_piecewise): Just mark the deleted bytes as R_RISCV_DELETE.
(_riscv_relax_delete_immediate): Delete some bytes from a section while
relaxing.
(riscv_relax_resolve_delete_relocs): Delete the bytes for R_RISCV_DELETE
relocations from a section, at the end of _bfd_riscv_relax_section.
(_bfd_riscv_relax_call): Mark deleted bytes as R_RISCV_DELETE by reusing
R_RISCV_RELAX.
(_bfd_riscv_relax_lui): Likewise, but reuse R_RISCV_HI20 for lui, and reuse
R_RISCV_RELAX for c.lui.
(_bfd_riscv_relax_tls_le): Likewise, but resue R_RISCV_TPREL_HI20 and
R_RISCV_TPREL_ADD.
(_bfd_riscv_relax_pc): Likewise, but resue R_RISCV_PCREL_HI20 for auipc.
(_bfd_riscv_relax_align): Updated, don't need to resue relocation since
calling _riscv_relax_delete_immediate.
(_bfd_riscv_relax_delete): Removed.
(_bfd_riscv_relax_section): Set riscv_relax_delete_bytes for each relax_func,
to delete bytes immediately or later. Call riscv_relax_resolve_delete_relocs
to delete bytes for DELETE relocations from a section.
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This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
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R_RISCV_JAL.
When generating the shared object, the default visibility symbols may bind
externally, which means they will be exported to the dynamic symbol table,
and are preemptible by default. These symbols cannot be referenced by the
non-pic R_RISCV_JAL and R_RISCV_RVC_JUMP. However, consider that linker
may relax the R_RISCV_CALL relocations to R_RISCV_JAL or R_RISCV_RVC_JUMP,
if these relocations are relocated to the plt entries, then we won't report
error for them. Perhaps we also need the similar checks for the
R_RISCV_BRANCH and R_RISCV_RVC_BRANCH relocations.
After applying this patch, and revert the following glibc patch,
riscv: Fix incorrect jal with HIDDEN_JUMPTARGET
https://sourceware.org/git/?p=glibc.git;a=commit;h=68389203832ab39dd0dbaabbc4059e7fff51c29b
I get the expected errors as follows,
ld: relocation R_RISCV_RVC_JUMP against `__sigsetjmp' which may bind externally can not be used when making a shared object; recompile with -fPIC
ld: relocation R_RISCV_JAL against `exit' which may bind externally can not be used when making a shared object; recompile with -fPIC
Besides, we also have similar changes for libgcc,
RISC-V: jal cannot refer to a default visibility symbol for shared object
https://github.com/gcc-mirror/gcc/commit/45116f342057b7facecd3d05c2091ce3a77eda59
bfd/
pr 28509
* elfnn-riscv.c (riscv_elf_relocate_section): Report errors when
makeing a shard object, and the referenced symbols of R_RISCV_JAL
relocations are default visibility. Besides, we should handle most
of the cases here, so don't need the unresolvable check later for
R_RISCV_JAL and R_RISCV_RVC_JUMP.
ld/
pr 28509
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/lib-nopic-01a.s: Removed.
* testsuite/ld-riscv-elf/lib-nopic-01b.d: Likewise.
* testsuite/ld-riscv-elf/lib-nopic-01b.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-01.d: New testcase.
* testsuite/ld-riscv-elf/shared-lib-nopic-01.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-02.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-02.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-03.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-03.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-04.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-04.s: Likewise.
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They were legacy relocation types copied from other ports. The related
-fvtable-gc was removed from GCC in 2003.
The associated assembler directives (.vtable_inherit and .vtable_entry)
have never been supported by the RISC-V port. Remove related ld code.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
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The extension version checking logic is really just too complicated to
encode into the linker, trying to do so causes more harm than good.
This removes the checks and the associated tests, leaving the logic to
keep the largest version of each extension linked into the target.
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Rename to
riscv_update_subset_version, and stop reporting warnings on
version mismatches.
(riscv_merge_std_ext): Adjust calls to riscv_version_mismatch.
(riscv_merge_multi_letter_ext): Likewise.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Remove
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: New test.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p0.s:
Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p1.s:
Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Remove obselete
attr-merge-arch-failed-{01,02}, replace with
attr-merge-user-ext-01.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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This is the original discussion,
https://github.com/riscv/riscv-elf-psabi-doc/pull/190
And here is the glibc part,
https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html
For binutils part, we need to support a new direcitve: .variant_cc.
The function symbol marked by .variant_cc means it need to be resolved
directly without resolver for dynamic linker. We also add a new dynamic
entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the
special attribute in the dynamic symbol table of the object.
I heard that llvm already have supported this in their mainline, so
I think it's time to commit this.
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc
flag. It is used to check if relocations for variant CC symbols
may be present.
(allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC
flag, then raise the variant_cc flag of riscv_elf_link_hash_table.
(riscv_elf_size_dynamic_sections): Added dynamic entry for
variant_cc.
(riscv_elf_merge_symbol_attribute): New function, used to merge
non-visibility st_other attributes, including STO_RISCV_VARIANT_CC.
binutils/
* readelf.c (get_riscv_dynamic_type): New function.
(get_dynamic_type): Called get_riscv_dynamic_type for riscv targets.
(get_riscv_symbol_other): New function.
(get_symbol_other): Called get_riscv_symbol_other for riscv targets.
gas/
* config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a
variant CC convention.
(riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes,
but without copying st_other. If a function symbol has special st_other
value set via directives, then attaching an IFUNC resolver to that symbol
should not override the st_other setting.
(riscv_pseudo_table): Support variant_cc diretive.
* config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined.
* testsuite/gas/riscv/variant_cc-set.d: New testcase.
* testsuite/gas/riscv/variant_cc-set.s: Likewise.
* testsuite/gas/riscv/variant_cc.d: Likewise.
* testsuite/gas/riscv/variant_cc.s: Likewise.
include/
* elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1).
(STO_RISCV_VARIANT_CC): Defined to 0x80.
ld/
* testsuite/ld-riscv-elf/variant_cc-1.s: New testcase.
* testsuite/ld-riscv-elf/variant_cc-2.s: Likewise.
* testsuite/ld-riscv-elf/variant_cc-now.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-r.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string. This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed. Consider the following case,
nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add a0, a0, a0
.byte 0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 nop
8: 00000013 nop
c: 00000013 nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong. After
applying this patch, I get the following result,
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 .2byte 0x1
8: 00000013 nop
c: 00000013 nop
For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.
However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes. We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized. Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.
This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains. Also, tested by --enable-targets=all and can build
riscv-gdb successfully.
bfd/
* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
codes for riscv_parse_subset_t setting.
* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
(riscv_multi_subset_supports): Likewise.
* elfxx-riscv.h: Added extern for riscv_subset_supports and
riscv_multi_subset_supports.
gas/
* config/tc-riscv.c (riscv_subset_supports): Moved to
bfd/elfxx-riscv.c.
(riscv_multi_subset_supports): Likewise.
(riscv_rps_as): Defined for architectrue parser.
(riscv_set_arch): Updated.
(riscv_set_abi_by_arch): Likewise.
(riscv_csr_address): Likewise.
(reg_lookup_internal): Likewise.
(riscv_ip): Likewise.
(s_riscv_option): Updated.
* testsuite/gas/riscv/mapping-04b.d: Updated.
* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
* riscv-dis.c: Include elfxx-riscv.h since we need the
architecture parser. Also removed the cpu-riscv.h, it
is already included in elfxx-riscv.h.
(default_isa_spec): Defined since the parser need this
to set the default architecture string.
(xlen): Moved out from riscv_disassemble_insn as a global
variable, it is more convenient to initialize riscv_rps_dis.
(riscv_subsets): Defined to recoed the supported
extensions.
(riscv_rps_dis): Defined for architectrue parser.
(riscv_disassemble_insn): Call riscv_multi_subset_supports
to make sure if the instructions are valid or not.
(print_insn_riscv): Initialize the riscv_subsets by parsing
the elf architectrue attribute. Otherwise, set the default
architectrue string to rv64gc.
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Commit abd20cb637008da9d32018b4b03973e119388a0a and
ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional
complexity into the paths run by the RISC-V relaxation pass in order to
resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo
pairs. The first commit split up relaxation of these relocs into a pass
which occurred after other relaxations in order to prevent the situation
where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting
our ability to find the corresponding pcrel_hi relocation from the
address attached to the pcrel_lo.
Since the relaxation was split into two passes the 'again' parameter
could not be used to perform the entire relaxation process again and so
the second commit added a way to restart ldelf_map_segments, thus
starting the whole process again.
Unfortunately this process could not account for the fact that we were
not finished with the relaxation process so in some cases - such as the
case where code would not fit in a memory region before the
R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code
would fail.
This patch fixes all three of these concerns by reverting back to a
system of having only one target relax pass but updating entries in the
table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus
we can keep track of the pairs accurately, and we can use the 'again'
parameter to restart the entire target relax pass, behaving in the way
that generic code expects. Unfortunately we must still have an
additional pass to delay deleting AUIPC bytes to avoid ambiguity between
pcrel_hi relocs stored in the table after deletion. This pass can only
be run once so we may potentially miss out on relaxation opportunities
but this is likely to be rare.
https://sourceware.org/bugzilla/show_bug.cgi?id=28410
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax.
(riscv_elf_link_hash_table_create): Updated.
(riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs.
Update the pcgp_relocs table whenever bytes are deleted.
(riscv_update_pcgp_relocs): Add function to update the section
offset of pcrel_hi and pcrel_lo, and also update the symbol value
of pcrel_hi.
(_bfd_riscv_relax_call): Need to update the pcgp_relocs table
when deleting codes.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN,
we can't relax anything else, so set the sec->sec_flg0 to true.
Besides, we don't need to update the pcgp_relocs table at this
stage, so just pass NULL pointer as the pcgp_relocs table for
riscv_relax_delete_bytes.
(_bfd_riscv_relax_section): Use only one pass for all target
relaxations.
(_bfd_riscv_relax_delete): Likewise, we don't need to update
the pcgp_relocs table at this stage, and don't need to set
the `again' since restart_relax mechanism is abandoned.
(bfd_elfNN_riscv_restart_relax_sections): Removed.
(_bfd_riscv_relax_section): Updated.
* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed.
(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
* emultempl/riscvelf.em: Revert restart_relax changes and set
relax_pass to 3.
* testsuite/ld-riscv-elf/align-small-region.d: New testcase.
* testsuite/ld-riscv-elf/align-small-region.ld: Likewise.
* testsuite/ld-riscv-elf/align-small-region.s: Likewise.
* testsuite/ld-riscv-elf/restart-relax.d: Removed sine the
restart_relax mechanism is abandoned.
* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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There are two main reasons for this patch,
* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c. It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table. Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.
* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default. For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set. In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.
The elf/linux regression tests of riscv-gnu-toolchain are passed.
bfd/
* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
bfd/elfxx-riscv.h.
(riscv_merge_std_ext): Updated since the field of rpe is changed.
* elfxx-riscv.c (cpu-riscv.h): Removed.
(riscv_implicit_subsets): Added implicit extensions for g.
(struct riscv_supported_ext): Used to be riscv_ext_version. Moved
from gas/config/tc-riscv.c, and added new field `default_enable' to
decide if the extension should be enabled by default.
(EXT_DEFAULT): Defined for `default_enable' field.
(riscv_supported_std_ext): It used to return the supported standard
architecture string, but now we move ext_version_table from
gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
Currently we not only use the table to initialize riscv_ext_order, but
also get the default versions of extensions, and decide if the extensions
should be enbaled by default.
(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
(riscv_all_supported_ext): Includes all supported extension tables.
(riscv_known_prefixed_ext): Updated.
(riscv_valid_prefixed_ext): Updated.
(riscv_init_ext_order): Init the riscv_ext_order table according to
riscv_supported_std_ext.
(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
Get the versions of extensions from riscv_supported_std* tables.
(riscv_parse_add_subset): Updated.
(riscv_parse_std_ext): Updated.
(riscv_set_default_arch): Set the default subset list according to
the default_enable field of riscv_supported_*ext tables.
(riscv_parse_subset): If the input ARCH is NULL, then we call
riscv_set_default_arch to set the default subset list.
* elfxx-riscv.h (cpu-riscv.h): Included.
(riscv_parse_subset_t): Removed get_default_version field, and added
isa_spec field to replace it.
(extern riscv_supported_std_ext): Removed.
gas/
* (bfd/cpu-riscv.h): Removed.
(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
(ext_version_table): Likewise.
(riscv_get_default_ext_version): Likewise.
(ext_version_hash): Removed.
(init_ext_version_hash): Removed.
(riscv_set_arch): Updated since the field of rps is changed. Besides,
report error when the architecture string is empty.
(riscv_after_parse_args): Updated.
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Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions. The $d means
data, and the $x means instruction. Then the disassembler uses these
symbols to decide whether we should dump data or instruction.
Consider the mapping-04 test case,
$ cat tmp.s
.text
.option norelax
.option norvc
.fill 2, 4, 0x1001
.byte 1
.word 0
.balign 8
add a0, a0, a0
.fill 5, 2, 0x2002
add a1, a1, a1
.data
.word 0x1 # No need to add mapping symbols.
.word 0x2
$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o
Disassembly of section .text:
0000000000000000 <.text>:
0: 00001001 .word 0x00001001 # Marked $d, .fill directive.
4: 00001001 .word 0x00001001
8: 00000001 .word 0x00000001 # .byte + part of .word.
c: 00 .byte 0x00 # remaining .word.
d: 00 .byte 0x00 # Marked $d, odd byte of alignment.
e: 0001 nop # Marked $x, nops for alignment.
10: 00a50533 add a0,a0,a0
14: 20022002 .word 0x20022002 # Marked $d, .fill directive.
18: 20022002 .word 0x20022002
1c: 2002 .short 0x2002
1e: 00b585b3 add a1,a1,a1 # Marked $x.
22: 0001 nop # Section tail alignment.
24: 00000013 nop
* Use $d and $x to mark the distribution of data and instructions.
Alignments of code are recognized as instructions, since we usually
fill nops for them.
* If the alignment have odd bytes, then we cannot just fill the nops
into the spaces. We always fill an odd byte 0x00 at the start of
the spaces. Therefore, add a $d mapping symbol for the odd byte,
to tell disassembler that it isn't an instruction. The behavior
is same as Arm and Aarch64.
The elf/linux toolchain regressions all passed. Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too. Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.
bfd/
pr 27916
* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
symbols as a function name.
(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
pr 27916
* testsuite/binutils-all/readelf.s: Updated.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
pr 27916
* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
(riscv_mapping_state): Decide whether to create mapping symbol for
frag_now. Only add the mapping symbols to text sections.
(riscv_add_odd_padding_symbol): Add the mapping symbols for the
riscv_handle_align, which have odd bytes spaces.
(riscv_check_mapping_symbols): Remove any excess mapping symbols.
(md_assemble): Marked as MAP_INSN.
(riscv_frag_align_code): Marked as MAP_INSN.
(riscv_init_frag): Add mapping symbols for frag, it usually called
by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and
marked as MAP_INSN for rs_align_code.
(s_riscv_insn): Marked as MAP_INSN.
(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
with MAP_DATA.
(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
(TC_FRAG_TYPE): Record the first and last mapping symbols for the
fragments. The first mapping symbol must be placed at the start
of the fragment.
(TC_FRAG_INIT): Defined to riscv_init_frag.
* testsuite/gas/riscv/mapping-01.s: New testcase.
* testsuite/gas/riscv/mapping-01a.d: Likewise.
* testsuite/gas/riscv/mapping-01b.d: Likewise.
* testsuite/gas/riscv/mapping-02.s: Likewise.
* testsuite/gas/riscv/mapping-02a.d: Likewise.
* testsuite/gas/riscv/mapping-02b.d: Likewise.
* testsuite/gas/riscv/mapping-03.s: Likewise.
* testsuite/gas/riscv/mapping-03a.d: Likewise.
* testsuite/gas/riscv/mapping-03b.d: Likewise.
* testsuite/gas/riscv/mapping-04.s: Likewise.
* testsuite/gas/riscv/mapping-04a.d: Likewise.
* testsuite/gas/riscv/mapping-04b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
* testsuite/gas/riscv/no-relax-align.d: Updated.
* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
pr 27916
* opcode/riscv.h (enum riscv_seg_mstate): Added.
opcodes/
pr 27916
* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
Added to dump sections with mapping symbols.
(riscv_get_map_state): Get the mapping state from the symbol.
(riscv_search_mapping_symbol): Check the sorted symbol table, and
then find the suitable mapping symbol.
(riscv_data_length): Decide which data size we should print.
(riscv_disassemble_data): Dump the data contents.
(print_insn_riscv): Handle the mapping symbols.
(riscv_symbol_is_valid): Marked mapping symbols as invalid.
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the fix for PR22756 only changed behaviour for hidden aliases,
but the same situation exists for non-hidden aliases: sym_hashes[]
can contain multiple entries pointing to the same symbol structure
leading to relaxation adjustment to be applied twice.
Fix this by testing for duplicates for everything that looks like it
has a version.
PR ld/28021
bfd/
* elfnn-riscv.c (riscv_relax_delete_bytes): Check for any
versioning.
ld/
* testsuite/ld-riscv-elf/relax-twice.ver: New.
* testsuite/ld-riscv-elf/relax-twice-1.s: New.
* testsuite/ld-riscv-elf/relax-twice-2.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp
(run_relax_twice_test): New, and call it.
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ChangeLog:
bfd/
* elfnn-riscv.c(riscv_elf_additional_program_headers): Removed the
unused variable s.
(riscv_elf_modify_segment_map): Added ATTRIBUTE_UNUSED for the
unused parameter info.
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We added PT_RISCV_ATTRIBUTES to program header to make
.riscv.attribute easier to find in dynamic loader or kernel.
Ref:
https://github.com/riscv/riscv-elf-psabi-doc/pull/71
ChangeLog:
bfd/
* elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New.
(riscv_elf_additional_program_headers): Ditto.
(riscv_elf_modify_segment_map): Ditto.
(elf_backend_additional_program_headers): Ditto.
(elf_backend_modify_segment_map): Ditto.
(elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME
rather than string literal.
binutils/
* readelf.c(get_riscv_segment_type): New.
(get_segment_type): Handle EM_RISCV.
include/
* elf/riscv.h (PT_RISCV_ATTRIBUTES): New.
* testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes
section for simplify testcase.
* testsuite/ld-riscv-elf/attr-phdr.d: New.
* testsuite/ld-riscv-elf/attr-phdr.s: Ditto.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to
testcase.
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The original discussion was here,
https://github.com/riscv/riscv-elf-psabi-doc/issues/184
After discussing with Kito Cheng, I think the addends of %pcrel_hi
and %pcrel_lo are both allowed in GNU toolchain. However, both of
the them mean the offset of symbols, rather than the pc address.
But the addends of %got_pcrel_hi and it's %pcrel_lo do not look
reasonable. I believe gcc won't generate the got patterns with
addends, so linker should report dangerous relocation errors,
in case the assembly code use them.
Another issue was here,
https://sourceware.org/pipermail/binutils/2021-June/116983.html
At the beginnig, I suppose %pcrel_hi and %pcrel_lo are valid only
when they are in the same input section. But Jim Wilson points out
that gcc may generate %hi and %lo in the different input sections,
when -freorder-blocks-and-partition option is used. So that a memory
references for a loop may have the %hi outside the loop, but the %lo
remain in the loop. However, it is hard to create the testcases,
to see if %pcrel_hi and %pcrel_lo have the same behavior.
Unfortunately, I notice that the current pcrel resolver cannot
work for the above case. For now we build a hash table for pcrel
at the start of riscv_elf_relocate_section, and then free the hash
at the end. But riscv_elf_relocate_section only handles an input
section at a time, so that means we can only resolve the %pcrel_hi
and %pcrel_lo which are in the same input section. Otherwise, like
the above case, we will report "%pcrel_lo missing matching %pcrel_hi"
for them. I have no plan to improve this in the short-term, so maybe
we can wait until someone meets the problem before we deal with it.
bfd/
* elfnn-riscv.c (riscv_pcrel_hi_reloc): Added field to store
the original relocation type, in case the type is converted to
R_RISCV_HI20.
(riscv_pcrel_lo_reloc): Removed unused name field.
(riscv_pcrel_relocs): Added comments.
(riscv_zero_pcrel_hi_reloc): Removed unused input_bfd.
(riscv_record_pcrel_hi_reloc): Updated.
(riscv_record_pcrel_lo_reloc): Likewise.
(riscv_resolve_pcrel_lo_relocs): Likewise. Check the original
type of auipc, to make sure the %pcrel_lo without any addends.
Otherwise, report dangerous relocation error.
(riscv_elf_relocate_section): Updated above functions are changed.
For R_RISCV_GOT_HI20, report dangerous relocation error when addend
isn't zero.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d: New testcase.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d: New testcase.
Should report error since the %pcrel_lo with addend refers to
%got_pcrel_hi.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d: New testcase.
Should report error since the %got_pcrel_hi with addend.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld: Likewise.
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2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
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Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.
The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.
bfd/
* elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
* elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
prefixed extension name if check_unknown_prefixed_ext is false.
* elfnn-riscv.c (riscv_merge_arch_attr_info): Set
check_unknown_prefixed_ext to false for linker.
gas/
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
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