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elfnn-riscv.c: In function ‘riscv_relax_resolve_delete_relocs’:
elfnn-riscv.c:4256:30: error: operand of ‘?:’ changes signedness from ‘int’ to ‘unsigned int’ due to unsignedness of other operand [-Werror=sign-compare]
So make the operands unsigned could resolve problem.
bfd/
* elfnn-riscv.c (riscv_relax_resolve_delete_relocs): Fixed build
failures for -Werror=sign-compare.
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The R_RISCV_DELETE relocations are no longer deleted at another relax pass,
so we should reset 'again' flag to true for _bfd_riscv_relax_pc, while the
deleted bytes are marked as R_RISCV_DELETE.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_pc): Set `again' to true while the
deleted bytes are marked as R_RISCV_DELETE.
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The riscv port does deletion and symbol table update for each relocation
while relaxing, so we are moving section bytes and scanning symbol table once
for each relocation. Compared to microblaze port, they record the relaxation
changes into a table, then do the deletion and symbol table update once per
section, rather than per relocation. Therefore, they should have better link
time complexity than us.
To improve the link time complexity, this patch try to make the deletion in
linear time. Compared to record the relaxation changes into a table, we
replace the unused relocation with R_RISCV_DELETE for the deleted bytes, and
then resolve them at the end of the section. Assuming the number of
R_RISCV_DELETE is m, and the number of symbols is n, the total link complexity
should be O(m) for moving section bytes, and O(m*n^2) for symbol table update.
If we record the relaxation changes into the table, and then sort the symbol
table by values, then probably can reduce the time complexity to O(m*n*log(n))
for updating symbol table, but it doesn't seem worth it for now.
bfd/
* elfnn-riscv.c (_riscv_relax_delete_bytes): Renamed from
riscv_relax_delete_bytes, updated to reduce the tiem complexity to O(m)
for memmove.
(typedef relax_delete_t): Function pointer declaration of delete functions.
(riscv_relax_delete_bytes): Can choose to use _riscv_relax_delete_piecewise
or _riscv_relax_delete_immediate for deletion.
(_riscv_relax_delete_piecewise): Just mark the deleted bytes as R_RISCV_DELETE.
(_riscv_relax_delete_immediate): Delete some bytes from a section while
relaxing.
(riscv_relax_resolve_delete_relocs): Delete the bytes for R_RISCV_DELETE
relocations from a section, at the end of _bfd_riscv_relax_section.
(_bfd_riscv_relax_call): Mark deleted bytes as R_RISCV_DELETE by reusing
R_RISCV_RELAX.
(_bfd_riscv_relax_lui): Likewise, but reuse R_RISCV_HI20 for lui, and reuse
R_RISCV_RELAX for c.lui.
(_bfd_riscv_relax_tls_le): Likewise, but resue R_RISCV_TPREL_HI20 and
R_RISCV_TPREL_ADD.
(_bfd_riscv_relax_pc): Likewise, but resue R_RISCV_PCREL_HI20 for auipc.
(_bfd_riscv_relax_align): Updated, don't need to resue relocation since
calling _riscv_relax_delete_immediate.
(_bfd_riscv_relax_delete): Removed.
(_bfd_riscv_relax_section): Set riscv_relax_delete_bytes for each relax_func,
to delete bytes immediately or later. Call riscv_relax_resolve_delete_relocs
to delete bytes for DELETE relocations from a section.
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This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
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R_RISCV_JAL.
When generating the shared object, the default visibility symbols may bind
externally, which means they will be exported to the dynamic symbol table,
and are preemptible by default. These symbols cannot be referenced by the
non-pic R_RISCV_JAL and R_RISCV_RVC_JUMP. However, consider that linker
may relax the R_RISCV_CALL relocations to R_RISCV_JAL or R_RISCV_RVC_JUMP,
if these relocations are relocated to the plt entries, then we won't report
error for them. Perhaps we also need the similar checks for the
R_RISCV_BRANCH and R_RISCV_RVC_BRANCH relocations.
After applying this patch, and revert the following glibc patch,
riscv: Fix incorrect jal with HIDDEN_JUMPTARGET
https://sourceware.org/git/?p=glibc.git;a=commit;h=68389203832ab39dd0dbaabbc4059e7fff51c29b
I get the expected errors as follows,
ld: relocation R_RISCV_RVC_JUMP against `__sigsetjmp' which may bind externally can not be used when making a shared object; recompile with -fPIC
ld: relocation R_RISCV_JAL against `exit' which may bind externally can not be used when making a shared object; recompile with -fPIC
Besides, we also have similar changes for libgcc,
RISC-V: jal cannot refer to a default visibility symbol for shared object
https://github.com/gcc-mirror/gcc/commit/45116f342057b7facecd3d05c2091ce3a77eda59
bfd/
pr 28509
* elfnn-riscv.c (riscv_elf_relocate_section): Report errors when
makeing a shard object, and the referenced symbols of R_RISCV_JAL
relocations are default visibility. Besides, we should handle most
of the cases here, so don't need the unresolvable check later for
R_RISCV_JAL and R_RISCV_RVC_JUMP.
ld/
pr 28509
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/lib-nopic-01a.s: Removed.
* testsuite/ld-riscv-elf/lib-nopic-01b.d: Likewise.
* testsuite/ld-riscv-elf/lib-nopic-01b.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-01.d: New testcase.
* testsuite/ld-riscv-elf/shared-lib-nopic-01.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-02.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-02.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-03.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-03.s: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-04.d: Likewise.
* testsuite/ld-riscv-elf/shared-lib-nopic-04.s: Likewise.
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They were legacy relocation types copied from other ports. The related
-fvtable-gc was removed from GCC in 2003.
The associated assembler directives (.vtable_inherit and .vtable_entry)
have never been supported by the RISC-V port. Remove related ld code.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
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The extension version checking logic is really just too complicated to
encode into the linker, trying to do so causes more harm than good.
This removes the checks and the associated tests, leaving the logic to
keep the largest version of each extension linked into the target.
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Rename to
riscv_update_subset_version, and stop reporting warnings on
version mismatches.
(riscv_merge_std_ext): Adjust calls to riscv_version_mismatch.
(riscv_merge_multi_letter_ext): Likewise.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Remove
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: New test.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p0.s:
Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p1.s:
Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Remove obselete
attr-merge-arch-failed-{01,02}, replace with
attr-merge-user-ext-01.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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This is the original discussion,
https://github.com/riscv/riscv-elf-psabi-doc/pull/190
And here is the glibc part,
https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html
For binutils part, we need to support a new direcitve: .variant_cc.
The function symbol marked by .variant_cc means it need to be resolved
directly without resolver for dynamic linker. We also add a new dynamic
entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the
special attribute in the dynamic symbol table of the object.
I heard that llvm already have supported this in their mainline, so
I think it's time to commit this.
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc
flag. It is used to check if relocations for variant CC symbols
may be present.
(allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC
flag, then raise the variant_cc flag of riscv_elf_link_hash_table.
(riscv_elf_size_dynamic_sections): Added dynamic entry for
variant_cc.
(riscv_elf_merge_symbol_attribute): New function, used to merge
non-visibility st_other attributes, including STO_RISCV_VARIANT_CC.
binutils/
* readelf.c (get_riscv_dynamic_type): New function.
(get_dynamic_type): Called get_riscv_dynamic_type for riscv targets.
(get_riscv_symbol_other): New function.
(get_symbol_other): Called get_riscv_symbol_other for riscv targets.
gas/
* config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a
variant CC convention.
(riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes,
but without copying st_other. If a function symbol has special st_other
value set via directives, then attaching an IFUNC resolver to that symbol
should not override the st_other setting.
(riscv_pseudo_table): Support variant_cc diretive.
* config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined.
* testsuite/gas/riscv/variant_cc-set.d: New testcase.
* testsuite/gas/riscv/variant_cc-set.s: Likewise.
* testsuite/gas/riscv/variant_cc.d: Likewise.
* testsuite/gas/riscv/variant_cc.s: Likewise.
include/
* elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1).
(STO_RISCV_VARIANT_CC): Defined to 0x80.
ld/
* testsuite/ld-riscv-elf/variant_cc-1.s: New testcase.
* testsuite/ld-riscv-elf/variant_cc-2.s: Likewise.
* testsuite/ld-riscv-elf/variant_cc-now.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-r.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string. This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed. Consider the following case,
nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add a0, a0, a0
.byte 0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 nop
8: 00000013 nop
c: 00000013 nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong. After
applying this patch, I get the following result,
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 .2byte 0x1
8: 00000013 nop
c: 00000013 nop
For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.
However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes. We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized. Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.
This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains. Also, tested by --enable-targets=all and can build
riscv-gdb successfully.
bfd/
* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
codes for riscv_parse_subset_t setting.
* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
(riscv_multi_subset_supports): Likewise.
* elfxx-riscv.h: Added extern for riscv_subset_supports and
riscv_multi_subset_supports.
gas/
* config/tc-riscv.c (riscv_subset_supports): Moved to
bfd/elfxx-riscv.c.
(riscv_multi_subset_supports): Likewise.
(riscv_rps_as): Defined for architectrue parser.
(riscv_set_arch): Updated.
(riscv_set_abi_by_arch): Likewise.
(riscv_csr_address): Likewise.
(reg_lookup_internal): Likewise.
(riscv_ip): Likewise.
(s_riscv_option): Updated.
* testsuite/gas/riscv/mapping-04b.d: Updated.
* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
* riscv-dis.c: Include elfxx-riscv.h since we need the
architecture parser. Also removed the cpu-riscv.h, it
is already included in elfxx-riscv.h.
(default_isa_spec): Defined since the parser need this
to set the default architecture string.
(xlen): Moved out from riscv_disassemble_insn as a global
variable, it is more convenient to initialize riscv_rps_dis.
(riscv_subsets): Defined to recoed the supported
extensions.
(riscv_rps_dis): Defined for architectrue parser.
(riscv_disassemble_insn): Call riscv_multi_subset_supports
to make sure if the instructions are valid or not.
(print_insn_riscv): Initialize the riscv_subsets by parsing
the elf architectrue attribute. Otherwise, set the default
architectrue string to rv64gc.
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Commit abd20cb637008da9d32018b4b03973e119388a0a and
ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional
complexity into the paths run by the RISC-V relaxation pass in order to
resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo
pairs. The first commit split up relaxation of these relocs into a pass
which occurred after other relaxations in order to prevent the situation
where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting
our ability to find the corresponding pcrel_hi relocation from the
address attached to the pcrel_lo.
Since the relaxation was split into two passes the 'again' parameter
could not be used to perform the entire relaxation process again and so
the second commit added a way to restart ldelf_map_segments, thus
starting the whole process again.
Unfortunately this process could not account for the fact that we were
not finished with the relaxation process so in some cases - such as the
case where code would not fit in a memory region before the
R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code
would fail.
This patch fixes all three of these concerns by reverting back to a
system of having only one target relax pass but updating entries in the
table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus
we can keep track of the pairs accurately, and we can use the 'again'
parameter to restart the entire target relax pass, behaving in the way
that generic code expects. Unfortunately we must still have an
additional pass to delay deleting AUIPC bytes to avoid ambiguity between
pcrel_hi relocs stored in the table after deletion. This pass can only
be run once so we may potentially miss out on relaxation opportunities
but this is likely to be rare.
https://sourceware.org/bugzilla/show_bug.cgi?id=28410
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax.
(riscv_elf_link_hash_table_create): Updated.
(riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs.
Update the pcgp_relocs table whenever bytes are deleted.
(riscv_update_pcgp_relocs): Add function to update the section
offset of pcrel_hi and pcrel_lo, and also update the symbol value
of pcrel_hi.
(_bfd_riscv_relax_call): Need to update the pcgp_relocs table
when deleting codes.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN,
we can't relax anything else, so set the sec->sec_flg0 to true.
Besides, we don't need to update the pcgp_relocs table at this
stage, so just pass NULL pointer as the pcgp_relocs table for
riscv_relax_delete_bytes.
(_bfd_riscv_relax_section): Use only one pass for all target
relaxations.
(_bfd_riscv_relax_delete): Likewise, we don't need to update
the pcgp_relocs table at this stage, and don't need to set
the `again' since restart_relax mechanism is abandoned.
(bfd_elfNN_riscv_restart_relax_sections): Removed.
(_bfd_riscv_relax_section): Updated.
* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed.
(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
* emultempl/riscvelf.em: Revert restart_relax changes and set
relax_pass to 3.
* testsuite/ld-riscv-elf/align-small-region.d: New testcase.
* testsuite/ld-riscv-elf/align-small-region.ld: Likewise.
* testsuite/ld-riscv-elf/align-small-region.s: Likewise.
* testsuite/ld-riscv-elf/restart-relax.d: Removed sine the
restart_relax mechanism is abandoned.
* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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There are two main reasons for this patch,
* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c. It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table. Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.
* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default. For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set. In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.
The elf/linux regression tests of riscv-gnu-toolchain are passed.
bfd/
* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
bfd/elfxx-riscv.h.
(riscv_merge_std_ext): Updated since the field of rpe is changed.
* elfxx-riscv.c (cpu-riscv.h): Removed.
(riscv_implicit_subsets): Added implicit extensions for g.
(struct riscv_supported_ext): Used to be riscv_ext_version. Moved
from gas/config/tc-riscv.c, and added new field `default_enable' to
decide if the extension should be enabled by default.
(EXT_DEFAULT): Defined for `default_enable' field.
(riscv_supported_std_ext): It used to return the supported standard
architecture string, but now we move ext_version_table from
gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
Currently we not only use the table to initialize riscv_ext_order, but
also get the default versions of extensions, and decide if the extensions
should be enbaled by default.
(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
(riscv_all_supported_ext): Includes all supported extension tables.
(riscv_known_prefixed_ext): Updated.
(riscv_valid_prefixed_ext): Updated.
(riscv_init_ext_order): Init the riscv_ext_order table according to
riscv_supported_std_ext.
(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
Get the versions of extensions from riscv_supported_std* tables.
(riscv_parse_add_subset): Updated.
(riscv_parse_std_ext): Updated.
(riscv_set_default_arch): Set the default subset list according to
the default_enable field of riscv_supported_*ext tables.
(riscv_parse_subset): If the input ARCH is NULL, then we call
riscv_set_default_arch to set the default subset list.
* elfxx-riscv.h (cpu-riscv.h): Included.
(riscv_parse_subset_t): Removed get_default_version field, and added
isa_spec field to replace it.
(extern riscv_supported_std_ext): Removed.
gas/
* (bfd/cpu-riscv.h): Removed.
(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
(ext_version_table): Likewise.
(riscv_get_default_ext_version): Likewise.
(ext_version_hash): Removed.
(init_ext_version_hash): Removed.
(riscv_set_arch): Updated since the field of rps is changed. Besides,
report error when the architecture string is empty.
(riscv_after_parse_args): Updated.
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Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions. The $d means
data, and the $x means instruction. Then the disassembler uses these
symbols to decide whether we should dump data or instruction.
Consider the mapping-04 test case,
$ cat tmp.s
.text
.option norelax
.option norvc
.fill 2, 4, 0x1001
.byte 1
.word 0
.balign 8
add a0, a0, a0
.fill 5, 2, 0x2002
add a1, a1, a1
.data
.word 0x1 # No need to add mapping symbols.
.word 0x2
$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o
Disassembly of section .text:
0000000000000000 <.text>:
0: 00001001 .word 0x00001001 # Marked $d, .fill directive.
4: 00001001 .word 0x00001001
8: 00000001 .word 0x00000001 # .byte + part of .word.
c: 00 .byte 0x00 # remaining .word.
d: 00 .byte 0x00 # Marked $d, odd byte of alignment.
e: 0001 nop # Marked $x, nops for alignment.
10: 00a50533 add a0,a0,a0
14: 20022002 .word 0x20022002 # Marked $d, .fill directive.
18: 20022002 .word 0x20022002
1c: 2002 .short 0x2002
1e: 00b585b3 add a1,a1,a1 # Marked $x.
22: 0001 nop # Section tail alignment.
24: 00000013 nop
* Use $d and $x to mark the distribution of data and instructions.
Alignments of code are recognized as instructions, since we usually
fill nops for them.
* If the alignment have odd bytes, then we cannot just fill the nops
into the spaces. We always fill an odd byte 0x00 at the start of
the spaces. Therefore, add a $d mapping symbol for the odd byte,
to tell disassembler that it isn't an instruction. The behavior
is same as Arm and Aarch64.
The elf/linux toolchain regressions all passed. Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too. Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.
bfd/
pr 27916
* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
symbols as a function name.
(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
pr 27916
* testsuite/binutils-all/readelf.s: Updated.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
pr 27916
* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
(riscv_mapping_state): Decide whether to create mapping symbol for
frag_now. Only add the mapping symbols to text sections.
(riscv_add_odd_padding_symbol): Add the mapping symbols for the
riscv_handle_align, which have odd bytes spaces.
(riscv_check_mapping_symbols): Remove any excess mapping symbols.
(md_assemble): Marked as MAP_INSN.
(riscv_frag_align_code): Marked as MAP_INSN.
(riscv_init_frag): Add mapping symbols for frag, it usually called
by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and
marked as MAP_INSN for rs_align_code.
(s_riscv_insn): Marked as MAP_INSN.
(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
with MAP_DATA.
(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
(TC_FRAG_TYPE): Record the first and last mapping symbols for the
fragments. The first mapping symbol must be placed at the start
of the fragment.
(TC_FRAG_INIT): Defined to riscv_init_frag.
* testsuite/gas/riscv/mapping-01.s: New testcase.
* testsuite/gas/riscv/mapping-01a.d: Likewise.
* testsuite/gas/riscv/mapping-01b.d: Likewise.
* testsuite/gas/riscv/mapping-02.s: Likewise.
* testsuite/gas/riscv/mapping-02a.d: Likewise.
* testsuite/gas/riscv/mapping-02b.d: Likewise.
* testsuite/gas/riscv/mapping-03.s: Likewise.
* testsuite/gas/riscv/mapping-03a.d: Likewise.
* testsuite/gas/riscv/mapping-03b.d: Likewise.
* testsuite/gas/riscv/mapping-04.s: Likewise.
* testsuite/gas/riscv/mapping-04a.d: Likewise.
* testsuite/gas/riscv/mapping-04b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
* testsuite/gas/riscv/no-relax-align.d: Updated.
* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
pr 27916
* opcode/riscv.h (enum riscv_seg_mstate): Added.
opcodes/
pr 27916
* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
Added to dump sections with mapping symbols.
(riscv_get_map_state): Get the mapping state from the symbol.
(riscv_search_mapping_symbol): Check the sorted symbol table, and
then find the suitable mapping symbol.
(riscv_data_length): Decide which data size we should print.
(riscv_disassemble_data): Dump the data contents.
(print_insn_riscv): Handle the mapping symbols.
(riscv_symbol_is_valid): Marked mapping symbols as invalid.
|
|
the fix for PR22756 only changed behaviour for hidden aliases,
but the same situation exists for non-hidden aliases: sym_hashes[]
can contain multiple entries pointing to the same symbol structure
leading to relaxation adjustment to be applied twice.
Fix this by testing for duplicates for everything that looks like it
has a version.
PR ld/28021
bfd/
* elfnn-riscv.c (riscv_relax_delete_bytes): Check for any
versioning.
ld/
* testsuite/ld-riscv-elf/relax-twice.ver: New.
* testsuite/ld-riscv-elf/relax-twice-1.s: New.
* testsuite/ld-riscv-elf/relax-twice-2.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp
(run_relax_twice_test): New, and call it.
|
|
ChangeLog:
bfd/
* elfnn-riscv.c(riscv_elf_additional_program_headers): Removed the
unused variable s.
(riscv_elf_modify_segment_map): Added ATTRIBUTE_UNUSED for the
unused parameter info.
|
|
We added PT_RISCV_ATTRIBUTES to program header to make
.riscv.attribute easier to find in dynamic loader or kernel.
Ref:
https://github.com/riscv/riscv-elf-psabi-doc/pull/71
ChangeLog:
bfd/
* elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New.
(riscv_elf_additional_program_headers): Ditto.
(riscv_elf_modify_segment_map): Ditto.
(elf_backend_additional_program_headers): Ditto.
(elf_backend_modify_segment_map): Ditto.
(elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME
rather than string literal.
binutils/
* readelf.c(get_riscv_segment_type): New.
(get_segment_type): Handle EM_RISCV.
include/
* elf/riscv.h (PT_RISCV_ATTRIBUTES): New.
* testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes
section for simplify testcase.
* testsuite/ld-riscv-elf/attr-phdr.d: New.
* testsuite/ld-riscv-elf/attr-phdr.s: Ditto.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to
testcase.
|
|
The original discussion was here,
https://github.com/riscv/riscv-elf-psabi-doc/issues/184
After discussing with Kito Cheng, I think the addends of %pcrel_hi
and %pcrel_lo are both allowed in GNU toolchain. However, both of
the them mean the offset of symbols, rather than the pc address.
But the addends of %got_pcrel_hi and it's %pcrel_lo do not look
reasonable. I believe gcc won't generate the got patterns with
addends, so linker should report dangerous relocation errors,
in case the assembly code use them.
Another issue was here,
https://sourceware.org/pipermail/binutils/2021-June/116983.html
At the beginnig, I suppose %pcrel_hi and %pcrel_lo are valid only
when they are in the same input section. But Jim Wilson points out
that gcc may generate %hi and %lo in the different input sections,
when -freorder-blocks-and-partition option is used. So that a memory
references for a loop may have the %hi outside the loop, but the %lo
remain in the loop. However, it is hard to create the testcases,
to see if %pcrel_hi and %pcrel_lo have the same behavior.
Unfortunately, I notice that the current pcrel resolver cannot
work for the above case. For now we build a hash table for pcrel
at the start of riscv_elf_relocate_section, and then free the hash
at the end. But riscv_elf_relocate_section only handles an input
section at a time, so that means we can only resolve the %pcrel_hi
and %pcrel_lo which are in the same input section. Otherwise, like
the above case, we will report "%pcrel_lo missing matching %pcrel_hi"
for them. I have no plan to improve this in the short-term, so maybe
we can wait until someone meets the problem before we deal with it.
bfd/
* elfnn-riscv.c (riscv_pcrel_hi_reloc): Added field to store
the original relocation type, in case the type is converted to
R_RISCV_HI20.
(riscv_pcrel_lo_reloc): Removed unused name field.
(riscv_pcrel_relocs): Added comments.
(riscv_zero_pcrel_hi_reloc): Removed unused input_bfd.
(riscv_record_pcrel_hi_reloc): Updated.
(riscv_record_pcrel_lo_reloc): Likewise.
(riscv_resolve_pcrel_lo_relocs): Likewise. Check the original
type of auipc, to make sure the %pcrel_lo without any addends.
Otherwise, report dangerous relocation error.
(riscv_elf_relocate_section): Updated above functions are changed.
For R_RISCV_GOT_HI20, report dangerous relocation error when addend
isn't zero.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d: New testcase.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d: New testcase.
Should report error since the %pcrel_lo with addend refers to
%got_pcrel_hi.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d: New testcase.
Should report error since the %got_pcrel_hi with addend.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld: Likewise.
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|
2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
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|
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.
The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.
bfd/
* elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
* elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
prefixed extension name if check_unknown_prefixed_ext is false.
* elfnn-riscv.c (riscv_merge_arch_attr_info): Set
check_unknown_prefixed_ext to false for linker.
gas/
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
|
|
The %pcrel_lo addend may causes the overflow, and need more than one
%pcrel_hi values. But there may be only one auipc, shared by those
%pcrel_lo with addends. However, the existing check method in the
riscv_resolve_pcrel_lo_relocs, may not be able to work for some
special/corner cases.
Consider the testcases pcrel-lo-addend-2b. Before applying this patch,
I can compile it successfully. But in fact the addend cause the value
of %pcrel_hi to be different. This patch try to check the value of
%pcrel_hi directly, to make sure it won't be changed. Otherwise, linker
will report the following errors,
(.text+0xa): dangerous relocation: %pcrel_lo overflow with an addend,
the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000
after adding the %pcrel_lo addend
The toolchain regressions, rv64gc-linux/rv64gc-elf/rv32gc-linux/rv32i-elf,
pass expectedly and looks fine.
bfd/
* elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Check the values
of %pcrel_hi, before and after adding the addend. Make sure the
value won't be changed, otherwise, report dangerous error.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d: Renamed from
pcrel-lo-addend-2.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d: New testcase.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s: Likewise.
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|
The local ".L0" symbol are usually generated to mark where the
auipc instruction is, and clang also uses ".LBB" to do the same
thing. Besides, clang also uses the empty name symbols for label
differences. Arm surpress their mapping symbols by regarding them
as special symbols, and MIPS surpress all local symbols. Therefore,
RISC-V probably need to surpress the local and empty name symbols
for nm and related tools. User can use "--special-syms" to show
these surpressed symbols.
bfd/
PR27584
* elfnn-riscv.c (riscv_elf_is_target_special_symbol): Added to
omit local and empty symbols since they usually generated to
mark the auipc instructions.
|
|
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Do not report the warning
when the version of input or output is RISCV_UNKNOWN_VERSION, since
the extension is added implicitly.
* elfxx-riscv.c: Updated the obsolete comments.
(RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h.
* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
|
|
Certain library headers and functions are required by C99. This
removes configure tests for them. The patch also removes AC_ISC_POSIX
and AC_HEADER_DIRENT, which the autoconf manual states are obsolescent.
sys/time.h is no longer tangled up with time.h so it can be handled by
the gprof configure.
* configure.ac: Don't check for long long or long double type.
Don't check for alloca.h, limits.h, stddef.h, stdlib.h, string.h,
strings.h, time.h, wchar.h, wctype.h or sys/time.h. Don't check
for strtoull, free, malloc, realloc, getenv, strstr, snprintf,
vsnprintf, strlen or setitimer. Sort AC_CHECK_DECLS.
(AC_ISC_POSIX): Don't invoke.
(AC_HEADER_TIME, AC_HEADER_DIRENT, ACX_HEADER_STRING): Likewise.
* sysdep.h: Remove many HAVE_*_H checks and fallback declarations.
Do test HAVE_SYS_TYPES_H. Don't include sys/time.h. Reorder
header order as per automake AC_INCLUDES_DEFAULT.
* bfd-in.h: Include inttypes.h unconditionally.
* bfd.c (_bfd_doprnt, _bfd_doprnt_scan): Assume long long and
long double are available.
(bfd_scan_vma): Assume long long and strtoull are available.
* elflink.c: Include limits.h unconditionally.
* elfnn-riscv.c: Likewise.
* wasm-module.c: Likewise.
* hpux-core.c: Include dirent.h unconditionally.
* trad-core.c: Likewise.
* hosts/x86-64linux.h: Include stdlib.h unconditionally.
* peXXigen.c: Remove HAVE_WCHAR_H and HAVE_WCTYPE_H checks.
* elf32-m68hc1x.c: Don't include alloca-conf.h.
* elf64-hppa.c: Likewise.
* som.c: Likewise.
* wasm-module.c: Likewise.
* xsym.c: Likewise.
* bfd-in2.h: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
|
|
bfd/ChangeLog:
* elf-bfd.h (bfd_section_is_ctf): Use startswith function.
* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
(elf_get_reloc_section): Likewise.
* elf32-arc.c (elf_arc_size_dynamic_sections): Likewise.
* elf32-m32r.c (m32r_elf_section_flags): Likewise.
* elf32-microblaze.c (microblaze_elf_size_dynamic_sections): Likewise.
* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
(nds32_elf_relocate_section): Likewise.
(nds32_elf_action_discarded): Likewise.
(nds32_elf_check_relocs): Likewise.
(nds32_elf_section_flags): Likewise.
* elf32-or1k.c (or1k_elf_check_relocs): Likewise.
* elf32-ppc.c (ppc_elf_section_from_shdr): Likewise.
* elf32-rx.c (rx_table_find): Likewise.
(rx_table_map): Likewise.
* elf32-spu.c (spu_elf_backend_symbol_processing): Likewise.
(spu_elf_find_overlays): Likewise.
(needs_ovl_stub): Likewise.
(allocate_spuear_stubs): Likewise.
(build_spuear_stubs): Likewise.
(mark_overlay_section): Likewise.
(spu_elf_auto_overlay): Likewise.
(spu_elf_output_symbol_hook): Likewise.
* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
* elf32-xtensa.c (xtensa_property_section_name): Likewise.
* elf64-ppc.c (ppc64_elf_section_flags): Likewise.
(ppc64_elf_relocate_section): Likewise.
* elflink.c (resolve_section): Likewise.
(UNARY_OP): Likewise.
(BINARY_OP_HEAD): Likewise.
(elf_link_input_bfd): Likewise.
* elfnn-riscv.c (riscv_elf_size_dynamic_sections): Likewise.
* elfxx-riscv.c (riscv_parse_subset): Likewise.
* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
* opncls.c (get_build_id): Likewise.
binutils/ChangeLog:
* dllwrap.c: Use startswith function.
* objcopy.c (is_dwo_section): Likewise.
(handle_remove_section_option): Likewise.
(copy_main): Likewise.
* objdump.c (is_significant_symbol_name): Likewise.
|
|
* sysdep.h: POISON_BFD_BOOLEAN: Define.
* aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h,
* aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c,
* bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c,
* coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c,
* coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c,
* coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c,
* coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
* coffcode.h, * coffgen.c, * cofflink.c, * compress.c,
* corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c,
* cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c,
* cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c,
* cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c,
* cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c,
* cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c,
* cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c,
* cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c,
* cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c,
* cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c,
* cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c,
* cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c,
* cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c,
* cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c,
* cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c,
* cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c,
* cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c,
* cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c,
* cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c,
* cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c,
* cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c,
* dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c,
* elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c,
* elf-nacl.h, * elf-properties.c, * elf-s390-common.c,
* elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h,
* elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c,
* elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c,
* elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c,
* elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c,
* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
* elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
* elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c,
* elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
* elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c,
* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
* elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c,
* elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h,
* elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h,
* elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h,
* elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
* elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c,
* elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c,
* elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c,
* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
* elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c,
* elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h,
* elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c,
* elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c,
* elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h,
* elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h,
* elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h,
* elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h,
* format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c,
* i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h,
* libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h,
* libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c,
* mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h,
* merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c,
* pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c,
* pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c,
* pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c,
* peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c,
* reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c,
* som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c,
* verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h,
* wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c,
* xsym.h: Replace bfd_boolean with bool, FALSE with false, and
TRUE with true throughout.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* libcoff.h: Regenerate.
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|
Correct return type of callbacks invoked by htab_traverse and other
hashtab.h functions to int, and one case of a callback invoked by
elf_link_hash_traverse to bfd_boolean.
* elf32-i386.c (elf_i386_finish_local_dynamic_symbol): Return int.
* elf64-ia64-vms.c (elf64_ia64_local_dyn_info_free): Likewise.
(elf64_ia64_local_dyn_sym_thunk): Likewise.
* elf64-x86-64.c (elf_x86_64_finish_local_dynamic_symbol): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_allocate_local_ifunc_dynrelocs),
(elfNN_aarch64_finish_local_dynamic_symbol): Likewise.
* elfnn-ia64.c (elfNN_ia64_local_dyn_info_free): Likewise.
(elfNN_ia64_local_dyn_sym_thunk): Likewise.
* elfnn-riscv.c (allocate_local_ifunc_dynrelocs): Likewise.
(riscv_pcrel_reloc_eq): Likewise.
(riscv_elf_finish_local_dynamic_symbol): Likewise.
* elfxx-sparc.c (allocate_local_dynrelocs): Likewise.
(finish_local_dynamic_symbol): Likewise.
* elfxx-x86.c (elf_x86_allocate_local_dynreloc): Likewise.
* elfxx-mips.c (mips_elf_resolve_got_page_ref): Likewise.
(mips_elf_count_got_symbols): Change return type to bfd_boolean.
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|
This functions was changed to return an int in commit ece5ef60797f but
since bfd_boolean was an int typedef I lazily left all the ELF
relocate_section functions as returning bfd_boolean, except the SPU
one. In order to use _Bool or bool in place of bfd_boolean we need to
be fussy about the return types.
* elf-m10200.c (mn10200_elf_relocate_section): Return int.
* elf-m10300.c (mn10300_elf_relocate_section): Likewise.
* elf32-arc.c (elf_arc_relocate_section): Likewise.
* elf32-arm.c (elf32_arm_relocate_section): Likewise.
* elf32-avr.c (elf32_avr_relocate_section): Likewise.
* elf32-bfin.c (bfin_relocate_section): Likewise.
(bfinfdpic_relocate_section): Likewise.
* elf32-cr16.c (elf32_cr16_relocate_section): Likewise.
* elf32-cris.c (cris_elf_relocate_section): Likewise.
* elf32-crx.c (elf32_crx_relocate_section): Likewise.
* elf32-csky.c (csky_elf_relocate_section): Likewise.
* elf32-d10v.c (elf32_d10v_relocate_section): Likewise.
* elf32-epiphany.c (epiphany_elf_relocate_section): Likewise.
* elf32-fr30.c (fr30_elf_relocate_section): Likewise.
* elf32-frv.c (elf32_frv_relocate_section): Likewise.
* elf32-ft32.c (ft32_elf_relocate_section): Likewise.
* elf32-h8300.c (elf32_h8_relocate_section): Likewise.
* elf32-hppa.c (elf32_hppa_relocate_section): Likewise.
* elf32-i386.c (elf_i386_relocate_section): Likewise.
* elf32-ip2k.c (ip2k_elf_relocate_section): Likewise.
* elf32-iq2000.c (iq2000_elf_relocate_section): Likewise.
* elf32-lm32.c (lm32_elf_relocate_section): Likewise.
* elf32-m32c.c (m32c_elf_relocate_section): Likewise.
* elf32-m32r.c (m32r_elf_relocate_section): Likewise.
* elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Likewise.
* elf32-m68hc1x.h (elf32_m68hc11_relocate_section): Likewise.
* elf32-m68k.c (elf_m68k_relocate_section): Likewise.
* elf32-mcore.c (mcore_elf_relocate_section): Likewise.
* elf32-mep.c (mep_elf_relocate_section): Likewise.
* elf32-metag.c (elf_metag_relocate_section): Likewise.
* elf32-microblaze.c (microblaze_elf_relocate_section): Likewise.
* elf32-moxie.c (moxie_elf_relocate_section): Likewise.
* elf32-msp430.c (elf32_msp430_relocate_section): Likewise.
* elf32-mt.c (mt_elf_relocate_section): Likewise.
* elf32-nds32.c (nds32_elf_relocate_section): Likewise.
* elf32-nios2.c (nios2_elf32_relocate_section): Likewise.
* elf32-or1k.c (or1k_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_relocate_section): Likewise.
* elf32-pru.c (pru_elf32_relocate_section): Likewise.
* elf32-rl78.c (rl78_elf_relocate_section): Likewise.
* elf32-rx.c (rx_elf_relocate_section): Likewise.
* elf32-s390.c (elf_s390_relocate_section): Likewise.
* elf32-score.c (s3_bfd_score_elf_relocate_section): Likewise.
(_bfd_score_elf_relocate_section): Likewise.
* elf32-score.h (s7_bfd_score_elf_relocate_section): Likewise.
* elf32-score7.c (s7_bfd_score_elf_relocate_section): Likewise.
* elf32-sh.c (sh_elf_relocate_section): Likewise.
* elf32-tic6x.c (elf32_tic6x_relocate_section): Likewise.
* elf32-tilepro.c (tilepro_elf_relocate_section): Likewise.
* elf32-v850.c (v850_elf_relocate_section): Likewise.
* elf32-vax.c (elf_vax_relocate_section): Likewise.
* elf32-visium.c (visium_elf_relocate_section): Likewise.
* elf32-xc16x.c (elf32_xc16x_relocate_section): Likewise.
* elf32-xstormy16.c (xstormy16_elf_relocate_section): Likewise.
* elf32-xtensa.c (elf_xtensa_relocate_section): Likewise.
* elf32-z80.c (z80_elf_relocate_section): Likewise.
* elf64-alpha.c (elf64_alpha_relocate_section_r): Likewise.
(elf64_alpha_relocate_section): Likewise.
* elf64-bpf.c (bpf_elf_relocate_section): Likewise.
* elf64-hppa.c (elf64_hppa_relocate_section): Likewise.
* elf64-ia64-vms.c (elf64_ia64_relocate_section): Likewise.
* elf64-mmix.c (mmix_elf_relocate_section): Likewise.
* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
* elf64-s390.c (elf_s390_relocate_section): Likewise.
* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_relocate_section): Likewise.
* elfnn-ia64.c (elfNN_ia64_relocate_section): Likewise.
* elfnn-riscv.c (riscv_elf_relocate_section): Likewise.
* elfxx-mips.c (_bfd_mips_elf_relocate_section): Likewise.
* elfxx-mips.h (_bfd_mips_elf_relocate_section): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Likewise.
* elfxx-sparc.h (_bfd_sparc_elf_relocate_section): Likewise.
* elfxx-tilegx.c (tilegx_elf_relocate_section): Likewise.
* elfxx-tilegx.h (tilegx_elf_relocate_section): Likewise.
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According to the commit abd20cb637008da9d32018b4b03973e119388a0a, an
intersting thing is that - the more relax passes, the more chances of
relaxations are reduced [1]. Originally, we set the boolean `again`
to TRUE once the code is actually deleted, and then we run the relaxations
repeatedly if `again` is still TRUE. But `again` only works for the
relax pass itself, and won't affect others. That is - we can not use
`again` to re-run the relax pass when we already enter into the following
passes (can not run the relax passes backwards). Besides, we must seperate
the PCREL relaxations into two relax passes for some reasons [2], it make
us lose some relax opportunities.
This patch try to fix the problem, and the basic idea was come from Jim
Wilson - we use a new boolean, restart_relax, to determine if we need to
run the whole relax passes again from 0 to 2. Once we have deleted the
code between relax pass 0 to 2, the restart_relax will be set to TRUE,
we should run the whole relaxations again to give them more chances to
shorten the code. We will only enter into the relax pass 3 when the
restart_relax is FALSE, since we can't relax anything else once we start
to handle the alignments.
I have passed the gcc/binutils regressions by riscv-gnu-toolchain, and
looks fine for now.
[1] https://sourceware.org/pipermail/binutils/2020-November/114223.html
[2] https://sourceware.org/pipermail/binutils/2020-November/114235.html
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): New boolean restart_relax,
used to check if we need to run the whole relaxations from relax pass 0
to 2 again.
(riscv_elf_link_hash_table_create): Init restart_relax to FALSE.
(_bfd_riscv_relax_align): Remove obsolete sec_flg0 set.
(_bfd_riscv_relax_delete): Set again to TRUE if we do delete the code.
(bfd_elfNN_riscv_restart_relax_sections): New function. Called by
after_allocation to check if we need to run the whole relaxations again.
(_bfd_riscv_relax_section): We will only enter into the relax pass 3 when
the restart_relax is FALSE; At last set restart_relax to TRUE if again is
TRUE, too.
* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Declaration.
(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
* emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments many
times if riscv_restart_relax_sections returns TRUE.
* testsuite/ld-riscv-elf/restart-relax.d: New testcase. Before applying
this patch, the call won't be relaxed to jal; But now we have more chances
to do relaxations.
* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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When creating a core file GDB will call the function
elfcore_write_prstatus to write out the general purpose registers
along with the pid/tid for the thread (into a prstatus structure) and
the executable name and arguments (into a prpsinfo_t structure).
However, for a bare metal RISC-V tool chain the prstatus_t and
prpsinfo_t types are not defined so the elfcore_write_prstatus
function will return NULL, preventing core file creation.
This commit provides the `elf_backend_write_core_note' hook and uses
the provided function to write out the required information.
In order to keep changes in the non bare metal tools to a minimum, the
provided backend function will itself return NULL when the prstatus_t
or pspsinfo_t types are available, the consequence of this is that the
generic code in elfcore_write_prstatus will be used just as before.
But, when prstatus_t or prpsinfo_t is not available, the new backend
function will write out the information using predefined offsets.
This new functionality will be used by a later GDB commit that will
add bare metal core dumps for RISC-V.
bfd/ChangeLog:
* elfnn-riscv.c (PRPSINFO_PR_FNAME_LENGTH): Define.
(PRPSINFO_PR_PSARGS_LENGTH): Define.
(riscv_write_core_note): New function.
(riscv_elf_grok_psinfo): Make use of two new length defines.
(elf_backend_write_core_note): Define.
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* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM: Renamed from SBTYPE_IMM.
JTYPE_IMM: Renamed from UJTYPE_IMM.
CITYPE_IMM: Renamed from RVC_IMM.
CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM: Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM: Added for .insn without special encoding.
CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
CLTYPE_IMM: Added for .insn without special encoding.
CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
RVC_SIMM3: Unused and removed.
CBTYPE_IMM: Renamed from RVC_B_IMM.
CJTYPE_IMM: Renamed from RVC_J_IMM.
* Added new operands and removed the unused ones,
C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.
bfd/
PR 27158
* elfnn-riscv.c (perform_relocation): Updated encoding macros.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
gas/
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
gdb/
PR 27158
* riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
(decode_j_type_insn): Likewise.
(decode_cj_type_insn): Likewise.
(decode_b_type_insn): Likewise.
(decode): Likewise.
include/
PR 27158
* opcode/riscv.h: Updated encoding macros.
opcodes/
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
sim/
PR 27158
* riscv/sim-main.c (execute_i): Updated encoding macros.
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Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use. To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.
bfd/
* Makefile.am: Added cpu-riscv.h.
* Makefile.in: Regenerated.
* po/SRC-POTFILES.in: Regenerated.
* cpu-riscv.h: Added to support spec versions controlling.
Also added extern arrays and functions for cpu-riscv.c.
(enum riscv_spec_class): Define all spec classes here uniformly.
(struct riscv_spec): Added for all specs.
(RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
(RISCV_GET_SPEC_NAME): Likewise.
(RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
(RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
(RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
* cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
(riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
(riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
(riscv_priv_specs): Moved below.
(riscv_get_priv_spec_class_from_numbers): Likewise, updated.
(riscv_isa_specs): Moved from include/opcode/riscv.h.
* elfnn-riscv.c: Included cpu-riscv.h.
(riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
* elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
(RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
* elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
* config/tc-riscv.c: Included cpu-riscv.h.
(enum riscv_csr_clas): Moved from include/opcode/riscv.h.
(struct riscv_csr_extra): Likewise.
(struct riscv_ext_version): Likewise.
(ext_version_table): Moved from opcodes/riscv-opc.c.
(default_isa_spec): Updated type to riscv_spec_class.
(default_priv_spec): Likewise.
(riscv_set_default_isa_spec): Updated.
(init_ext_version_hash): Likewise.
(riscv_init_csr_hash): Likewise, also fixed indent.
include/
* opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
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RISC-V only defines two float ABIs, soft-float and double-float, and the
value of soft-float is 0x0. But 0x0 usually means unknown/default setting
for many targets, and the non-ABI binary, which is generated by "ld/objcopy
-b binary", also has the 0x0 elf header flags, this may be confused.
We probably can define a new unknown/default ABI value to make them more
clear, but that will need more bits in the elf header flags, and also need
to discuss in the riscv psabi spec.
Training linker have a default ABI setting, and can be changed by ld
options or configure options is another solution, like what assemblr
usually do. So all objects, including the binary files, will have
explicit ABI setting. But the binary files will no longer be linked
with any object, users need to recompile them with the exactly ABI
they want. It may be inconvenience sometimes. Besides, I think linker
doesn't need to know the default arch/abi so far, just set them according
to the linked objects should be enough.
Therefore, without changing the riscv psabi, and keep the non-ABI binary
can be linked with any object, we don't check the ABI flags if no code
section in the PR24389. Just that we find the first input non-ABI binary
still cannot be linked with others in the PR27200. This patch fixs the
problem by delaying the elf_flags_init(obfd) check, since the flags of
non-ABI object with no code cannot be copyed to output BFD, we should
skip it, even if it is the first linked object.
However, there is a strange "break" at the end of loop in the PR24389.
The "break" cause the ld testcase "Link with zlib-gabi compressed debug
output 1" fails for rv64gc-linux toolchain, after applying the above
change. The root cause is that - the "break" make linker only checks
the "first" section of input BFD rather than the entire sections.
I have checked that AARCH64 and ARM both have the "break" at the end
of loop, but ARC doesn't. I suppose we should remove the "break" like
what ARC do, or use a pair of braces for the if statement.
I have passed the elf/linux toolchain regressions, so the change should
be fine.
bfd/
PR 27200
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Delay
copying the elf flags from input BFD to output BFD, until we have
checked if the input BFD has no code section or not. Also fix the
problem that we only check the first section rather than the entire
sections for input BFD.
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bfd/
* elfnn-riscv.c (riscv_relax_delete_bytes): Fixed the indent that
caused by the previous commit accidentally.
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bfd/
* elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
also aligned the code.
gas/
* config/tc-riscv.c: Indent and GNU coding standards tidy,
also aligned the code.
* config/tc-riscv.h: Likewise.
include/
* opcode/riscv.h: Indent and GNU coding standards tidy,
also aligned the code.
opcodes/
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
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Error and warning messages usually starting with lower case letter,
and without the period at the end. Besides, add the prefixed "internel:"
at the beginning of the messages when they are caused internally.
Also fix indents and typos.
bfd/
* elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages.
gas/
* config/tc-riscv.c: Error and warning messages tidy.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Updated.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
opcodes/
* riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
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The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces. But sometimes it should be more
cleaner when the comments only include a word or codes. Therefore, I made
the following changes after referring to other target/generic codes,
* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.
Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.
bfd/
* elfnn-riscv.c: Comments tidy and improvement.
* elfxx-riscv.c: Likewise.
* elfxx-riscv.h: Likewise.
gas/
* config/tc-riscv.c: Comments tidy and improvement. Also update
comment "fallthru" to "Fall through" that end with a period and
two spaces.
include/
* elf/riscv.h: Comments tidy and improvement.
* opcode/riscv-opc.h: Likewise.
* opcode/riscv.h: Likewise.
opcodes/
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
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RISC-V instruction/code is always little endian, but data might be
big-endian. Therefore, we can not use the original bfd_get/bfd_put
to get/put the code for big endian targets. Add new riscv_get_insn
and riscv_put_insn to always get/put code as little endian can resolve
the problem. Just remember to update them once we have supported
the 48-bit/128-bit instructions in the future patches.
bfd/
* config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and
riscvbe*-*-*. Also added riscv_elf[32|64]_be_vec.
* configure.ac: Handle riscv_elf[32|64]_be_vec.
* configure: Regenerate.
* elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for
riscv_is_insn_reloc.
(riscv_get_insn): RISC-V instructions are always little endian, but
bfd_get may be used for big-endian, so add new riscv_get_insn to handle
the insturctions.
(riscv_put_insn): Likewsie.
(riscv_is_insn_reloc): Check if we are relocaing an instruction.
(perform_relocation): Call riscv_is_insn_reloc to decide if we should
use riscv_[get|put]_insn or bfd_[get|put].
(riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32
or bfd_[get|put]l16 for code.
(riscv_elf_relocate_section): Likewise.
(riscv_elf_finish_dynamic_symbol): Likewise.
(riscv_elf_finish_dynamic_sections): Likewise.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_pc): Likewise.
(riscv_elf_object_p): Handled for big endian.
(TARGET_BIG_SYM, TARGET_BIG_NAME): Defined.
* targets.c: Add riscv_elf[32|64]_be_vec.
(_bfd_target_vector): Likewise.
gas/
* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
elf32-bigriscv.
(install_insn): Always write instructions as little endian.
(riscv_make_nops): Likewise.
(md_convert_frag_branch): Likewise.
(md_number_to_chars): Write data in target endianness.
(options, md_longopts): Add -mbig-endian and -mlittle-endian options.
(md_parse_option): Handle the endian options.
* config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
already defined.
* configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.
ld/
* configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
riscv32be*-*-linux*, and riscv64be*-*-linux*.
* Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and
eelf32briscv_ilp32.c.
* Makefile.in: Regenerate.
* emulparams/elf32briscv.sh: Added.
* emulparams/elf32briscv_ilp32.sh: Likewise.
* emulparams/elf32briscv_ilp32f.sh: Likewise.
* emulparams/elf64briscv.sh: Likewise.
* emulparams/elf64briscv_lp64.sh: Likewise.
* emulparams/elf64briscv_lp64f.sh: Likewise.
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When the ifunc resolver is in the executable, we may relax the variables
to gp-relative access instruction in the ifunc resolver, or in other functions
that called by the ifunc resolver. But this will cause the uninitialized
gp problem since the ifunc need to be resolved at the early runtime, that
is at the pre-load stage, but we set the gp until the startup code.
At first, we try to add a new dynamic tag, DT_RISCV_GP, to stroe the gp value
and let ld.so can init the gp register early, before the pre-load stage. But
we need to extend the ABI if we want to add a new dynamic tag. Therefore,
in the psabi discussion, we try another solution, which was suggested by the
lld and FreeBSD linker experts, to let ld.so set the gp earlier - make sure
__global_pointer$ is output as a dynamic symbol when we are generating pde,
since we only do the relaxation for it. Afterwards, ld.so can search the
DT_SYMTAB to get the gp value, and set the gp register before resolving ifunc.
bfd/
* elfnn-riscv.c (allocate_dynrelocs): When we are generating pde, make
sure gp symbol is output as a dynamic symbol.
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Similar to the commit 6729e2c2af2bd94408430734316597843718a484,
we have to check the first char of the Z* extensions, to make
sure that they follow the order of the standard extensions.
bfd/
* elfxx-riscv.c (riscv_compare_subsets): Removed static.
* elfxx-riscv.h: Add declaration.
* elfnn-riscv.c (riscv_merge_multi_letter_ext): Use
riscv_compare_subsets to check the orders.
(riscv_skip_prefix): Removed.
(riscv_prefix_cmp): Removed.
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We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions. That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions. For now we
follow the following rules to add the implicit extensions,
* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.
Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.
bfd/
* elfnn-riscv.c (riscv_merge_std_ext): Updated since
riscv_lookup_subset is changed.
* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
extensions' order quickly.
(riscv_init_ext_order): New function. Init the riscv_ext_order
according to the riscv_supported_std_ext and parse_config[i].class
automatically.
(riscv_compare_subsets): New function. Similar to the strcmp, but
compare the subsets with the specific order.
(riscv_lookup_subset): Return TRUE and set `current` to the subset
if it is found. Otherwise, return FALSE and set `current` to the
place where we should insert the subset.
(riscv_add_implicit_subset): New function. Search the list first,
and then find the right place to add the implicit_subset.
(riscv_parse_add_subset): Since We have to add all arch string
extensions first, and then start to add their implicit extensions.
We can add arch string extensions in order by the original
riscv_add_subset, and then add the implicit subsets by the
riscv_add_implicit_subset. Besides, do not add the implicit
extensions if we failed to find their default versions.
(riscv_parse_std_ext): Updated.
(riscv_parse_add_implicit_subsets): New function. Add all implicit
extensions according to the arch string extensions.
(riscv_parse_subset): Call riscv_init_ext_order and
riscv_parse_add_implicit_subsets, before and after parsing the
arch string. Remove parts of the ISA conflict checking since
the implicit extensions are added.
* elfxx-riscv.h (riscv_lookup_subset): Updated.
gas/
* config/tc-riscv.c (riscv_subset_supports): Updated.
* testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to
add the implicit zicsr and zifencei when i's version less than 2.1.
* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
* testsuite/gas/riscv/march-imply-d.d: Likewise.
* testsuite/gas/riscv/march-imply-f.d: Likewise.
* testsuite/gas/riscv/march-imply-q.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
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I get the feedback recently that enable linker relaxations may fail to
build some program. Consider the following case,
.text
foo:
addi a0, a0, %pcrel_lo(.L2)
call foo
.L1: auipc a1, %pcrel_hi(data_g)
addi a1, a1, %pcrel_lo(.L1)
lui a2, %hi(data_g)
addi a2, a2, %lo(data_g)
lui a3, %tprel_hi(data_t)
add a3, a3, tp, %tprel_add(data_t)
addi a3, a3, %tprel_lo(data_t)
.L2: auipc a0, %pcrel_hi(data_g)
.data
.word 0x0
.global data_g
data_g: .word 0x1
.section .tbss
data_t: .word 0x0
The current ld reports `dangerous relocation error` when doing the
pcgp relaxation,
test.o: in function `foo':
(.text+0x0): dangerous relocation: %pcrel_lo missing matching %pcrel_hi
The .L2 auipc should not be removed since it is behind the corresponding
addi, so we record the information in the pcgp_relocs table to avoid
removing the auipc later. But current ld still remove it since we do not
update the pcgp_relocs table while doing other relaxations. I have two
solutions to fix the problem,
1. Update the pcgp_relocs table once we actually delete the code.
2. Add new relax pass to do the pcgp relaxations
At first I tried to do the first solution, and we need to update at
least three information - hi_sec_off of riscv_pcgp_lo_reloc, hi_sec_off
and hi_addr (symbol value) of riscv_pcgp_hi_reloc. Update the hi_sec_off
is simple, but it is more complicate to update the symbol value, since we
almost have to do parts the same works of _bfd_riscv_relax_call again in
the riscv_relax_delete_bytes to get the correct symbol value.
Compared with the first solution, the second one is more intuitive and
simple. We add a new relax pass to do the pcgp relaxations later, so
we will get all the information correctly in the _bfd_riscv_relax_call,
including the symbol value, without changing so much code. I do not see
any penalty by adding a new relax pass for now, so it should be fine
to delay the pcgp relaxations.
Besides, I have pass all riscv-gnu-toolchain regressions for this patch.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_section): Add a new relax pass
to do the pcgp relaxation later, after the lui and call relaxations,
but before the delete and alignment relaxations.
ld/
* emultempl/riscvelf.em (riscv_elf_before_allocation): Change
link_info.relax_pass from 3 to 4.
* testsuite/ld-riscv-elf/pcgp-relax.d: New testcase.
* testsuite/ld-riscv-elf/pcgp-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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For the ifunc symbol, which is referenced by GOT rather than PLT relocs,
we should add the dynamic reloc (usually IRELATIVE) into the .rel.iplt
when generating the static executable. But if we use riscv_elf_append_rela
to add the dynamic relocs into .rela.iplt, this may cause the overwrite
problem.
The reason is that we don't handle the `reloc_index` of .rela.iplt, but
the riscv_elf_append_rela adds the relocs to the place that are calculated
from the reloc_index (in seqential). Therefore, we may overwrite the
dynamic relocs when the `reloc_index` of .rela.iplt isn't handled correctly.
One solution is that we can add these dynamic relocs (GOT ifunc) from
the last of .rela.iplt section. But I'm not sure if it is the best way.
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Add last_iplt_index.
(riscv_elf_size_dynamic_sections): Initialize the last_iplt_index.
(riscv_elf_relocate_section): Use riscv_elf_append_rela.
(riscv_elf_finish_dynamic_symbol): If the use_elf_append_rela is
false, then we should add the dynamic relocs from the last of
the .rela.iplt, and don't use the riscv_elf_append_rela to add.
ld/
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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Generally, glibc dynamic linker should have two ways to deal with ifunc
- one is to handle the IRELATIVE relocations for the non-preemtive ifunc
symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT
relocations with the STT_IFUNC preemtive symbols. No matter which method
is used, both of them should get the resolved ifunc symbols at runtime.
Therefore, linker needs to generate the correct dynamic relocations for
ifunc to make sure the the dynamic linker works well. For now, there are
thirteen relocations are supported for ifunc in GNU ld,
* R_RISCV_CALL and R_RISCV_CALL_PLT:
The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an
ifunc. Besides, we disable the relaxations for the relocation referenced
to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be
enough. Linker should generate a .plt entry and a .got.plt entry for it,
and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or
insert a R_RISCV_JUMP_SLOT when generating shared library.
* R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S:
LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol.
The PC-relative relocation. The current linker will deal with them in
the same way as R_RISCV_CALL_PLT.
* R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S:
LA pattern with global PIC ifunc symbol. Linker should insert a dynamic
IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating
shared library.
* R_RISCV_32 and R_RISCV_64:
Store the ifunc symbol into the data section. Linker should insert a
dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when
generating shared library.
* R_RISCV_HI20 and R_RISCV_LO12_I/S:
The LUI + ADDI/LW/SW patterns. The absolute access relocation. The
medlow model without the -fPIC compiler option should generate them.
The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the
relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler
support.
However, we also made some optimizations with reference to x86,
* If GOT and PLT relocations refer to the same ifunc symbol when generating
pie, then they can actually share a .got entry without creating two entries
to store the same value and relocation.
* If GOT, PLT and DATA relocations refer to the same ifunc symbol when
generating position dependency executable, then linker will fill the address
of .plt entry into the corresponding .got entry and data section, without
insert any dynamic relocations for the GOT and DATA relocations.
For the ifunc testcases, there are three types of them,
1. ifunc-reloc-*: Only check the single type of relocation refers to
ifunc symbol.
* ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT.
* ifunc-reloc-data: R_RISCV_32 and R_RISCV_64.
* ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S.
* ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S.
2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to
create the PLT and it's .plt entries.
* ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64.
* ifunc-plt: Combine all ifunc relocations.
3. ifunc-seperate-*: If we link the ifunc caller and resolver into the
same module (link the objects), then the results are the same as the
ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that
the ifunc callers and resolver are in the different modules, that is, we
compile the ifunc resolver to the shared library first, and then link it
with the ifunc callers. The output of ifunc callers should be the same as
the normal STT_FUNC cases, and the shared ifunc resolver should define the
symbols as STT_IFUNC.
The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved
locally, so if the ifunc resolver is defined in other modules (other shared
libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should
issue an unresolvable reloc error.
bfd/
* elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc.
(riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory
for local STT_GNU_IFUNC symbols.
(riscv_elf_got_plt_val): Removed.
(riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions.
Use to compare local hash entries.
(riscv_elf_get_local_sym_hash): New function. Find a hash entry for
local symbol, and create a new one if needed.
(riscv_elf_link_hash_table_free): New function. Destroy an riscv
elf linker hash table.
(riscv_elf_link_hash_table_create): Create hash table for local ifunc.
(riscv_elf_check_relocs): Create a fake global symbol to track the
local ifunc symbol. Add support to check and handle the relocations
reference to ifunc symbols.
(allocate_dynrelocs): Let allocate_ifunc_dynrelocs and
allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they
are defined and referenced in a non-shared object.
(allocate_ifunc_dynrelocs): New function. Allocate space in .plt,
.got and associated reloc sections for ifunc dynamic relocs.
(allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc
dynamic relocs.
(riscv_elf_relocate_section): Add support to handle the relocation
referenced to ifunc symbols.
(riscv_elf_size_dynamic_sections): Updated.
(riscv_elf_adjust_dynamic_symbol): Updated.
(riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling,
including fill the PLT and GOT entries for ifunc symbols.
(riscv_elf_finish_local_dynamic_symbol): New function. Called by
riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols.
(_bfd_riscv_relax_section): Don't do the relaxation for ifunc.
* elfxx-riscv.c: Add R_RISCV_IRELATIVE.
* configure.ac: Link elf-ifunc.lo to use the generic ifunc support.
* configure: Regenerated.
include/
* elf/riscv.h: Add R_RISCV_IRELATIVE to 58.
ld/
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
New dump test for ifunc. There are two arguments, 'target` and
`output`. The `target` is rv32 or rv64, and the `output` is used
to choose which output you want to test (exe, pie or .so).
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
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bfd/
* elfnn-riscv.c (riscv_i_or_e_p): Minor cleanup for warnings/errors.
(riscv_merge_std_ext): Likewise.
(riscv_merge_arch_attr_info): Likewise.
(riscv_merge_attributes): Likewise and fix comment typos.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Remove
the useless `warnings` keywords.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
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Same as the privileged spec attributes check - different ISA versions
should be compatible, unless there are some known conflicts. Therefore,
we should allow to link objects with different ISA versions, and update
the output ISA versions once the corresponding input ones are newer.
But it's better to also warn people that the conflicts may happen when
the ISA versions are mis-matched.
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Change the return type
from void to bfd_boolean. Report warnings rather than errors
when the ISA versions are mis-matched. Afterwards, remember to
update the output ISA versions to the newest ones.
(riscv_merge_std_ext): Allow to link objects with different
standard ISA versions. Try to add output ISA versions to
merged_subsets first.
(riscv_merge_multi_letter_ext): Likewise. But for standard additional
ISA and non-standard ISA versions.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update the
message from error to warning.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: New testcases.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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Consider the updated attr-merge-arch-failed-01.d testcase. Extension
A's version are mis-matched between attr-merge-arch-failed-01a.s and
attr-merge-arch-failed-01b.s. But the old binutils reports that the
mis-matched extension is M rather than A. This commit is used to fix
the wrong mis-matched error message.
Besides, when parsing the arch string in the riscv_parse_subset, it
shouldn't be NULL or empty. However, it might be empty when we failed
to merge the arch string in the riscv_merge_attributes. Since we should
already issue the correct error message in another side, and the message
- ISA string must begin with rv32 or rv64 - is meaninglesss when the arch
string is empty, so do not issue it.
bfd/
* elfnn-riscv.c (riscv_merge_std_ext): Fix to report the correct
error message when the versions of extension are mis-matched.
* elfxx-riscv.c (riscv_parse_subset): Don't issue the error when
the string is empty.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise.
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include/
PR 26493
* opcode/riscv.h (OP_MASK_CSR, OP_MASK_CUSTOM_IMM)
(OP_MASK_FUNCT7, OP_MASK_RS3): Make unsigned.
bfd/
PR 26493
* elfnn-riscv.c (riscv_make_plt_header): Cast PLT_HEADER_SIZE to
unsigned when using with RISCV_ITYPE.
(_bfd_riscv_relax_call): Use an unsigned foff.
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In fact, we can treate these two relocation as the same one in the
riscv_elf_check_relocs. I have heard that RISC-V lld had made this
improvement, and so had GNU AARCH64, they only need R_AARCH64_CALL26
for calls rather than two seperate relocations.
Beside, the following PLT issue for RISC-V 32-bit glibc seems to be
fixed by applying at least this patch.
<https://sourceware.org/pipermail/libc-alpha/2020-August/117214.html>
I have ran the toolchain regression, and everything seems fine for now.
bfd/
* elfnn-riscv.c (riscv_elf_check_relocs): Treat R_RISCV_CALL
and R_RISCV_CALL_PLT as the same in the riscv_elf_check_relocs.
(riscv_elf_relocate_section): Remove the R_RISCV_CALL for the
unresolved reloc checks.
ld/
testsuite/ld-riscv-elf/lib-nopic-01a.s: Use R_RISCV_JAL rather
than R_RISCV_CALL.
testsuite/ld-riscv-elf/lib-nopic-01b.d: Likewise.
testsuite/ld-riscv-elf/lib-nopic-01b.s: Likewise.
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* elf-m10300.c (elf32_mn10300_hash_table): Test is_elf_hash_table
before accessing elf_hash_table_id.
* elf32-arc.c (elf_arc_hash_table): Likewise.
* elf32-arm.c (elf32_arm_hash_table): Likewise.
* elf32-avr.c (avr_link_hash_table): Likewise.
* elf32-bfin.c (bfinfdpic_hash_table): Likewise.
* elf32-cris.c (elf_cris_hash_table): Likewise.
* elf32-csky.c (csky_elf_hash_table): Likewise.
* elf32-frv.c (frvfdpic_hash_table): Likewise.
* elf32-hppa.c (hppa_link_hash_table): Likewise.
* elf32-lm32.c (lm32_elf_hash_table): Likewise.
* elf32-m32r.c (m32r_elf_hash_table): Likewise.
* elf32-m68hc1x.h (m68hc11_elf_hash_table): Likewise.
* elf32-m68k.c (elf_m68k_hash_table): Likewise.
* elf32-metag.c (metag_link_hash_table): Likewise.
* elf32-microblaze.c (elf32_mb_hash_table): Likewise.
* elf32-nds32.h (nds32_elf_hash_table): Likewise.
* elf32-or1k.c (or1k_elf_hash_table): Likewise.
* elf32-s390.c (elf_s390_hash_table): Likewise.
* elf32-sh.c (sh_elf_hash_table): Likewise.
* elf32-spu.c (spu_hash_table): Likewise.
* elf32-tilepro.c (tilepro_elf_hash_table): Likewise.
* elf32-xtensa.c (elf_xtensa_hash_table): Likewise.
* elf64-alpha.c (alpha_elf_hash_table): Likewise.
* elf64-hppa.c (hppa_link_hash_table): Likewise.
* elf64-ia64-vms.c (elf64_ia64_hash_table): Likewise.
* elf64-s390.c (elf_s390_hash_table): Likewise.
* elfnn-ia64.c (elfNN_ia64_hash_table): Likewise.
* elfnn-riscv.c (riscv_elf_hash_table): Likewise.
* elfxx-mips.c (mips_elf_hash_table): Likewise.
* elfxx-sparc.h (_bfd_sparc_elf_hash_table): Likewise.
* elfxx-tilegx.c (tilegx_elf_hash_table): Likewise.
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